Collaboration diagram for STM8AF_STM8S:

Data Structures
struct	PORT_t
	structure for controlling pins in PORT mode (PORTx, x=A..I) More...

struct	FLASH_t
	struct to control write/erase of flash memory (FLASH) More...

struct	EXTI_t
	struct for configuring external port interrupts (EXTI) More...

struct	RST_t
	struct for determining reset source (RST) More...

struct	CLK_t
	struct for configuring/monitoring clock module (CLK) More...

struct	WWDG_t
	struct for access to Window Watchdog registers (WWDG) More...

struct	IWDG_t
	struct for access to Independent Timeout Watchdog registers (IWDG) More...

struct	AWU_t
	struct for cofiguring the Auto Wake-Up Module (AWU) More...

struct	BEEP_t
	struct for beeper control (BEEP) More...

struct	SPI_t
	struct for controlling SPI module (SPI) More...

struct	I2C_t
	struct for controlling I2C module (I2C) More...

struct	UART1_t
	struct for controlling Universal Asynchronous Receiver Transmitter 1 (UART1) More...

struct	UART2_t
	struct for controlling Universal Asynchronous Receiver Transmitter 2 (UART2) More...

struct	UART3_t
	struct for controlling Universal Asynchronous Receiver Transmitter 3 (UART3) More...

struct	UART4_t
	struct for controlling Universal Asynchronous Receiver Transmitter 4 (UART4) More...

struct	TIM1_t
	struct for controlling 16-Bit Timer 1 (TIM1) More...

struct	TIM2_t
	struct for controlling 16-Bit Timer 2 (TIM2) More...

struct	TIM3_t
	struct for controlling 16-Bit Timer 3 (TIM3) More...

struct	TIM4_t
	struct for controlling 8-Bit Timer 4 (TIM4) More...

struct	TIM5_t
	struct for controlling 16-Bit Timer 5 (TIM5) More...

struct	TIM6_t
	struct for controlling 8-Bit Timer 6 (TIM6) More...

struct	ADC1_t
	struct containing Analog Digital Converter 1 (ADC1) More...

struct	ADC2_t
	struct containing Analog Digital Converter 2 (ADC2) More...

struct	CAN_t
	struct for controlling Controller Area Network Module (CAN) More...

struct	CFG_t
	struct for Global Configuration registers (CFG) More...

struct	ITC_t
	struct for setting interrupt Priority (ITC) More...

Macros
#define	STM8AF5268

#define	STM8AF526x

#define	STM8_PFLASH_SIZE 32768

#define	STM8_RAM_SIZE 6144

#define	STM8_EEPROM_SIZE 1024

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	PORTH_AddressBase 0x5023

#define	PORTI_AddressBase 0x5028

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	UART3_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC2_AddressBase 0x5400

#define	CAN_AddressBase 0x5420

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	STM8AF5269

#define	STM8AF526x

#define	STM8_PFLASH_SIZE 32768

#define	STM8_RAM_SIZE 6144

#define	STM8_EEPROM_SIZE 1024

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	PORTH_AddressBase 0x5023

#define	PORTI_AddressBase 0x5028

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	UART3_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC2_AddressBase 0x5400

#define	CAN_AddressBase 0x5420

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	STM8AF5286

#define	STM8AF528x

#define	STM8_PFLASH_SIZE 65536

#define	STM8_RAM_SIZE 6144

#define	STM8_EEPROM_SIZE 2048

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	PORTH_AddressBase 0x5023

#define	PORTI_AddressBase 0x5028

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	UART3_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC2_AddressBase 0x5400

#define	CAN_AddressBase 0x5420

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	STM8AF5288

#define	STM8AF528x

#define	STM8_PFLASH_SIZE 65536

#define	STM8_RAM_SIZE 6144

#define	STM8_EEPROM_SIZE 2048

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	PORTH_AddressBase 0x5023

#define	PORTI_AddressBase 0x5028

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	UART3_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC2_AddressBase 0x5400

#define	CAN_AddressBase 0x5420

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	STM8AF5289

#define	STM8AF528x

#define	STM8_PFLASH_SIZE 65536

#define	STM8_RAM_SIZE 6144

#define	STM8_EEPROM_SIZE 2048

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	PORTH_AddressBase 0x5023

#define	PORTI_AddressBase 0x5028

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	UART3_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC2_AddressBase 0x5400

#define	CAN_AddressBase 0x5420

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	STM8AF528A

#define	STM8AF528x

#define	STM8_PFLASH_SIZE 65536

#define	STM8_RAM_SIZE 6144

#define	STM8_EEPROM_SIZE 2048

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	PORTH_AddressBase 0x5023

#define	PORTI_AddressBase 0x5028

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	UART3_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC2_AddressBase 0x5400

#define	CAN_AddressBase 0x5420

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	STM8AF52A6

#define	STM8AF52Ax

#define	STM8_PFLASH_SIZE 131072

#define	STM8_RAM_SIZE 6144

#define	STM8_EEPROM_SIZE 2048

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	PORTH_AddressBase 0x5023

#define	PORTI_AddressBase 0x5028

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	UART3_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC2_AddressBase 0x5400

#define	CAN_AddressBase 0x5420

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	STM8AF52A8

#define	STM8AF52Ax

#define	STM8_PFLASH_SIZE 131072

#define	STM8_RAM_SIZE 6144

#define	STM8_EEPROM_SIZE 2048

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	PORTH_AddressBase 0x5023

#define	PORTI_AddressBase 0x5028

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	UART3_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC2_AddressBase 0x5400

#define	CAN_AddressBase 0x5420

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	STM8AF52A9

#define	STM8AF52Ax

#define	STM8_PFLASH_SIZE 131072

#define	STM8_RAM_SIZE 6144

#define	STM8_EEPROM_SIZE 2048

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	PORTH_AddressBase 0x5023

#define	PORTI_AddressBase 0x5028

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	UART3_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC2_AddressBase 0x5400

#define	CAN_AddressBase 0x5420

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	STM8AF52AA

#define	STM8AF52Ax

#define	STM8_PFLASH_SIZE 131072

#define	STM8_RAM_SIZE 6144

#define	STM8_EEPROM_SIZE 2048

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	PORTH_AddressBase 0x5023

#define	PORTI_AddressBase 0x5028

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	UART3_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC2_AddressBase 0x5400

#define	CAN_AddressBase 0x5420

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	STM8AF6213

#define	STM8AF621x

#define	STM8_PFLASH_SIZE 4096

#define	STM8_RAM_SIZE 1024

#define	STM8_EEPROM_SIZE 640

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART4_AddressBase 0x5230

#define	TIM1_AddressBase 0x5250

#define	TIM5_AddressBase 0x5300

#define	TIM6_AddressBase 0x5340

#define	ADC1_AddressBase 0x53E0

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	STM8AF6213A

#define	STM8AF621x

#define	STM8_PFLASH_SIZE 4096

#define	STM8_RAM_SIZE 1024

#define	STM8_EEPROM_SIZE 640

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART4_AddressBase 0x5230

#define	TIM1_AddressBase 0x5250

#define	TIM5_AddressBase 0x5300

#define	TIM6_AddressBase 0x5340

#define	ADC1_AddressBase 0x53E0

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	STM8AF6223

#define	STM8AF622x

#define	STM8_PFLASH_SIZE 8192

#define	STM8_RAM_SIZE 1024

#define	STM8_EEPROM_SIZE 640

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART4_AddressBase 0x5230

#define	TIM1_AddressBase 0x5250

#define	TIM5_AddressBase 0x5300

#define	TIM6_AddressBase 0x5340

#define	ADC1_AddressBase 0x53E0

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	STM8AF6223A

#define	STM8AF622x

#define	STM8_PFLASH_SIZE 8192

#define	STM8_RAM_SIZE 1024

#define	STM8_EEPROM_SIZE 640

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART4_AddressBase 0x5230

#define	TIM1_AddressBase 0x5250

#define	TIM5_AddressBase 0x5300

#define	TIM6_AddressBase 0x5340

#define	ADC1_AddressBase 0x53E0

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	STM8AF6226

#define	STM8AF622x

#define	STM8_PFLASH_SIZE 8192

#define	STM8_RAM_SIZE 2048

#define	STM8_EEPROM_SIZE 640

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART4_AddressBase 0x5230

#define	TIM1_AddressBase 0x5250

#define	TIM5_AddressBase 0x5300

#define	TIM6_AddressBase 0x5340

#define	ADC1_AddressBase 0x53E0

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	STM8AF6246

#define	STM8AF624x

#define	STM8_PFLASH_SIZE 16384

#define	STM8_RAM_SIZE 2048

#define	STM8_EEPROM_SIZE 512

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART2_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC1_AddressBase 0x53E0

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	STM8AF6248

#define	STM8AF624x

#define	STM8_PFLASH_SIZE 16384

#define	STM8_RAM_SIZE 2048

#define	STM8_EEPROM_SIZE 512

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART2_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC1_AddressBase 0x53E0

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	STM8AF6266

#define	STM8AF626x

#define	STM8_PFLASH_SIZE 32768

#define	STM8_RAM_SIZE 2048

#define	STM8_EEPROM_SIZE 1024

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART2_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC1_AddressBase 0x53E0

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	STM8AF6268

#define	STM8AF626x

#define	STM8_PFLASH_SIZE 32768

#define	STM8_RAM_SIZE 2048

#define	STM8_EEPROM_SIZE 1024

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART2_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC1_AddressBase 0x53E0

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	STM8AF6269

#define	STM8AF626x

#define	STM8_PFLASH_SIZE 32768

#define	STM8_RAM_SIZE 6144

#define	STM8_EEPROM_SIZE 1024

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART2_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC1_AddressBase 0x53E0

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	STM8AF6286

#define	STM8AF628x

#define	STM8_PFLASH_SIZE 65536

#define	STM8_RAM_SIZE 6144

#define	STM8_EEPROM_SIZE 2048

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	PORTH_AddressBase 0x5023

#define	PORTI_AddressBase 0x5028

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	UART3_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC2_AddressBase 0x5400

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	STM8AF6288

#define	STM8AF628x

#define	STM8_PFLASH_SIZE 65536

#define	STM8_RAM_SIZE 6144

#define	STM8_EEPROM_SIZE 2048

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	PORTH_AddressBase 0x5023

#define	PORTI_AddressBase 0x5028

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	UART3_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC2_AddressBase 0x5400

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	STM8AF6289

#define	STM8AF628x

#define	STM8_PFLASH_SIZE 65536

#define	STM8_RAM_SIZE 6144

#define	STM8_EEPROM_SIZE 2048

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	PORTH_AddressBase 0x5023

#define	PORTI_AddressBase 0x5028

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	UART3_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC2_AddressBase 0x5400

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	STM8AF628A

#define	STM8AF628x

#define	STM8_PFLASH_SIZE 65536

#define	STM8_RAM_SIZE 6144

#define	STM8_EEPROM_SIZE 2048

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	PORTH_AddressBase 0x5023

#define	PORTI_AddressBase 0x5028

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	UART3_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC2_AddressBase 0x5400

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	STM8AF62A6

#define	STM8AF62Ax

#define	STM8_PFLASH_SIZE 131072

#define	STM8_RAM_SIZE 6144

#define	STM8_EEPROM_SIZE 2048

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	PORTH_AddressBase 0x5023

#define	PORTI_AddressBase 0x5028

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	UART3_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC2_AddressBase 0x5400

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	STM8AF62A8

#define	STM8AF62Ax

#define	STM8_PFLASH_SIZE 131072

#define	STM8_RAM_SIZE 6144

#define	STM8_EEPROM_SIZE 2048

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	PORTH_AddressBase 0x5023

#define	PORTI_AddressBase 0x5028

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	UART3_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC2_AddressBase 0x5400

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	STM8AF62A9

#define	STM8AF62Ax

#define	STM8_PFLASH_SIZE 131072

#define	STM8_RAM_SIZE 6144

#define	STM8_EEPROM_SIZE 2048

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	PORTH_AddressBase 0x5023

#define	PORTI_AddressBase 0x5028

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	UART3_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC2_AddressBase 0x5400

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	STM8AF62AA

#define	STM8AF62Ax

#define	STM8_PFLASH_SIZE 131072

#define	STM8_RAM_SIZE 6144

#define	STM8_EEPROM_SIZE 2048

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	PORTH_AddressBase 0x5023

#define	PORTI_AddressBase 0x5028

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	UART3_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC2_AddressBase 0x5400

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	STM8AF6366

#define	STM8AF636x

#define	STM8_PFLASH_SIZE 32768

#define	STM8_RAM_SIZE 2048

#define	STM8_EEPROM_SIZE 1024

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART2_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC1_AddressBase 0x53E0

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	STM8AF6388

#define	STM8AF638x

#define	STM8_PFLASH_SIZE 65536

#define	STM8_RAM_SIZE 6144

#define	STM8_EEPROM_SIZE 2048

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	PORTH_AddressBase 0x5023

#define	PORTI_AddressBase 0x5028

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	UART3_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC2_AddressBase 0x5400

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	STM8_PFLASH_SIZE 2048
	size of program flash [B] More...

#define	STM8_RAM_SIZE 1024
	size of RAM [B] More...

#define	STM8_EEPROM_SIZE 128
	size of data EEPROM [B] More...

#define	STM8_PFLASH_START 0x8000
	first address in program flash More...

#define	STM8_PFLASH_END (STM8_PFLASH_START + STM8_PFLASH_SIZE - 1)
	last address in program flash More...

#define	STM8_RAM_START 0x0000
	first address in RAM More...

#define	STM8_RAM_END (STM8_RAM_START + STM8_RAM_SIZE - 1)
	last address in RAM More...

#define	STM8_EEPROM_START 0x4000
	first address in EEPROM More...

#define	STM8_EEPROM_END (STM8_EEPROM_START + STM8_EEPROM_SIZE - 1)
	last address in EEPROM More...

#define	STM8_ADDR_WIDTH 16
	width of address space More...

#define	STM8_MEM_POINTER_T uint16_t
	address variable type More...

#define	ISR_HANDLER(func, irq) void func(void) __interrupt(irq)
	handler for interrupt service routine More...

#define	ISR_HANDLER_TRAP(func) void func() __trap
	handler for trap service routine More...

#define	NOP() __asm__("nop")
	perform a nop() operation (=minimum delay) More...

#define	DISABLE_INTERRUPTS() __asm__("sim")
	disable interrupt handling More...

#define	ENABLE_INTERRUPTS() __asm__("rim")
	enable interrupt handling More...

#define	TRIGGER_TRAP __asm__("trap")
	trigger a trap (=soft interrupt) e.g. for EMC robustness (see AN1015) More...

#define	WAIT_FOR_INTERRUPT() __asm__("wfi")
	stop code execution and wait for interrupt More...

#define	ENTER_HALT() __asm__("halt")
	put controller to HALT mode More...

#define	SW_RESET() (_WWDG_CR=0xBF)
	reset controller via WWGD module More...

#define	_BITS unsigned int
	data type in bit structs (follow C90 standard) More...

#define	_SFR(type, addr) (((volatile type) (addr)))
	peripheral register More...

#define	__TLI_VECTOR__ 0
	irq0 - External Top Level interrupt (TLI) for pin PD7 More...

#define	__AWU_VECTOR__ 1
	irq1 - Auto Wake Up from Halt interrupt (AWU) More...

#define	__CLK_VECTOR__ 2
	irq2 - Clock Controller interrupt More...

#define	__PORTA_VECTOR__ 3
	irq3 - External interrupt 0 (GPIOA) More...

#define	__PORTB_VECTOR__ 4
	irq4 - External interrupt 1 (GPIOB) More...

#define	__PORTC_VECTOR__ 5
	irq5 - External interrupt 2 (GPIOC) More...

#define	__PORTD_VECTOR__ 6
	irq6 - External interrupt 3 (GPIOD) More...

#define	__PORTE_VECTOR__ 7
	irq7 - External interrupt 4 (GPIOE) More...

#define	__CAN_RX_VECTOR__ 8
	irq8 - CAN receive interrupt (shared with __PORTF_VECTOR__) More...

#define	__PORTF_VECTOR__ 8
	irq8 - External interrupt 5 (GPIOF, shared with __CAN_RX_VECTOR__) More...

#define	__CAN_TX_VECTOR__ 9
	irq9 - CAN transmit interrupt More...

#define	__SPI_VECTOR__ 10
	irq10 - SPI End of transfer interrupt More...

#define	__TIM1_UPD_OVF_VECTOR__ 11
	irq11 - TIM1 Update/Overflow/Trigger/Break interrupt More...

#define	__TIM1_CAPCOM_VECTOR__ 12
	irq12 - TIM1 Capture/Compare interrupt More...

#define	__TIM2_UPD_OVF_VECTOR__ 13
	irq13 - TIM2 Update/overflow interrupt (shared with __TIM5_UPD_OVF_VECTOR__) More...

#define	__TIM5_UPD_OVF_VECTOR__ 13
	irq13 - TIM5 Update/overflow interrupt (shared with __TIM2_UPD_OVF_VECTOR__) More...

#define	__TIM2_CAPCOM_VECTOR__ 14
	irq14 - TIM2 Capture/Compare interrupt (shared with __TIM5_CAPCOM_VECTOR__) More...

#define	__TIM3_UPD_OVF_VECTOR__ 15
	irq15 - TIM3 Update/overflow interrupt More...

#define	__TIM3_CAPCOM_VECTOR__ 16
	irq16 - TIM3 Capture/Compare interrupt More...

#define	__UART1_TXE_VECTOR__ 17
	irq17 - USART/UART1 send (TX empty) interrupt More...

#define	__UART1_RXF_VECTOR__ 18
	irq18 - USART/UART1 receive (RX full) interrupt More...

#define	__I2C_VECTOR__ 19
	irq19 - I2C interrupt More...

#define	__UART2_TXE_VECTOR__ 20
	irq20 - UART2 send (TX empty) interrupt (shared with __UART3_TXE_VECTOR__ and __UART4_TXE_VECTOR__) More...

#define	__UART2_RXF_VECTOR__ 21
	irq21 - UART2 receive (RX full) interrupt (shared with __UART3_RXF_VECTOR__ and __UART4_RXF_VECTOR__) More...

#define	__ADC1_VECTOR__ 22
	irq22 - ADC1 end of conversion (shared with __ADC2_VECTOR__) More...

#define	__TIM4_UPD_OVF_VECTOR__ 23
	irq23 - TIM4 Update/Overflow interrupt (shared with __TIM6_UPD_OVF_VECTOR__) More...

#define	__FLASH_VECTOR__ 24
	irq24 - flash interrupt More...

#define	_GPIOA _SFR(PORT_t, PORTA_AddressBase)
	port A struct/bit access More...

#define	_GPIOA_ODR _SFR(uint8_t, PORTA_AddressBase+0x00)
	port A output register More...

#define	_GPIOA_IDR _SFR(uint8_t, PORTA_AddressBase+0x01)
	port A input register More...

#define	_GPIOA_DDR _SFR(uint8_t, PORTA_AddressBase+0x02)
	port A direction register More...

#define	_GPIOA_CR1 _SFR(uint8_t, PORTA_AddressBase+0x03)
	port A control register 1 More...

#define	_GPIOA_CR2 _SFR(uint8_t, PORTA_AddressBase+0x04)
	port A control register 2 More...

#define	_GPIOB _SFR(PORT_t, PORTB_AddressBase)
	port B struct/bit access More...

#define	_GPIOB_ODR _SFR(uint8_t, PORTB_AddressBase+0x00)
	port B output register More...

#define	_GPIOB_IDR _SFR(uint8_t, PORTB_AddressBase+0x01)
	port B input register More...

#define	_GPIOB_DDR _SFR(uint8_t, PORTB_AddressBase+0x02)
	port B direction register More...

#define	_GPIOB_CR1 _SFR(uint8_t, PORTB_AddressBase+0x03)
	port B control register 1 More...

#define	_GPIOB_CR2 _SFR(uint8_t, PORTB_AddressBase+0x04)
	port B control register 2 More...

#define	_GPIOC _SFR(PORT_t, PORTC_AddressBase)
	port C struct/bit access More...

#define	_GPIOC_ODR _SFR(uint8_t, PORTC_AddressBase+0x00)
	port C output register More...

#define	_GPIOC_IDR _SFR(uint8_t, PORTC_AddressBase+0x01)
	port C input register More...

#define	_GPIOC_DDR _SFR(uint8_t, PORTC_AddressBase+0x02)
	port C direction register More...

#define	_GPIOC_CR1 _SFR(uint8_t, PORTC_AddressBase+0x03)
	port C control register 1 More...

#define	_GPIOC_CR2 _SFR(uint8_t, PORTC_AddressBase+0x04)
	port C control register 2 More...

#define	_GPIOD _SFR(PORT_t, PORTD_AddressBase)
	port D struct/bit access More...

#define	_GPIOD_ODR _SFR(uint8_t, PORTD_AddressBase+0x00)
	port D output register More...

#define	_GPIOD_IDR _SFR(uint8_t, PORTD_AddressBase+0x01)
	port D input register More...

#define	_GPIOD_DDR _SFR(uint8_t, PORTD_AddressBase+0x02)
	port D direction register More...

#define	_GPIOD_CR1 _SFR(uint8_t, PORTD_AddressBase+0x03)
	port D control register 1 More...

#define	_GPIOD_CR2 _SFR(uint8_t, PORTD_AddressBase+0x04)
	port D control register 2 More...

#define	_GPIOE _SFR(PORT_t, PORTE_AddressBase)
	port E struct/bit access More...

#define	_GPIOE_ODR _SFR(uint8_t, PORTE_AddressBase+0x00)
	port E output register More...

#define	_GPIOE_IDR _SFR(uint8_t, PORTE_AddressBase+0x01)
	port E input register More...

#define	_GPIOE_DDR _SFR(uint8_t, PORTE_AddressBase+0x02)
	port E direction register More...

#define	_GPIOE_CR1 _SFR(uint8_t, PORTE_AddressBase+0x03)
	port E control register 1 More...

#define	_GPIOE_CR2 _SFR(uint8_t, PORTE_AddressBase+0x04)
	port E control register 2 More...

#define	_GPIOF _SFR(PORT_t, PORTF_AddressBase)
	port F struct/bit access More...

#define	_GPIOF_ODR _SFR(uint8_t, PORTF_AddressBase+0x00)
	port F output register More...

#define	_GPIOF_IDR _SFR(uint8_t, PORTF_AddressBase+0x01)
	port F input register More...

#define	_GPIOF_DDR _SFR(uint8_t, PORTF_AddressBase+0x02)
	port F direction register More...

#define	_GPIOF_CR1 _SFR(uint8_t, PORTF_AddressBase+0x03)
	port F control register 1 More...

#define	_GPIOF_CR2 _SFR(uint8_t, PORTF_AddressBase+0x04)
	port F control register 2 More...

#define	_GPIOG _SFR(PORT_t, PORTG_AddressBase)
	port G struct/bit access More...

#define	_GPIOG_ODR _SFR(uint8_t, PORTG_AddressBase+0x00)
	port G output register More...

#define	_GPIOG_IDR _SFR(uint8_t, PORTG_AddressBase+0x01)
	port G input register More...

#define	_GPIOG_DDR _SFR(uint8_t, PORTG_AddressBase+0x02)
	port G direction register More...

#define	_GPIOG_CR1 _SFR(uint8_t, PORTG_AddressBase+0x03)
	port G control register 1 More...

#define	_GPIOG_CR2 _SFR(uint8_t, PORTG_AddressBase+0x04)
	port G control register 2 More...

#define	_GPIOH _SFR(PORT_t, PORTH_AddressBase)
	port H struct/bit access More...

#define	_GPIOH_ODR _SFR(uint8_t, PORTH_AddressBase+0x00)
	port H output register More...

#define	_GPIOH_IDR _SFR(uint8_t, PORTH_AddressBase+0x01)
	port H input register More...

#define	_GPIOH_DDR _SFR(uint8_t, PORTH_AddressBase+0x02)
	port H direction register More...

#define	_GPIOH_CR1 _SFR(uint8_t, PORTH_AddressBase+0x03)
	port H control register 1 More...

#define	_GPIOH_CR2 _SFR(uint8_t, PORTH_AddressBase+0x04)
	port H control register 2 More...

#define	_GPIOI _SFR(PORT_t, PORTI_AddressBase)
	port I struct/bit access More...

#define	_GPIOI_ODR _SFR(uint8_t, PORTI_AddressBase+0x00)
	port I output register More...

#define	_GPIOI_IDR _SFR(uint8_t, PORTI_AddressBase+0x01)
	port I input register More...

#define	_GPIOI_DDR _SFR(uint8_t, PORTI_AddressBase+0x02)
	port I direction register More...

#define	_GPIOI_CR1 _SFR(uint8_t, PORTI_AddressBase+0x03)
	port I control register 1 More...

#define	_GPIOI_CR2 _SFR(uint8_t, PORTI_AddressBase+0x04)
	port I control register 2 More...

#define	_GPIO_ODR_RESET_VALUE ((uint8_t) 0x00)
	port output register reset value More...

#define	_GPIO_DDR_RESET_VALUE ((uint8_t) 0x00)
	port direction register reset value More...

#define	_GPIO_CR1_RESET_VALUE ((uint8_t) 0x00)
	port control register 1 reset value More...

#define	_GPIO_CR2_RESET_VALUE ((uint8_t) 0x00)
	port control register 2 reset value More...

#define	_GPIO_PIN0 ((uint8_t) (0x01 << 0))
	port bit mask for pin 0 (in _GPIOI_ODR, _GPIOI_IDR, _GPIOI_DDR, _GPIOI_CR1, _GPIOI_CR2) More...

#define	_GPIO_PIN1 ((uint8_t) (0x01 << 1))
	port bit mask for pin 1 (in _GPIOI_ODR, _GPIOI_IDR, _GPIOI_DDR, _GPIOI_CR1, _GPIOI_CR2) More...

#define	_GPIO_PIN2 ((uint8_t) (0x01 << 2))
	port bit mask for pin 2 (in _GPIOI_ODR, _GPIOI_IDR, _GPIOI_DDR, _GPIOI_CR1, _GPIOI_CR2) More...

#define	_GPIO_PIN3 ((uint8_t) (0x01 << 3))
	port bit mask for pin 3 (in _GPIOI_ODR, _GPIOI_IDR, _GPIOI_DDR, _GPIOI_CR1, _GPIOI_CR2) More...

#define	_GPIO_PIN4 ((uint8_t) (0x01 << 4))
	port bit mask for pin 4 (in _GPIOI_ODR, _GPIOI_IDR, _GPIOI_DDR, _GPIOI_CR1, _GPIOI_CR2) More...

#define	_GPIO_PIN5 ((uint8_t) (0x01 << 5))
	port bit mask for pin 5 (in _GPIOI_ODR, _GPIOI_IDR, _GPIOI_DDR, _GPIOI_CR1, _GPIOI_CR2) More...

#define	_GPIO_PIN6 ((uint8_t) (0x01 << 6))
	port bit mask for pin 6 (in _GPIOI_ODR, _GPIOI_IDR, _GPIOI_DDR, _GPIOI_CR1, _GPIOI_CR2) More...

#define	_GPIO_PIN7 ((uint8_t) (0x01 << 7))
	port bit mask for pin 7 (in _GPIOI_ODR, _GPIOI_IDR, _GPIOI_DDR, _GPIOI_CR1, _GPIOI_CR2) More...

#define	_FLASH _SFR(FLASH_t, FLASH_AddressBase)
	Flash struct/bit access. More...

#define	_FLASH_CR1 _SFR(uint8_t, FLASH_AddressBase+0x00)
	Flash control register 1 (FLASH_CR1) More...

#define	_FLASH_CR2 _SFR(uint8_t, FLASH_AddressBase+0x01)
	Flash control register 2 (FLASH_CR2) More...

#define	_FLASH_NCR2 _SFR(uint8_t, FLASH_AddressBase+0x02)
	complementary Flash control register 2 (FLASH_NCR2) More...

#define	_FLASH_FPR _SFR(uint8_t, FLASH_AddressBase+0x03)
	Flash protection register (FLASH_FPR) More...

#define	_FLASH_NFPR _SFR(uint8_t, FLASH_AddressBase+0x04)
	complementary Flash protection register (FLASH_NFPR) More...

#define	_FLASH_IAPSR _SFR(uint8_t, FLASH_AddressBase+0x05)
	Flash status register (FLASH_IAPSR) More...

#define	_FLASH_PUKR _SFR(uint8_t, FLASH_AddressBase+0x08)
	Flash program memory unprotecting key register (FLASH_PUKR) More...

#define	_FLASH_DUKR _SFR(uint8_t, FLASH_AddressBase+0x0A)
	Data EEPROM unprotection key register (FLASH_DUKR) More...

#define	_FLASH_CR1_RESET_VALUE ((uint8_t) 0x00)
	Flash control register 1 reset value. More...

#define	_FLASH_CR2_RESET_VALUE ((uint8_t) 0x00)
	Flash control register 2 reset value. More...

#define	_FLASH_NCR2_RESET_VALUE ((uint8_t) 0xFF)
	complementary Flash control register 2 reset value More...

#define	_FLASH_IAPSR_RESET_VALUE ((uint8_t) 0x40)
	Flash status register reset value. More...

#define	_FLASH_PUKR_RESET_VALUE ((uint8_t) 0x00)
	Flash program memory unprotecting key reset value. More...

#define	_FLASH_DUKR_RESET_VALUE ((uint8_t) 0x00)
	Data EEPROM unprotection key reset value. More...

#define	_FLASH_FIX ((uint8_t) (0x01 << 0))
	Fixed Byte programming time [0] (in _FLASH_CR1) More...

#define	_FLASH_IE ((uint8_t) (0x01 << 1))
	Flash Interrupt enable [0] (in _FLASH_CR1) More...

#define	_FLASH_AHALT ((uint8_t) (0x01 << 2))
	Power-down in Active-halt mode [0] (in _FLASH_CR1) More...

#define	_FLASH_HALT ((uint8_t) (0x01 << 3))
	Power-down in Halt mode [0] (in _FLASH_CR1) More...

#define	_FLASH_PRG ((uint8_t) (0x01 << 0))
	Standard block programming [0] (in _FLASH_CR2 and _FLASH_NCR2) More...

#define	_FLASH_FPRG ((uint8_t) (0x01 << 4))
	Fast block programming [0] (in _FLASH_CR2 and _FLASH_NCR2) More...

#define	_FLASH_ERASE ((uint8_t) (0x01 << 5))
	Block erasing [0] (in _FLASH_CR2 and _FLASH_NCR2) More...

#define	_FLASH_WPRG ((uint8_t) (0x01 << 6))
	Word programming [0] (in _FLASH_CR2 and _FLASH_NCR2) More...

#define	_FLASH_OPT ((uint8_t) (0x01 << 7))
	Write option bytes [0] (in _FLASH_CR2 and _FLASH_NCR2) More...

#define	_FLASH_WPB ((uint8_t) (0x3F << 0))
	User boot code area protection bits [5:0] (in _FLASH_FPR and _FLASH_NFPR) More...

#define	_FLASH_WPB0 ((uint8_t) (0x01 << 0))
	User boot code area protection bit [0] (in _FLASH_FPR and _FLASH_NFPR) More...

#define	_FLASH_WPB1 ((uint8_t) (0x01 << 1))
	User boot code area protection bit [1] (in _FLASH_FPR and _FLASH_NFPR) More...

#define	_FLASH_WPB2 ((uint8_t) (0x01 << 2))
	User boot code area protection bit [2] (in _FLASH_FPR and _FLASH_NFPR) More...

#define	_FLASH_WPB3 ((uint8_t) (0x01 << 3))
	User boot code area protection bit [3] (in _FLASH_FPR and _FLASH_NFPR) More...

#define	_FLASH_WPB4 ((uint8_t) (0x01 << 4))
	User boot code area protection bit [4] (in _FLASH_FPR and _FLASH_NFPR) More...

#define	_FLASH_WPB5 ((uint8_t) (0x01 << 5))
	User boot code area protection bit [5] (in _FLASH_FPR and _FLASH_NFPR) More...

#define	_FLASH_WR_PG_DIS ((uint8_t) (0x01 << 0))
	Write attempted to protected page flag [0] (in _FLASH_IAPSR) More...

#define	_FLASH_PUL ((uint8_t) (0x01 << 1))
	Flash Program memory unlocked flag [0] (in _FLASH_IAPSR) More...

#define	_FLASH_EOP ((uint8_t) (0x01 << 2))
	End of programming (write or erase operation) flag [0] (in _FLASH_IAPSR) More...

#define	_FLASH_DUL ((uint8_t) (0x01 << 3))
	Data EEPROM area unlocked flag [0] (in _FLASH_IAPSR) More...

#define	_FLASH_HVOFF ((uint8_t) (0x01 << 5))
	End of high voltage flag [0] (in _FLASH_IAPSR) More...

#define	_EXTI _SFR(EXTI_t, EXTI_AddressBase)
	External interrupt struct/bit access. More...

#define	_EXTI_CR1 _SFR(uint8_t, EXTI_AddressBase+0x00)
	External interrupt control register 1 (EXTI_CR1) More...

#define	_EXTI_CR2 _SFR(uint8_t, EXTI_AddressBase+0x01)
	External interrupt control register 2 (EXTI_CR2) More...

#define	_EXTI_CR1_RESET_VALUE ((uint8_t) 0x00)
	External interrupt control register 1 reset value. More...

#define	_EXTI_CR2_RESET_VALUE ((uint8_t) 0x00)
	External interrupt control register 2 reset value. More...

#define	_EXTI_PAIS ((uint8_t) (0x03 << 0))
	External interrupt sensitivity for Port A [1:0] (in _EXTI_CR1) More...

#define	_EXTI_PAIS0 ((uint8_t) (0x01 << 0))
	External interrupt sensitivity for Port A [0] (in _EXTI_CR1) More...

#define	_EXTI_PAIS1 ((uint8_t) (0x01 << 1))
	External interrupt sensitivity for Port A [1] (in _EXTI_CR1) More...

#define	_EXTI_PBIS ((uint8_t) (0x03 << 2))
	External interrupt sensitivity for Port B [1:0] (in _EXTI_CR1) More...

#define	_EXTI_PBIS0 ((uint8_t) (0x01 << 2))
	External interrupt sensitivity for Port B [0] (in _EXTI_CR1) More...

#define	_EXTI_PBIS1 ((uint8_t) (0x01 << 3))
	External interrupt sensitivity for Port B [1] (in _EXTI_CR1) More...

#define	_EXTI_PCIS ((uint8_t) (0x03 << 4))
	External interrupt sensitivity for Port C [1:0] (in _EXTI_CR1) More...

#define	_EXTI_PCIS0 ((uint8_t) (0x01 << 4))
	External interrupt sensitivity for Port C [0] (in _EXTI_CR1) More...

#define	_EXTI_PCIS1 ((uint8_t) (0x01 << 5))
	External interrupt sensitivity for Port C [1] (in _EXTI_CR1) More...

#define	_EXTI_PDIS ((uint8_t) (0x03 << 6))
	External interrupt sensitivity for Port D [1:0] (in _EXTI_CR1) More...

#define	_EXTI_PDIS0 ((uint8_t) (0x01 << 6))
	External interrupt sensitivity for Port D [0] (in _EXTI_CR1) More...

#define	_EXTI_PDIS1 ((uint8_t) (0x01 << 7))
	External interrupt sensitivity for Port D [1] (in _EXTI_CR1) More...

#define	_EXTI_PEIS ((uint8_t) (0x03 << 0))
	Port E external interrupt sensitivity bits [1:0] (in _EXTI_CR2) More...

#define	_EXTI_PEIS0 ((uint8_t) (0x01 << 0))
	Port E external interrupt sensitivity bits [0] (in _EXTI_CR2) More...

#define	_EXTI_PEIS1 ((uint8_t) (0x01 << 1))
	Port E external interrupt sensitivity bits [1] (in _EXTI_CR2) More...

#define	_EXTI_TLIS ((uint8_t) (0x01 << 2))
	Top level interrupt sensitivity [0] (in _EXTI_CR2) More...

#define	_RST _SFR(RST_t, RST_AddressBase)
	Reset module struct/bit access. More...

#define	_RST_SR _SFR(uint8_t, RST_AddressBase+0x00)
	Reset module status register (RST_SR) More...

#define	_RST_WWDGF ((uint8_t) (0x01 << 0))
	Window Watchdog reset flag [0] (in _RST_SR) More...

#define	_RST_IWDGF ((uint8_t) (0x01 << 1))
	Independent Watchdog reset flag [0] (in _RST_SR) More...

#define	_RST_ILLOPF ((uint8_t) (0x01 << 2))
	Illegal opcode reset flag [0] (in _RST_SR) More...

#define	_RST_SWIMF ((uint8_t) (0x01 << 3))
	SWIM reset flag [0] (in _RST_SR) More...

#define	_RST_EMCF ((uint8_t) (0x01 << 4))
	EMC reset flag [0] (in _RST_SR) More...

#define	_CLK _SFR(CLK_t, CLK_AddressBase)
	Clock module struct/bit access. More...

#define	_CLK_ICKR _SFR(uint8_t, CLK_AddressBase+0x00)
	Internal clock register. More...

#define	_CLK_ECKR _SFR(uint8_t, CLK_AddressBase+0x01)
	External clock register. More...

#define	_CLK_CMSR _SFR(uint8_t, CLK_AddressBase+0x03)
	Clock master status register. More...

#define	_CLK_SWR _SFR(uint8_t, CLK_AddressBase+0x04)
	Clock master switch register. More...

#define	_CLK_SWCR _SFR(uint8_t, CLK_AddressBase+0x05)
	Clock switch control register. More...

#define	_CLK_CKDIVR _SFR(uint8_t, CLK_AddressBase+0x06)
	Clock divider register. More...

#define	_CLK_PCKENR1 _SFR(uint8_t, CLK_AddressBase+0x07)
	Peripheral clock gating register 1. More...

#define	_CLK_CSSR _SFR(uint8_t, CLK_AddressBase+0x08)
	Clock security system register. More...

#define	_CLK_CCOR _SFR(uint8_t, CLK_AddressBase+0x09)
	Configurable clock output register. More...

#define	_CLK_PCKENR2 _SFR(uint8_t, CLK_AddressBase+0x0A)
	Peripheral clock gating register 2. More...

#define	_CLK_HSITRIMR _SFR(uint8_t, CLK_AddressBase+0x0C)
	HSI clock calibration trimming register. More...

#define	_CLK_SWIMCCR _SFR(uint8_t, CLK_AddressBase+0x0D)
	SWIM clock control register. More...

#define	_CLK_ICKR_RESET_VALUE ((uint8_t) 0x01)
	Internal clock register reset value. More...

#define	_CLK_ECKR_RESET_VALUE ((uint8_t) 0x00)
	External clock register reset value. More...

#define	_CLK_CMSR_RESET_VALUE ((uint8_t) 0xE1)
	Clock master status reset value. More...

#define	_CLK_SWR_RESET_VALUE ((uint8_t) 0xE1)
	Clock master switch reset value. More...

#define	_CLK_SWCR_RESET_VALUE ((uint8_t) 0x00)
	Clock switch control reset value. More...

#define	_CLK_CKDIVR_RESET_VALUE ((uint8_t) 0x18)
	Clock divider register reset value. More...

#define	_CLK_PCKENR1_RESET_VALUE ((uint8_t) 0xFF)
	Peripheral clock gating register 1 reset value. More...

#define	_CLK_PCKENR2_RESET_VALUE ((uint8_t) 0xFF)
	Peripheral clock gating register 2 reset value. More...

#define	_CLK_CSSR_RESET_VALUE ((uint8_t) 0x00)
	Clock security system register reset value. More...

#define	_CLK_CCOR_RESET_VALUE ((uint8_t) 0x00)
	Configurable clock output register reset value. More...

#define	_CLK_HSITRIMR_RESET_VALUE ((uint8_t) 0x00)
	HSI clock calibration trimming register reset value. More...

#define	_CLK_SWIMCCR_RESET_VALUE ((uint8_t) 0x00)
	SWIM clock control register reset value. More...

#define	_CLK_HSIEN ((uint8_t) (0x01 << 0))
	High speed internal RC oscillator enable [0] (in _CLK_ICKR) More...

#define	_CLK_HSIRDY ((uint8_t) (0x01 << 1))
	High speed internal oscillator ready [0] (in _CLK_ICKR) More...

#define	_CLK_FHWU ((uint8_t) (0x01 << 2))
	Fast wakeup from Halt/Active-halt modes [0] (in _CLK_ICKR) More...

#define	_CLK_LSIEN ((uint8_t) (0x01 << 3))
	Low speed internal RC oscillator enable [0] (in _CLK_ICKR) More...

#define	_CLK_LSIRDY ((uint8_t) (0x01 << 4))
	Low speed internal oscillator ready [0] (in _CLK_ICKR) More...

#define	_CLK_REGAH ((uint8_t) (0x01 << 5))
	Regulator power off in Active-halt mode [0] (in _CLK_ICKR) More...

#define	_CLK_HSEEN ((uint8_t) (0x01 << 0))
	High speed external crystal oscillator enable [0] (in _CLK_ECKR) More...

#define	_CLK_ECKR_HSERDY ((uint8_t) (0x01 << 1))
	High speed external crystal oscillator ready [0] (in _CLK_ECKR) More...

#define	_CLK_SWI_HSI ((uint8_t) 0xE1)
	write to CLK_SWR for HSI clock (in _CLK_SWR) More...

#define	_CLK_SWI_LSI ((uint8_t) 0xD2)
	write to CLK_SWR for LSI clock (in _CLK_SWR) More...

#define	_CLK_SWI_HSE ((uint8_t) 0xB4)
	write to CLK_SWR for HSE clock (in _CLK_SWR) More...

#define	_CLK_SWBSY ((uint8_t) (0x01 << 0))
	Switch busy flag [0] (in _CLK_SWCR) More...

#define	_CLK_SWEN ((uint8_t) (0x01 << 1))
	Switch start/stop enable [0] (in _CLK_SWCR) More...

#define	_CLK_SWIEN ((uint8_t) (0x01 << 2))
	Clock switch interrupt enable [0] (in _CLK_SWCR) More...

#define	_CLK_SWIF ((uint8_t) (0x01 << 3))
	Clock switch interrupt flag [0] (in _CLK_SWCR) More...

#define	_CLK_CPUDIV ((uint8_t) (0x07 << 0))
	CPU clock prescaler [2:0] (in _CLK_CKDIVR) More...

#define	_CLK_CPUDIV0 ((uint8_t) (0x01 << 0))
	CPU clock prescaler [0] (in _CLK_CKDIVR) More...

#define	_CLK_CPUDIV1 ((uint8_t) (0x01 << 1))
	CPU clock prescaler [1] (in _CLK_CKDIVR) More...

#define	_CLK_CPUDIV2 ((uint8_t) (0x01 << 2))
	CPU clock prescaler [2] (in _CLK_CKDIVR) More...

#define	_CLK_HSIDIV ((uint8_t) (0x03 << 3))
	High speed internal clock prescaler [1:0] (in _CLK_CKDIVR) More...

#define	_CLK_HSIDIV0 ((uint8_t) (0x01 << 3))
	High speed internal clock prescaler [0] (in _CLK_CKDIVR) More...

#define	_CLK_HSIDIV1 ((uint8_t) (0x01 << 4))
	High speed internal clock prescaler [1] (in _CLK_CKDIVR) More...

#define	_CLK_I2C ((uint8_t) (0x01 << 0))
	clock enable I2C [0] (in _CLK_PCKENR1) More...

#define	_CLK_SPI ((uint8_t) (0x01 << 1))
	clock enable SPI [0] (in _CLK_PCKENR1) More...

#define	_CLK_UART1 ((uint8_t) (0x01 << 2))
	clock enable UART1 [0] (in _CLK_PCKENR1) More...

#define	_CLK_UART2 ((uint8_t) (0x01 << 3))
	clock enable UART2 [0] (in _CLK_PCKENR1) More...

#define	_CLK_TIM4_TIM6 ((uint8_t) (0x01 << 4))
	clock enable TIM4/TIM6 [0] (in _CLK_PCKENR1) More...

#define	_CLK_TIM2_TIM5 ((uint8_t) (0x01 << 5))
	clock enable TIM2/TIM5 [0] (in _CLK_PCKENR1) More...

#define	_CLK_TIM3 ((uint8_t) (0x01 << 6))
	clock enable TIM3 [0] (in _CLK_PCKENR1) More...

#define	_CLK_TIM1 ((uint8_t) (0x01 << 7))
	clock enable TIM1 [0] (in _CLK_PCKENR1) More...

#define	_CLK_CSSEN ((uint8_t) (0x01 << 0))
	Clock security system enable [0] (in _CLK_CSSR) More...

#define	_CLK_AUX ((uint8_t) (0x01 << 1))
	Auxiliary oscillator connected to master clock [0] (in _CLK_CSSR) More...

#define	_CLK_CSSDIE ((uint8_t) (0x01 << 2))
	Clock security system detection interrupt enable [0] (in _CLK_CSSR) More...

#define	_CLK_CSSD ((uint8_t) (0x01 << 3))
	Clock security system detection [0] (in _CLK_CSSR) More...

#define	_CLK_CCOEN ((uint8_t) (0x01 << 0))
	Configurable clock output enable [0] (in _CLK_CCOR) More...

#define	_CLK_CCOSEL ((uint8_t) (0x0F << 1))
	Configurable clock output selection [3:0] (in _CLK_CCOR) More...

#define	_CLK_CCOSEL0 ((uint8_t) (0x01 << 1))
	Configurable clock output selection [0] (in _CLK_CCOR) More...

#define	_CLK_CCOSEL1 ((uint8_t) (0x01 << 2))
	Configurable clock output selection [1] (in _CLK_CCOR) More...

#define	_CLK_CCOSEL2 ((uint8_t) (0x01 << 3))
	Configurable clock output selection [2] (in _CLK_CCOR) More...

#define	_CLK_CCOSEL3 ((uint8_t) (0x01 << 4))
	Configurable clock output selection [3] (in _CLK_CCOR) More...

#define	_CLK_CCORDY ((uint8_t) (0x01 << 5))
	Configurable clock output ready [0] (in _CLK_CCOR) More...

#define	_CLK_CCOBSY ((uint8_t) (0x01 << 6))
	Configurable clock output busy [0] (in _CLK_CCOR) More...

#define	_CLK_AWU ((uint8_t) (0x01 << 2))
	clock enable AWU [0] (in _CLK_PCKENR2) More...

#define	_CLK_ADC ((uint8_t) (0x01 << 3))
	clock enable ADC [0] (in _CLK_PCKENR2) More...

#define	_CLK_CAN ((uint8_t) (0x01 << 7))
	clock enable CAN [0] (in _CLK_PCKENR2) More...

#define	_CLK_HSITRIM ((uint8_t) (0x0F << 0))
	HSI trimming value (some devices only support 3 bits, see DS!) [3:0] (in _CLK_HSITRIMR) More...

#define	_CLK_HSITRIM0 ((uint8_t) (0x01 << 0))
	HSI trimming value [0] (in _CLK_HSITRIMR) More...

#define	_CLK_HSITRIM1 ((uint8_t) (0x01 << 1))
	HSI trimming value [1] (in _CLK_HSITRIMR) More...

#define	_CLK_HSITRIM2 ((uint8_t) (0x01 << 2))
	HSI trimming value [2] (in _CLK_HSITRIMR) More...

#define	_CLK_HSITRIM3 ((uint8_t) (0x01 << 3))
	HSI trimming value [3] (in _CLK_HSITRIMR) More...

#define	_CLK_SWIMCLK ((uint8_t) (0x01 << 0))
	SWIM clock divider [0] (in _CLK_SWIMCCR) More...

#define	_WWDG _SFR(WWDG_t, WWDG_AddressBase)
	Window Watchdog struct/bit access. More...

#define	_WWDG_CR _SFR(uint8_t, WWDG_AddressBase+0x00)
	Window Watchdog Control register (WWDG_CR) More...

#define	_WWDG_WR _SFR(uint8_t, WWDG_AddressBase+0x01)
	Window Watchdog Window register (WWDG_WR) More...

#define	_WWDG_CR_RESET_VALUE ((uint8_t) 0x7F)
	Window Watchdog Control register reset value. More...

#define	_WWDG_WR_RESET_VALUE ((uint8_t) 0x7F)
	Window Watchdog Window register reset value. More...

#define	_WWDG_T ((uint8_t) (0x7F << 0))
	Window Watchdog 7-bit counter [6:0] (in _WWDG_CR) More...

#define	_WWDG_T0 ((uint8_t) (0x01 << 0))
	Window Watchdog 7-bit counter [0] (in _WWDG_CR) More...

#define	_WWDG_T1 ((uint8_t) (0x01 << 1))
	Window Watchdog 7-bit counter [1] (in _WWDG_CR) More...

#define	_WWDG_T2 ((uint8_t) (0x01 << 2))
	Window Watchdog 7-bit counter [2] (in _WWDG_CR) More...

#define	_WWDG_T3 ((uint8_t) (0x01 << 3))
	Window Watchdog 7-bit counter [3] (in _WWDG_CR) More...

#define	_WWDG_T4 ((uint8_t) (0x01 << 4))
	Window Watchdog 7-bit counter [4] (in _WWDG_CR) More...

#define	_WWDG_T5 ((uint8_t) (0x01 << 5))
	Window Watchdog 7-bit counter [5] (in _WWDG_CR) More...

#define	_WWDG_T6 ((uint8_t) (0x01 << 6))
	Window Watchdog 7-bit counter [6] (in _WWDG_CR) More...

#define	_WWDG_WDGA ((uint8_t) (0x01 << 7))
	Window Watchdog activation bit (n/a if WWDG enabled by option byte) [0] (in _WWDG_CR) More...

#define	_WWDG_W ((uint8_t) (0x7F << 0))
	Window Watchdog 7-bit window value [6:0] (in _WWDG_WR) More...

#define	_WWDG_W0 ((uint8_t) (0x01 << 0))
	Window Watchdog 7-bit window value [0] (in _WWDG_WR) More...

#define	_WWDG_W1 ((uint8_t) (0x01 << 1))
	Window Watchdog 7-bit window value [1] (in _WWDG_WR) More...

#define	_WWDG_W2 ((uint8_t) (0x01 << 2))
	Window Watchdog 7-bit window value [2] (in _WWDG_WR) More...

#define	_WWDG_W3 ((uint8_t) (0x01 << 3))
	Window Watchdog 7-bit window value [3] (in _WWDG_WR) More...

#define	_WWDG_W4 ((uint8_t) (0x01 << 4))
	Window Watchdog 7-bit window value [4] (in _WWDG_WR) More...

#define	_WWDG_W5 ((uint8_t) (0x01 << 5))
	Window Watchdog 7-bit window value [5] (in _WWDG_WR) More...

#define	_WWDG_W6 ((uint8_t) (0x01 << 6))
	Window Watchdog 7-bit window value [6] (in _WWDG_WR) More...

#define	_IWDG _SFR(IWDG_t, IWDG_AddressBase)
	Independent Timeout Watchdog struct/bit access. More...

#define	_IWDG_KR _SFR(uint8_t, IWDG_AddressBase+0x00)
	Independent Timeout Watchdog Key register (IWDG_KR) More...

#define	_IWDG_PR _SFR(uint8_t, IWDG_AddressBase+0x01)
	Independent Timeout Watchdog Prescaler register (IWDG_PR) More...

#define	_IWDG_RLR _SFR(uint8_t, IWDG_AddressBase+0x02)
	Independent Timeout Watchdog Reload register (IWDG_RLR) More...

#define	_IWDG_PR_RESET_VALUE ((uint8_t) 0x00)
	Independent Timeout Watchdog Prescaler register reset value. More...

#define	_IWDG_RLR_RESET_VALUE ((uint8_t) 0xFF)
	Independent Timeout Watchdog Reload register reset value. More...

#define	_IWDG_KEY_ENABLE ((uint8_t) 0xCC)
	Independent Timeout Watchdog enable (in _IWDG_KR) More...

#define	_IWDG_KEY_REFRESH ((uint8_t) 0xAA)
	Independent Timeout Watchdog refresh (in _IWDG_KR) More...

#define	_IWDG_KEY_ACCESS ((uint8_t) 0x55)
	Independent Timeout Watchdog unlock write to IWDG_PR and IWDG_RLR (in _IWDG_KR) More...

#define	_IWDG_PRE ((uint8_t) (0x07 << 0))
	Independent Timeout Watchdog Prescaler divider [2:0] (in _IWDG_PR) More...

#define	_IWDG_PRE0 ((uint8_t) (0x01 << 0))
	Independent Timeout Watchdog Prescaler divider [0] (in _IWDG_PR) More...

#define	_IWDG_PRE1 ((uint8_t) (0x01 << 1))
	Independent Timeout Watchdog Prescaler divider [1] (in _IWDG_PR) More...

#define	_IWDG_PRE2 ((uint8_t) (0x01 << 2))
	Independent Timeout Watchdog Prescaler divider [2] (in _IWDG_PR) More...

#define	_AWU _SFR(AWU_t, AWU_AddressBase)
	Auto Wake-Up struct/bit access. More...

#define	_AWU_CSR _SFR(uint8_t, AWU_AddressBase+0x00)
	Auto Wake-Up Control/status register (AWU_CSR) More...

#define	_AWU_APR _SFR(uint8_t, AWU_AddressBase+0x01)
	Auto Wake-Up Asynchronous prescaler register (AWU_APR) More...

#define	_AWU_TBR _SFR(uint8_t, AWU_AddressBase+0x02)
	Auto Wake-Up Timebase selection register (AWU_TBR) More...

#define	_AWU_CSR_RESET_VALUE ((uint8_t) 0x00)
	Auto Wake-Up Control/status register reset value. More...

#define	_AWU_APR_RESET_VALUE ((uint8_t) 0x3F)
	Auto Wake-Up Asynchronous prescaler register reset value. More...

#define	_AWU_TBR_RESET_VALUE ((uint8_t) 0x00)
	Auto Wake-Up Timebase selection register reset value. More...

#define	_AWU_MSR ((uint8_t) (0x01 << 0))
	Auto Wake-Up LSI measurement enable [0] (in _AWU_CSR) More...

#define	_AWU_AWUEN ((uint8_t) (0x01 << 4))
	Auto-wakeup enable [0] (in _AWU_CSR) More...

#define	_AWU_AWUF ((uint8_t) (0x01 << 5))
	Auto-wakeup status flag [0] (in _AWU_CSR) More...

#define	_AWU_APRE ((uint8_t) (0x3F << 0))
	Auto-wakeup asynchronous prescaler divider [5:0] (in _AWU_APR) More...

#define	_AWU_APRE0 ((uint8_t) (0x01 << 0))
	Auto-wakeup asynchronous prescaler divider [0] (in _AWU_APR) More...

#define	_AWU_APRE1 ((uint8_t) (0x01 << 1))
	Auto-wakeup asynchronous prescaler divider [1] (in _AWU_APR) More...

#define	_AWU_APRE2 ((uint8_t) (0x01 << 2))
	Auto-wakeup asynchronous prescaler divider [2] (in _AWU_APR) More...

#define	_AWU_APRE3 ((uint8_t) (0x01 << 3))
	Auto-wakeup asynchronous prescaler divider [3] (in _AWU_APR) More...

#define	_AWU_APRE4 ((uint8_t) (0x01 << 4))
	Auto-wakeup asynchronous prescaler divider [4] (in _AWU_APR) More...

#define	_AWU_APRE5 ((uint8_t) (0x01 << 5))
	Auto-wakeup asynchronous prescaler divider [5] (in _AWU_APR) More...

#define	_AWU_AWUTB ((uint8_t) (0x0F << 0))
	Auto-wakeup timebase selection [3:0] (in _AWU_APR) More...

#define	_AWU_AWUTB0 ((uint8_t) (0x01 << 0))
	Auto-wakeup timebase selection [0] (in _AWU_APR) More...

#define	_AWU_AWUTB1 ((uint8_t) (0x01 << 1))
	Auto-wakeup timebase selection [1] (in _AWU_APR) More...

#define	_AWU_AWUTB2 ((uint8_t) (0x01 << 2))
	Auto-wakeup timebase selection [2] (in _AWU_APR) More...

#define	_AWU_AWUTB3 ((uint8_t) (0x01 << 3))
	Auto-wakeup timebase selection [3] (in _AWU_APR) More...

#define	_BEEP _SFR(BEEP_t, BEEP_AddressBase)
	Beeper struct/bit access. More...

#define	_BEEP_CSR _SFR(uint8_t, BEEP_AddressBase+0x00)
	Beeper control/status register (BEEP_CSR) More...

#define	_BEEP_CSR_RESET_VALUE ((uint8_t) 0x1F)
	Beeper control/status register reset value. More...

#define	_BEEP_BEEPDIV ((uint8_t) (0x1F << 0))
	Beeper clock prescaler divider [4:0] (in _BEEP_CSR) More...

#define	_BEEP_BEEPDIV0 ((uint8_t) (0x01 << 0))
	Beeper clock prescaler divider [0] (in _BEEP_CSR) More...

#define	_BEEP_BEEPDIV1 ((uint8_t) (0x01 << 1))
	Beeper clock prescaler divider [1] (in _BEEP_CSR) More...

#define	_BEEP_BEEPDIV2 ((uint8_t) (0x01 << 2))
	Beeper clock prescaler divider [2] (in _BEEP_CSR) More...

#define	_BEEP_BEEPDIV3 ((uint8_t) (0x01 << 3))
	Beeper clock prescaler divider [3] (in _BEEP_CSR) More...

#define	_BEEP_BEEPDIV4 ((uint8_t) (0x01 << 4))
	Beeper clock prescaler divider [4] (in _BEEP_CSR) More...

#define	_BEEP_BEEPEN ((uint8_t) (0x01 << 5))
	Beeper enable [0] (in _BEEP_CSR) More...

#define	_BEEP_BEEPSEL ((uint8_t) (0x03 << 6))
	Beeper frequency selection [1:0] (in _BEEP_CSR) More...

#define	_BEEP_BEEPSEL0 ((uint8_t) (0x01 << 6))
	Beeper frequency selection [0] (in _BEEP_CSR) More...

#define	_BEEP_BEEPSEL1 ((uint8_t) (0x01 << 7))
	Beeper frequency selection [1] (in _BEEP_CSR) More...

#define	_SPI _SFR(SPI_t, SPI_AddressBase)
	register for SPI control More...

#define	_SPI_CR1 _SFR(uint8_t, SPI_AddressBase+0x00)
	SPI control register 1. More...

#define	_SPI_CR2 _SFR(uint8_t, SPI_AddressBase+0x01)
	SPI control register 2. More...

#define	_SPI_ICR _SFR(uint8_t, SPI_AddressBase+0x02)
	SPI interrupt control register. More...

#define	_SPI_SR _SFR(uint8_t, SPI_AddressBase+0x03)
	SPI status register. More...

#define	_SPI_DR _SFR(uint8_t, SPI_AddressBase+0x04)
	SPI data register. More...

#define	_SPI_CRCPR _SFR(uint8_t, SPI_AddressBase+0x05)
	SPI CRC polynomial register. More...

#define	_SPI_RXCRCR _SFR(uint8_t, SPI_AddressBase+0x06)
	SPI Rx CRC register. More...

#define	_SPI_TXCRCR _SFR(uint8_t, SPI_AddressBase+0x07)
	SPI Tx CRC register. More...

#define	_SPI_CR1_RESET_VALUE ((uint8_t) 0x00)
	SPI Control Register 1 reset value. More...

#define	_SPI_CR2_RESET_VALUE ((uint8_t) 0x00)
	SPI Control Register 2 reset value. More...

#define	_SPI_ICR_RESET_VALUE ((uint8_t) 0x00)
	SPI Interrupt Control Register reset value. More...

#define	_SPI_SR_RESET_VALUE ((uint8_t) 0x02)
	SPI Status Register reset value. More...

#define	_SPI_DR_RESET_VALUE ((uint8_t) 0x00)
	SPI Data Register reset value. More...

#define	_SPI_CRCPR_RESET_VALUE ((uint8_t) 0x07)
	SPI Polynomial Register reset value. More...

#define	_SPI_RXCRCR_RESET_VALUE ((uint8_t) 0x00)
	SPI RX CRC Register reset value. More...

#define	_SPI_TXCRCR_RESET_VALUE ((uint8_t) 0x00)
	SPI TX CRC Register reset value. More...

#define	_SPI_CPHA ((uint8_t) (0x01 << 0))
	SPI Clock phase [0] (in _SPI_CR1) More...

#define	_SPI_CPOL ((uint8_t) (0x01 << 1))
	SPI Clock polarity [0] (in _SPI_CR1) More...

#define	_SPI_MSTR ((uint8_t) (0x01 << 2))
	SPI Master/slave selection [0] (in _SPI_CR1) More...

#define	_SPI_BR ((uint8_t) (0x07 << 3))
	SPI Baudrate control [2:0] (in _SPI_CR1) More...

#define	_SPI_BR0 ((uint8_t) (0x01 << 3))
	SPI Baudrate control [0] (in _SPI_CR1) More...

#define	_SPI_BR1 ((uint8_t) (0x01 << 4))
	SPI Baudrate control [1] (in _SPI_CR1) More...

#define	_SPI_BR2 ((uint8_t) (0x01 << 5))
	SPI Baudrate control [2] (in _SPI_CR1) More...

#define	_SPI_SPE ((uint8_t) (0x01 << 6))
	SPI enable [0] (in _SPI_CR1) More...

#define	_SPI_LSBFIRST ((uint8_t) (0x01 << 7))
	SPI Frame format [0] (in _SPI_CR1) More...

#define	_SPI_SSI ((uint8_t) (0x01 << 0))
	SPI Internal slave select [0] (in _SPI_CR2) More...

#define	_SPI_SSM ((uint8_t) (0x01 << 1))
	SPI Software slave management [0] (in _SPI_CR2) More...

#define	_SPI_RXONLY ((uint8_t) (0x01 << 2))
	SPI Receive only [0] (in _SPI_CR2) More...

#define	_SPI_CRCNEXT ((uint8_t) (0x01 << 4))
	SPI Transmit CRC next [0] (in _SPI_CR2) More...

#define	_SPI_CRCEN ((uint8_t) (0x01 << 5))
	SPI Hardware CRC calculation enable [0] (in _SPI_CR2) More...

#define	_SPI_BDOE ((uint8_t) (0x01 << 6))
	SPI Input/Output enable in bidirectional mode [0] (in _SPI_CR2) More...

#define	_SPI_BDM ((uint8_t) (0x01 << 7))
	SPI Bidirectional data mode enable [0] (in _SPI_CR2) More...

#define	_SPI_WKIE ((uint8_t) (0x01 << 4))
	SPI Wakeup interrupt enable [0] (in _SPI_ICR) More...

#define	_SPI_ERRIE ((uint8_t) (0x01 << 5))
	SPI Error interrupt enable [0] (in _SPI_ICR) More...

#define	_SPI_RXIE ((uint8_t) (0x01 << 6))
	SPI Rx buffer not empty interrupt enable [0] (in _SPI_ICR) More...

#define	_SPI_TXIE ((uint8_t) (0x01 << 7))
	SPI Tx buffer empty interrupt enable [0] (in _SPI_ICR) More...

#define	_SPI_RXNE ((uint8_t) (0x01 << 0))
	SPI Receive buffer not empty [0] (in _SPI_SR) More...

#define	_SPI_TXE ((uint8_t) (0x01 << 1))
	SPI Transmit buffer empty [0] (in _SPI_SR) More...

#define	_SPI_WKUP ((uint8_t) (0x01 << 3))
	SPI Wakeup flag [0] (in _SPI_SR) More...

#define	_SPI_CRCERR ((uint8_t) (0x01 << 4))
	SPI CRC error flag [0] (in _SPI_SR) More...

#define	_SPI_MODF ((uint8_t) (0x01 << 5))
	SPI Mode fault [0] (in _SPI_SR) More...

#define	_SPI_OVR ((uint8_t) (0x01 << 6))
	SPI Overrun flag [0] (in _SPI_SR) More...

#define	_SPI_BSY ((uint8_t) (0x01 << 7))
	SPI Busy flag [0] (in _SPI_SR) More...

#define	_I2C _SFR(I2C_t, I2C_AddressBase)
	register for SPI control More...

#define	_I2C_CR1 _SFR(uint8_t, I2C_AddressBase+0x00)
	I2C Control register 1. More...

#define	_I2C_CR2 _SFR(uint8_t, I2C_AddressBase+0x01)
	I2C Control register 2. More...

#define	_I2C_FREQR _SFR(uint8_t, I2C_AddressBase+0x02)
	I2C Frequency register. More...

#define	_I2C_OARL _SFR(uint8_t, I2C_AddressBase+0x03)
	I2C own address register low byte. More...

#define	_I2C_OARH _SFR(uint8_t, I2C_AddressBase+0x04)
	I2C own address register high byte. More...

#define	_I2C_DR _SFR(uint8_t, I2C_AddressBase+0x06)
	I2C data register. More...

#define	_I2C_SR1 _SFR(uint8_t, I2C_AddressBase+0x07)
	I2C Status register 1. More...

#define	_I2C_SR2 _SFR(uint8_t, I2C_AddressBase+0x08)
	I2C Status register 2. More...

#define	_I2C_SR3 _SFR(uint8_t, I2C_AddressBase+0x09)
	I2C Status register 3. More...

#define	_I2C_ITR _SFR(uint8_t, I2C_AddressBase+0x0A)
	I2C Interrupt register. More...

#define	_I2C_CCRL _SFR(uint8_t, I2C_AddressBase+0x0B)
	I2C Clock control register low byte. More...

#define	_I2C_CCRH _SFR(uint8_t, I2C_AddressBase+0x0C)
	I2C Clock control register high byte. More...

#define	_I2C_TRISER _SFR(uint8_t, I2C_AddressBase+0x0D)
	I2C rise time register. More...

#define	_I2C_CR1_RESET_VALUE ((uint8_t) 0x00)
	I2C Control register 1 reset value. More...

#define	_I2C_CR2_RESET_VALUE ((uint8_t) 0x00)
	I2C Control register 2 reset value. More...

#define	_I2C_FREQR_RESET_VALUE ((uint8_t) 0x00)
	I2C Frequency register reset value. More...

#define	_I2C_OARL_RESET_VALUE ((uint8_t) 0x00)
	I2C own address register low byte reset value. More...

#define	_I2C_OARH_RESET_VALUE ((uint8_t) 0x00)
	I2C own address register high byte reset value. More...

#define	_I2C_DR_RESET_VALUE ((uint8_t) 0x00)
	I2C data register reset value. More...

#define	_I2C_SR1_RESET_VALUE ((uint8_t) 0x00)
	I2C Status register 1 reset value. More...

#define	_I2C_SR2_RESET_VALUE ((uint8_t) 0x00)
	I2C Status register 2 reset value. More...

#define	_I2C_SR3_RESET_VALUE ((uint8_t) 0x00)
	I2C Status register 3 reset value. More...

#define	_I2C_ITR_RESET_VALUE ((uint8_t) 0x00)
	I2C Interrupt register reset value. More...

#define	_I2C_CCRL_RESET_VALUE ((uint8_t) 0x00)
	I2C Clock control register low byte reset value. More...

#define	_I2C_CCRH_RESET_VALUE ((uint8_t) 0x00)
	I2C Clock control register high byte reset value. More...

#define	_I2C_TRISER_RESET_VALUE ((uint8_t) 0x02)
	I2C rise time register reset value. More...

#define	_I2C_PE ((uint8_t) (0x01 << 0))
	I2C Peripheral enable [0] (in _I2C_CR1) More...

#define	_I2C_ENGC ((uint8_t) (0x01 << 6))
	I2C General call enable [0] (in _I2C_CR1) More...

#define	_I2C_NOSTRETCH ((uint8_t) (0x01 << 7))
	I2C Clock stretching disable (Slave mode) [0] (in _I2C_CR1) More...

#define	_I2C_START ((uint8_t) (0x01 << 0))
	I2C Start generation [0] (in _I2C_CR2) More...

#define	_I2C_STOP ((uint8_t) (0x01 << 1))
	I2C Stop generation [0] (in _I2C_CR2) More...

#define	_I2C_ACK ((uint8_t) (0x01 << 2))
	I2C Acknowledge enable [0] (in _I2C_CR2) More...

#define	_I2C_POS ((uint8_t) (0x01 << 3))
	I2C Acknowledge position (for data reception) [0] (in _I2C_CR2) More...

#define	_I2C_SWRST ((uint8_t) (0x01 << 7))
	I2C Software reset [0] (in _I2C_CR2) More...

#define	_I2C_FREQ ((uint8_t) (0x3F << 0))
	I2C Peripheral clock frequency [5:0] (in _I2C_FREQR) More...

#define	_I2C_FREQ0 ((uint8_t) (0x01 << 0))
	I2C Peripheral clock frequency [0] (in _I2C_FREQR) More...

#define	_I2C_FREQ1 ((uint8_t) (0x01 << 1))
	I2C Peripheral clock frequency [1] (in _I2C_FREQR) More...

#define	_I2C_FREQ2 ((uint8_t) (0x01 << 2))
	I2C Peripheral clock frequency [2] (in _I2C_FREQR) More...

#define	_I2C_FREQ3 ((uint8_t) (0x01 << 3))
	I2C Peripheral clock frequency [3] (in _I2C_FREQR) More...

#define	_I2C_FREQ4 ((uint8_t) (0x01 << 4))
	I2C Peripheral clock frequency [4] (in _I2C_FREQR) More...

#define	_I2C_FREQ5 ((uint8_t) (0x01 << 5))
	I2C Peripheral clock frequency [5] (in _I2C_FREQR) More...

#define	_I2C_ADD0 ((uint8_t) (0x01 << 0))
	I2C Interface address [0] (in 10-bit address mode) (in _I2C_OARL) More...

#define	_I2C_ADD1 ((uint8_t) (0x01 << 1))
	I2C Interface address [1] (in _I2C_OARL) More...

#define	_I2C_ADD2 ((uint8_t) (0x01 << 2))
	I2C Interface address [2] (in _I2C_OARL) More...

#define	_I2C_ADD3 ((uint8_t) (0x01 << 3))
	I2C Interface address [3] (in _I2C_OARL) More...

#define	_I2C_ADD4 ((uint8_t) (0x01 << 4))
	I2C Interface address [4] (in _I2C_OARL) More...

#define	_I2C_ADD5 ((uint8_t) (0x01 << 5))
	I2C Interface address [5] (in _I2C_OARL) More...

#define	_I2C_ADD6 ((uint8_t) (0x01 << 6))
	I2C Interface address [6] (in _I2C_OARL) More...

#define	_I2C_ADD7 ((uint8_t) (0x01 << 7))
	I2C Interface address [7] (in _I2C_OARL) More...

#define	_I2C_ADD_8_9 ((uint8_t) (0x03 << 1))
	I2C Interface address [9:8] (in 10-bit address mode) (in _I2C_OARH) More...

#define	_I2C_ADD8 ((uint8_t) (0x01 << 1))
	I2C Interface address [8] (in _I2C_OARH) More...

#define	_I2C_ADD9 ((uint8_t) (0x01 << 2))
	I2C Interface address [9] (in _I2C_OARH) More...

#define	_I2C_ADDCONF ((uint8_t) (0x01 << 6))
	I2C Address mode configuration [0] (in _I2C_OARH) More...

#define	_I2C_ADDMODE ((uint8_t) (0x01 << 7))
	I2C 7-/10-bit addressing mode (Slave mode) [0] (in _I2C_OARH) More...

#define	_I2C_SB ((uint8_t) (0x01 << 0))
	I2C Start bit (Master mode) [0] (in _I2C_SR1) More...

#define	_I2C_ADDR ((uint8_t) (0x01 << 1))
	I2C Address sent (Master mode) / matched (Slave mode) [0] (in _I2C_SR1) More...

#define	_I2C_BTF ((uint8_t) (0x01 << 2))
	I2C Byte transfer finished [0] (in _I2C_SR1) More...

#define	_I2C_ADD10 ((uint8_t) (0x01 << 3))
	I2C 10-bit header sent (Master mode) [0] (in _I2C_SR1) More...

#define	_I2C_STOPF ((uint8_t) (0x01 << 4))
	I2C Stop detection (Slave mode) [0] (in _I2C_SR1) More...

#define	_I2C_RXNE ((uint8_t) (0x01 << 6))
	I2C Data register not empty (receivers) [0] (in _I2C_SR1) More...

#define	_I2C_TXE ((uint8_t) (0x01 << 7))
	I2C Data register empty (transmitters) [0] (in _I2C_SR1) More...

#define	_I2C_BERR ((uint8_t) (0x01 << 0))
	I2C Bus error [0] (in _I2C_SR2) More...

#define	_I2C_ARLO ((uint8_t) (0x01 << 1))
	I2C Arbitration lost (Master mode) [0] (in _I2C_SR2) More...

#define	_I2C_AF ((uint8_t) (0x01 << 2))
	I2C Acknowledge failure [0] (in _I2C_SR2) More...

#define	_I2C_OVR ((uint8_t) (0x01 << 3))
	I2C Overrun/underrun [0] (in _I2C_SR2) More...

#define	_I2C_WUFH ((uint8_t) (0x01 << 5))
	I2C Wakeup from Halt [0] (in _I2C_SR2) More...

#define	_I2C_MSL ((uint8_t) (0x01 << 0))
	I2C Master/Slave [0] (in _I2C_SR3) More...

#define	_I2C_BUSY ((uint8_t) (0x01 << 1))
	I2C Bus busy [0] (in _I2C_SR3) More...

#define	_I2C_TRA ((uint8_t) (0x01 << 2))
	I2C Transmitter/Receiver [0] (in _I2C_SR3) More...

#define	_I2C_GENCALL ((uint8_t) (0x01 << 4))
	I2C General call header (Slavemode) [0] (in _I2C_SR3) More...

#define	_I2C_ITERREN ((uint8_t) (0x01 << 0))
	I2C Error interrupt enable [0] (in _I2C_ITR) More...

#define	_I2C_ITEVTEN ((uint8_t) (0x01 << 1))
	I2C Event interrupt enable [0] (in _I2C_ITR) More...

#define	_I2C_ITBUFEN ((uint8_t) (0x01 << 2))
	I2C Buffer interrupt enable [0] (in _I2C_ITR) More...

#define	_I2C_CCR ((uint8_t) (0x0F << 0))
	I2C Clock control register (Master mode) [3:0] (in _I2C_CCRH) More...

#define	_I2C_CCR0 ((uint8_t) (0x01 << 0))
	I2C Clock control register (Master mode) [0] (in _I2C_CCRH) More...

#define	_I2C_CCR1 ((uint8_t) (0x01 << 1))
	I2C Clock control register (Master mode) [1] (in _I2C_CCRH) More...

#define	_I2C_CCR2 ((uint8_t) (0x01 << 2))
	I2C Clock control register (Master mode) [2] (in _I2C_CCRH) More...

#define	_I2C_CCR3 ((uint8_t) (0x01 << 3))
	I2C Clock control register (Master mode) [3] (in _I2C_CCRH) More...

#define	_I2C_DUTY ((uint8_t) (0x01 << 6))
	I2C Fast mode duty cycle [0] (in _I2C_CCRH) More...

#define	_I2C_FS ((uint8_t) (0x01 << 7))
	I2C Master mode selection [0] (in _I2C_CCRH) More...

#define	_I2C_TRISE ((uint8_t) (0x3F << 0))
	I2C Maximum rise time (Master mode) [5:0] (in _I2C_TRISER) More...

#define	_I2C_TRISE0 ((uint8_t) (0x01 << 0))
	I2C Maximum rise time (Master mode) [0] (in _I2C_TRISER) More...

#define	_I2C_TRISE1 ((uint8_t) (0x01 << 1))
	I2C Maximum rise time (Master mode) [1] (in _I2C_TRISER) More...

#define	_I2C_TRISE2 ((uint8_t) (0x01 << 2))
	I2C Maximum rise time (Master mode) [2] (in _I2C_TRISER) More...

#define	_I2C_TRISE3 ((uint8_t) (0x01 << 3))
	I2C Maximum rise time (Master mode) [3] (in _I2C_TRISER) More...

#define	_I2C_TRISE4 ((uint8_t) (0x01 << 4))
	I2C Maximum rise time (Master mode) [4] (in _I2C_TRISER) More...

#define	_I2C_TRISE5 ((uint8_t) (0x01 << 5))
	I2C Maximum rise time (Master mode) [5] (in _I2C_TRISER) More...

#define	_UART1 _SFR(UART1_t, UART1_AddressBase)
	UART1 struct/bit access. More...

#define	_UART1_SR _SFR(uint8_t, UART1_AddressBase+0x00)
	UART1 Status register. More...

#define	_UART1_DR _SFR(uint8_t, UART1_AddressBase+0x01)
	UART1 data register. More...

#define	_UART1_BRR1 _SFR(uint8_t, UART1_AddressBase+0x02)
	UART1 Baud rate register 1. More...

#define	_UART1_BRR2 _SFR(uint8_t, UART1_AddressBase+0x03)
	UART1 Baud rate register 2. More...

#define	_UART1_CR1 _SFR(uint8_t, UART1_AddressBase+0x04)
	UART1 Control register 1. More...

#define	_UART1_CR2 _SFR(uint8_t, UART1_AddressBase+0x05)
	UART1 Control register 2. More...

#define	_UART1_CR3 _SFR(uint8_t, UART1_AddressBase+0x06)
	UART1 Control register 3. More...

#define	_UART1_CR4 _SFR(uint8_t, UART1_AddressBase+0x07)
	UART1 Control register 4. More...

#define	_UART1_CR5 _SFR(uint8_t, UART1_AddressBase+0x08)
	UART1 Control register 5. More...

#define	_UART1_GTR _SFR(uint8_t, UART1_AddressBase+0x09)
	UART1 guard time register. More...

#define	_UART1_PSCR _SFR(uint8_t, UART1_AddressBase+0x0A)
	UART1 prescaler register. More...

#define	_UART1_SR_RESET_VALUE ((uint8_t) 0xC0)
	UART1 Status register reset value. More...

#define	_UART1_BRR1_RESET_VALUE ((uint8_t) 0x00)
	UART1 Baud rate register 1 reset value. More...

#define	_UART1_BRR2_RESET_VALUE ((uint8_t) 0x00)
	UART1 Baud rate register 2 reset value. More...

#define	_UART1_CR1_RESET_VALUE ((uint8_t) 0x00)
	UART1 Control register 1 reset value. More...

#define	_UART1_CR2_RESET_VALUE ((uint8_t) 0x00)
	UART1 Control register 2 reset value. More...

#define	_UART1_CR3_RESET_VALUE ((uint8_t) 0x00)
	UART1 Control register 3 reset value. More...

#define	_UART1_CR4_RESET_VALUE ((uint8_t) 0x00)
	UART1 Control register 4 reset value. More...

#define	_UART1_CR5_RESET_VALUE ((uint8_t) 0x00)
	UART1 Control register 5 reset value. More...

#define	_UART1_GTR_RESET_VALUE ((uint8_t) 0x00)
	UART1 guard time register reset value. More...

#define	_UART1_PSCR_RESET_VALUE ((uint8_t) 0x00)
	UART1 prescaler register reset value. More...

#define	_UART1_PE ((uint8_t) (0x01 << 0))
	UART1 Parity error [0] (in _UART1_SR) More...

#define	_UART1_FE ((uint8_t) (0x01 << 1))
	UART1 Framing error [0] (in _UART1_SR) More...

#define	_UART1_NF ((uint8_t) (0x01 << 2))
	UART1 Noise flag [0] (in _UART1_SR) More...

#define	_UART1_OR_LHE ((uint8_t) (0x01 << 3))
	UART1 LIN Header Error (LIN slave mode) / Overrun error [0] (in _UART1_SR) More...

#define	_UART1_IDLE ((uint8_t) (0x01 << 4))
	UART1 IDLE line detected [0] (in _UART1_SR) More...

#define	_UART1_RXNE ((uint8_t) (0x01 << 5))
	UART1 Read data register not empty [0] (in _UART1_SR) More...

#define	_UART1_TC ((uint8_t) (0x01 << 6))
	UART1 Transmission complete [0] (in _UART1_SR) More...

#define	_UART1_TXE ((uint8_t) (0x01 << 7))
	UART1 Transmit data register empty [0] (in _UART1_SR) More...

#define	_UART1_PIEN ((uint8_t) (0x01 << 0))
	UART1 Parity interrupt enable [0] (in _UART1_CR1) More...

#define	_UART1_PS ((uint8_t) (0x01 << 1))
	UART1 Parity selection [0] (in _UART1_CR1) More...

#define	_UART1_PCEN ((uint8_t) (0x01 << 2))
	UART1 Parity control enable [0] (in _UART1_CR1) More...

#define	_UART1_WAKE ((uint8_t) (0x01 << 3))
	UART1 Wakeup method [0] (in _UART1_CR1) More...

#define	_UART1_M ((uint8_t) (0x01 << 4))
	UART1 word length [0] (in _UART1_CR1) More...

#define	_UART1_UARTD ((uint8_t) (0x01 << 5))
	UART1 Disable (for low power consumption) [0] (in _UART1_CR1) More...

#define	_UART1_T8 ((uint8_t) (0x01 << 6))
	UART1 Transmit Data bit 8 (in 9-bit mode) [0] (in _UART1_CR1) More...

#define	_UART1_R8 ((uint8_t) (0x01 << 7))
	UART1 Receive Data bit 8 (in 9-bit mode) [0] (in _UART1_CR1) More...

#define	_UART1_SBK ((uint8_t) (0x01 << 0))
	UART1 Send break [0] (in _UART1_CR2) More...

#define	_UART1_RWU ((uint8_t) (0x01 << 1))
	UART1 Receiver wakeup [0] (in _UART1_CR2) More...

#define	_UART1_REN ((uint8_t) (0x01 << 2))
	UART1 Receiver enable [0] (in _UART1_CR2) More...

#define	_UART1_TEN ((uint8_t) (0x01 << 3))
	UART1 Transmitter enable [0] (in _UART1_CR2) More...

#define	_UART1_ILIEN ((uint8_t) (0x01 << 4))
	UART1 IDLE Line interrupt enable [0] (in _UART1_CR2) More...

#define	_UART1_RIEN ((uint8_t) (0x01 << 5))
	UART1 Receiver interrupt enable [0] (in _UART1_CR2) More...

#define	_UART1_TCIEN ((uint8_t) (0x01 << 6))
	UART1 Transmission complete interrupt enable [0] (in _UART1_CR2) More...

#define	_UART1_TIEN ((uint8_t) (0x01 << 7))
	UART1 Transmitter interrupt enable [0] (in _UART1_CR2) More...

#define	_UART1_LBCL ((uint8_t) (0x01 << 0))
	UART1 Last bit clock pulse [0] (in _UART1_CR3) More...

#define	_UART1_CPHA ((uint8_t) (0x01 << 1))
	UART1 Clock phase [0] (in _UART1_CR3) More...

#define	_UART1_CPOL ((uint8_t) (0x01 << 2))
	UART1 Clock polarity [0] (in _UART1_CR3) More...

#define	_UART1_CKEN ((uint8_t) (0x01 << 3))
	UART1 Clock enable [0] (in _UART1_CR3) More...

#define	_UART1_STOP ((uint8_t) (0x03 << 4))
	UART1 STOP bits [1:0] (in _UART1_CR3) More...

#define	_UART1_STOP0 ((uint8_t) (0x01 << 4))
	UART1 STOP bits [0] (in _UART1_CR3) More...

#define	_UART1_STOP1 ((uint8_t) (0x01 << 5))
	UART1 STOP bits [1] (in _UART1_CR3) More...

#define	_UART1_LINEN ((uint8_t) (0x01 << 6))
	UART1 LIN mode enable [0] (in _UART1_CR3) More...

#define	_UART1_ADD ((uint8_t) (0x0F << 0))
	UART1 Address of the UART node [3:0] (in _UART1_CR4) More...

#define	_UART1_ADD0 ((uint8_t) (0x01 << 0))
	UART1 Address of the UART node [0] (in _UART1_CR4) More...

#define	_UART1_ADD1 ((uint8_t) (0x01 << 1))
	UART1 Address of the UART node [1] (in _UART1_CR4) More...

#define	_UART1_ADD2 ((uint8_t) (0x01 << 2))
	UART1 Address of the UART node [2] (in _UART1_CR4) More...

#define	_UART1_ADD3 ((uint8_t) (0x01 << 3))
	UART1 Address of the UART node [3] (in _UART1_CR4) More...

#define	_UART1_LBDF ((uint8_t) (0x01 << 4))
	UART1 LIN Break Detection Flag [0] (in _UART1_CR4) More...

#define	_UART1_LBDL ((uint8_t) (0x01 << 5))
	UART1 LIN Break Detection Length [0] (in _UART1_CR4) More...

#define	_UART1_LBDIEN ((uint8_t) (0x01 << 6))
	UART1 LIN Break Detection Interrupt Enable [0] (in _UART1_CR4) More...

#define	_UART1_IREN ((uint8_t) (0x01 << 1))
	UART1 IrDA mode Enable [0] (in _UART1_CR5) More...

#define	_UART1_IRLP ((uint8_t) (0x01 << 2))
	UART1 IrDA Low Power [0] (in _UART1_CR5) More...

#define	_UART1_HDSEL ((uint8_t) (0x01 << 3))
	UART1 Half-Duplex Selection [0] (in _UART1_CR5) More...

#define	_UART1_NACK ((uint8_t) (0x01 << 4))
	UART1 Smartcard NACK enable [0] (in _UART1_CR5) More...

#define	_UART1_SCEN ((uint8_t) (0x01 << 5))
	UART1 Smartcard mode enable [0] (in _UART1_CR5) More...

#define	_UART2 _SFR(UART2_t, UART2_AddressBase)
	UART2 struct/bit access. More...

#define	_UART2_SR _SFR(uint8_t, UART2_AddressBase+0x00)
	UART2 Status register. More...

#define	_UART2_DR _SFR(uint8_t, UART2_AddressBase+0x01)
	UART2 data register. More...

#define	_UART2_BRR1 _SFR(uint8_t, UART2_AddressBase+0x02)
	UART2 Baud rate register 1. More...

#define	_UART2_BRR2 _SFR(uint8_t, UART2_AddressBase+0x03)
	UART2 Baud rate register 2. More...

#define	_UART2_CR1 _SFR(uint8_t, UART2_AddressBase+0x04)
	UART2 Control register 1. More...

#define	_UART2_CR2 _SFR(uint8_t, UART2_AddressBase+0x05)
	UART2 Control register 2. More...

#define	_UART2_CR3 _SFR(uint8_t, UART2_AddressBase+0x06)
	UART2 Control register 3. More...

#define	_UART2_CR4 _SFR(uint8_t, UART2_AddressBase+0x07)
	UART2 Control register 4. More...

#define	_UART2_CR5 _SFR(uint8_t, UART2_AddressBase+0x08)
	UART2 Control register 5. More...

#define	_UART2_CR6 _SFR(uint8_t, UART2_AddressBase+0x09)
	UART2 Control register 6. More...

#define	_UART2_GTR _SFR(uint8_t, UART2_AddressBase+0x0A)
	UART2 guard time register. More...

#define	_UART2_PSCR _SFR(uint8_t, UART2_AddressBase+0x0B)
	UART2 prescaler register. More...

#define	_UART2_SR_RESET_VALUE ((uint8_t) 0xC0)
	UART2 Status register reset value. More...

#define	_UART2_BRR1_RESET_VALUE ((uint8_t) 0x00)
	UART2 Baud rate register 1 reset value. More...

#define	_UART2_BRR2_RESET_VALUE ((uint8_t) 0x00)
	UART2 Baud rate register 2 reset value. More...

#define	_UART2_CR1_RESET_VALUE ((uint8_t) 0x00)
	UART2 Control register 1 reset value. More...

#define	_UART2_CR2_RESET_VALUE ((uint8_t) 0x00)
	UART2 Control register 2 reset value. More...

#define	_UART2_CR3_RESET_VALUE ((uint8_t) 0x00)
	UART2 Control register 3 reset value. More...

#define	_UART2_CR4_RESET_VALUE ((uint8_t) 0x00)
	UART2 Control register 4 reset value. More...

#define	_UART2_CR5_RESET_VALUE ((uint8_t) 0x00)
	UART2 Control register 5 reset value. More...

#define	_UART2_CR6_RESET_VALUE ((uint8_t) 0x00)
	UART2 Control register 6 reset value. More...

#define	_UART2_GTR_RESET_VALUE ((uint8_t) 0x00)
	UART2 guard time register reset value. More...

#define	_UART2_PSCR_RESET_VALUE ((uint8_t) 0x00)
	UART2 prescaler register reset value. More...

#define	_UART2_PE ((uint8_t) (0x01 << 0))
	UART2 Parity error [0] (in _UART2_SR) More...

#define	_UART2_FE ((uint8_t) (0x01 << 1))
	UART2 Framing error [0] (in _UART2_SR) More...

#define	_UART2_NF ((uint8_t) (0x01 << 2))
	UART2 Noise flag [0] (in _UART2_SR) More...

#define	_UART2_OR_LHE ((uint8_t) (0x01 << 3))
	UART2 LIN Header Error (LIN slave mode) / Overrun error [0] (in _UART2_SR) More...

#define	_UART2_IDLE ((uint8_t) (0x01 << 4))
	UART2 IDLE line detected [0] (in _UART2_SR) More...

#define	_UART2_RXNE ((uint8_t) (0x01 << 5))
	UART2 Read data register not empty [0] (in _UART2_SR) More...

#define	_UART2_TC ((uint8_t) (0x01 << 6))
	UART2 Transmission complete [0] (in _UART2_SR) More...

#define	_UART2_TXE ((uint8_t) (0x01 << 7))
	UART2 Transmit data register empty [0] (in _UART2_SR) More...

#define	_UART2_PIEN ((uint8_t) (0x01 << 0))
	UART2 Parity interrupt enable [0] (in _UART2_CR1) More...

#define	_UART2_PS ((uint8_t) (0x01 << 1))
	UART2 Parity selection [0] (in _UART2_CR1) More...

#define	_UART2_PCEN ((uint8_t) (0x01 << 2))
	UART2 Parity control enable [0] (in _UART2_CR1) More...

#define	_UART2_WAKE ((uint8_t) (0x01 << 3))
	UART2 Wakeup method [0] (in _UART2_CR1) More...

#define	_UART2_M ((uint8_t) (0x01 << 4))
	UART2 word length [0] (in _UART2_CR1) More...

#define	_UART2_UARTD ((uint8_t) (0x01 << 5))
	UART2 Disable (for low power consumption) [0] (in _UART2_CR1) More...

#define	_UART2_T8 ((uint8_t) (0x01 << 6))
	UART2 Transmit Data bit 8 (in 9-bit mode) [0] (in _UART2_CR1) More...

#define	_UART2_R8 ((uint8_t) (0x01 << 7))
	UART2 Receive Data bit 8 (in 9-bit mode) [0] (in _UART2_CR1) More...

#define	_UART2_SBK ((uint8_t) (0x01 << 0))
	UART2 Send break [0] (in _UART2_CR2) More...

#define	_UART2_RWU ((uint8_t) (0x01 << 1))
	UART2 Receiver wakeup [0] (in _UART2_CR2) More...

#define	_UART2_REN ((uint8_t) (0x01 << 2))
	UART2 Receiver enable [0] (in _UART2_CR2) More...

#define	_UART2_TEN ((uint8_t) (0x01 << 3))
	UART2 Transmitter enable [0] (in _UART2_CR2) More...

#define	_UART2_ILIEN ((uint8_t) (0x01 << 4))
	UART2 IDLE Line interrupt enable [0] (in _UART2_CR2) More...

#define	_UART2_RIEN ((uint8_t) (0x01 << 5))
	UART2 Receiver interrupt enable [0] (in _UART2_CR2) More...

#define	_UART2_TCIEN ((uint8_t) (0x01 << 6))
	UART2 Transmission complete interrupt enable [0] (in _UART2_CR2) More...

#define	_UART2_TIEN ((uint8_t) (0x01 << 7))
	UART2 Transmitter interrupt enable [0] (in _UART2_CR2) More...

#define	_UART2_LBCL ((uint8_t) (0x01 << 0))
	UART2 Last bit clock pulse [0] (in _UART2_CR3) More...

#define	_UART2_CPHA ((uint8_t) (0x01 << 1))
	UART2 Clock phase [0] (in _UART2_CR3) More...

#define	_UART2_CPOL ((uint8_t) (0x01 << 2))
	UART2 Clock polarity [0] (in _UART2_CR3) More...

#define	_UART2_CKEN ((uint8_t) (0x01 << 3))
	UART2 Clock enable [0] (in _UART2_CR3) More...

#define	_UART2_STOP ((uint8_t) (0x03 << 4))
	UART2 STOP bits [1:0] (in _UART2_CR3) More...

#define	_UART2_STOP0 ((uint8_t) (0x01 << 4))
	UART2 STOP bits [0] (in _UART2_CR3) More...

#define	_UART2_STOP1 ((uint8_t) (0x01 << 5))
	UART2 STOP bits [1] (in _UART2_CR3) More...

#define	_UART2_LINEN ((uint8_t) (0x01 << 6))
	UART2 LIN mode enable [0] (in _UART2_CR3) More...

#define	_UART2_ADD ((uint8_t) (0x0F << 0))
	UART2 Address of the UART node [3:0] (in _UART2_CR4) More...

#define	_UART2_ADD0 ((uint8_t) (0x01 << 0))
	UART2 Address of the UART node [0] (in _UART2_CR4) More...

#define	_UART2_ADD1 ((uint8_t) (0x01 << 1))
	UART2 Address of the UART node [1] (in _UART2_CR4) More...

#define	_UART2_ADD2 ((uint8_t) (0x01 << 2))
	UART2 Address of the UART node [2] (in _UART2_CR4) More...

#define	_UART2_ADD3 ((uint8_t) (0x01 << 3))
	UART2 Address of the UART node [3] (in _UART2_CR4) More...

#define	_UART2_LBDF ((uint8_t) (0x01 << 4))
	UART2 LIN Break Detection Flag [0] (in _UART2_CR4) More...

#define	_UART2_LBDL ((uint8_t) (0x01 << 5))
	UART2 LIN Break Detection Length [0] (in _UART2_CR4) More...

#define	_UART2_LBDIEN ((uint8_t) (0x01 << 6))
	UART2 LIN Break Detection Interrupt Enable [0] (in _UART2_CR4) More...

#define	_UART2_IREN ((uint8_t) (0x01 << 1))
	UART2 IrDA mode Enable [0] (in _UART2_CR5) More...

#define	_UART2_IRLP ((uint8_t) (0x01 << 2))
	UART2 IrDA Low Power [0] (in _UART2_CR5) More...

#define	_UART2_NACK ((uint8_t) (0x01 << 4))
	UART2 Smartcard NACK enable [0] (in _UART2_CR5) More...

#define	_UART2_SCEN ((uint8_t) (0x01 << 5))
	UART2 Smartcard mode enable [0] (in _UART2_CR5) More...

#define	_UART2_LSF ((uint8_t) (0x01 << 0))
	UART2 LIN Sync Field [0] (in _UART2_CR6) More...

#define	_UART2_LHDF ((uint8_t) (0x01 << 1))
	UART2 LIN Header Detection Flag [0] (in _UART2_CR6) More...

#define	_UART2_LHDIEN ((uint8_t) (0x01 << 2))
	UART2 LIN Header Detection Interrupt Enable [0] (in _UART2_CR6) More...

#define	_UART2_LASE ((uint8_t) (0x01 << 4))
	UART2 LIN automatic resynchronisation enable [0] (in _UART2_CR6) More...

#define	_UART2_LSLV ((uint8_t) (0x01 << 5))
	UART2 LIN Slave Enable [0] (in _UART2_CR6) More...

#define	_UART2_LDUM ((uint8_t) (0x01 << 7))
	UART2 LIN Divider Update Method [0] (in _UART2_CR6) More...

#define	_UART3 _SFR(UART3_t, UART3_AddressBase)
	UART3 struct/bit access. More...

#define	_UART3_SR _SFR(uint8_t, UART3_AddressBase+0x00)
	UART3 Status register. More...

#define	_UART3_DR _SFR(uint8_t, UART3_AddressBase+0x01)
	UART3 data register. More...

#define	_UART3_BRR1 _SFR(uint8_t, UART3_AddressBase+0x02)
	UART3 Baud rate register 1. More...

#define	_UART3_BRR2 _SFR(uint8_t, UART3_AddressBase+0x03)
	UART3 Baud rate register 2. More...

#define	_UART3_CR1 _SFR(uint8_t, UART3_AddressBase+0x04)
	UART3 Control register 1. More...

#define	_UART3_CR2 _SFR(uint8_t, UART3_AddressBase+0x05)
	UART3 Control register 2. More...

#define	_UART3_CR3 _SFR(uint8_t, UART3_AddressBase+0x06)
	UART3 Control register 3. More...

#define	_UART3_CR4 _SFR(uint8_t, UART3_AddressBase+0x07)
	UART3 Control register 4. More...

#define	_UART3_CR6 _SFR(uint8_t, UART3_AddressBase+0x09)
	UART3 Control register 6. More...

#define	_UART3_SR_RESET_VALUE ((uint8_t) 0xC0)
	UART3 Status register reset value. More...

#define	_UART3_BRR1_RESET_VALUE ((uint8_t) 0x00)
	UART3 Baud rate register 1 reset value. More...

#define	_UART3_BRR2_RESET_VALUE ((uint8_t) 0x00)
	UART3 Baud rate register 2 reset value. More...

#define	_UART3_CR1_RESET_VALUE ((uint8_t) 0x00)
	UART3 Control register 1 reset value. More...

#define	_UART3_CR2_RESET_VALUE ((uint8_t) 0x00)
	UART3 Control register 2 reset value. More...

#define	_UART3_CR3_RESET_VALUE ((uint8_t) 0x00)
	UART3 Control register 3 reset value. More...

#define	_UART3_CR4_RESET_VALUE ((uint8_t) 0x00)
	UART3 Control register 4 reset value. More...

#define	_UART3_CR6_RESET_VALUE ((uint8_t) 0x00)
	UART3 Control register 6 reset value. More...

#define	_UART3_PE ((uint8_t) (0x01 << 0))
	UART3 Parity error [0] (in _UART3_SR) More...

#define	_UART3_FE ((uint8_t) (0x01 << 1))
	UART3 Framing error [0] (in _UART3_SR) More...

#define	_UART3_NF ((uint8_t) (0x01 << 2))
	UART3 Noise flag [0] (in _UART3_SR) More...

#define	_UART3_OR_LHE ((uint8_t) (0x01 << 3))
	UART3 LIN Header Error (LIN slave mode) / Overrun error [0] (in _UART3_SR) More...

#define	_UART3_IDLE ((uint8_t) (0x01 << 4))
	UART3 IDLE line detected [0] (in _UART3_SR) More...

#define	_UART3_RXNE ((uint8_t) (0x01 << 5))
	UART3 Read data register not empty [0] (in _UART3_SR) More...

#define	_UART3_TC ((uint8_t) (0x01 << 6))
	UART3 Transmission complete [0] (in _UART3_SR) More...

#define	_UART3_TXE ((uint8_t) (0x01 << 7))
	UART3 Transmit data register empty [0] (in _UART3_SR) More...

#define	_UART3_PIEN ((uint8_t) (0x01 << 0))
	UART3 Parity interrupt enable [0] (in _UART3_CR1) More...

#define	_UART3_PS ((uint8_t) (0x01 << 1))
	UART3 Parity selection [0] (in _UART3_CR1) More...

#define	_UART3_PCEN ((uint8_t) (0x01 << 2))
	UART3 Parity control enable [0] (in _UART3_CR1) More...

#define	_UART3_WAKE ((uint8_t) (0x01 << 3))
	UART3 Wakeup method [0] (in _UART3_CR1) More...

#define	_UART3_M ((uint8_t) (0x01 << 4))
	UART3 word length [0] (in _UART3_CR1) More...

#define	_UART3_UARTD ((uint8_t) (0x01 << 5))
	UART3 Disable (for low power consumption) [0] (in _UART3_CR1) More...

#define	_UART3_T8 ((uint8_t) (0x01 << 6))
	UART3 Transmit Data bit 8 (in 9-bit mode) [0] (in _UART3_CR1) More...

#define	_UART3_R8 ((uint8_t) (0x01 << 7))
	UART3 Receive Data bit 8 (in 9-bit mode) [0] (in _UART3_CR1) More...

#define	_UART3_SBK ((uint8_t) (0x01 << 0))
	UART3 Send break [0] (in _UART3_CR2) More...

#define	_UART3_RWU ((uint8_t) (0x01 << 1))
	UART3 Receiver wakeup [0] (in _UART3_CR2) More...

#define	_UART3_REN ((uint8_t) (0x01 << 2))
	UART3 Receiver enable [0] (in _UART3_CR2) More...

#define	_UART3_TEN ((uint8_t) (0x01 << 3))
	UART3 Transmitter enable [0] (in _UART3_CR2) More...

#define	_UART3_ILIEN ((uint8_t) (0x01 << 4))
	UART3 IDLE Line interrupt enable [0] (in _UART3_CR2) More...

#define	_UART3_RIEN ((uint8_t) (0x01 << 5))
	UART3 Receiver interrupt enable [0] (in _UART3_CR2) More...

#define	_UART3_TCIEN ((uint8_t) (0x01 << 6))
	UART3 Transmission complete interrupt enable [0] (in _UART3_CR2) More...

#define	_UART3_TIEN ((uint8_t) (0x01 << 7))
	UART3 Transmitter interrupt enable [0] (in _UART3_CR2) More...

#define	_UART3_STOP ((uint8_t) (0x03 << 4))
	UART3 STOP bits [1:0] (in _UART3_CR3) More...

#define	_UART3_STOP0 ((uint8_t) (0x01 << 4))
	UART3 STOP bits [0] (in _UART3_CR3) More...

#define	_UART3_STOP1 ((uint8_t) (0x01 << 5))
	UART3 STOP bits [1] (in _UART3_CR3) More...

#define	_UART3_LINEN ((uint8_t) (0x01 << 6))
	UART3 LIN mode enable [0] (in _UART3_CR3) More...

#define	_UART3_ADD ((uint8_t) (0x0F << 0))
	UART3 Address of the UART node [3:0] (in _UART3_CR4) More...

#define	_UART3_ADD0 ((uint8_t) (0x01 << 0))
	UART3 Address of the UART node [0] (in _UART3_CR4) More...

#define	_UART3_ADD1 ((uint8_t) (0x01 << 1))
	UART3 Address of the UART node [1] (in _UART3_CR4) More...

#define	_UART3_ADD2 ((uint8_t) (0x01 << 2))
	UART3 Address of the UART node [2] (in _UART3_CR4) More...

#define	_UART3_ADD3 ((uint8_t) (0x01 << 3))
	UART3 Address of the UART node [3] (in _UART3_CR4) More...

#define	_UART3_LBDF ((uint8_t) (0x01 << 4))
	UART3 LIN Break Detection Flag [0] (in _UART3_CR4) More...

#define	_UART3_LBDL ((uint8_t) (0x01 << 5))
	UART3 LIN Break Detection Length [0] (in _UART3_CR4) More...

#define	_UART3_LBDIEN ((uint8_t) (0x01 << 6))
	UART3 LIN Break Detection Interrupt Enable [0] (in _UART3_CR4) More...

#define	_UART3_LSF ((uint8_t) (0x01 << 0))
	UART3 LIN Sync Field [0] (in _UART3_CR6) More...

#define	_UART3_LHDF ((uint8_t) (0x01 << 1))
	UART3 LIN Header Detection Flag [0] (in _UART3_CR6) More...

#define	_UART3_LHDIEN ((uint8_t) (0x01 << 2))
	UART3 LIN Header Detection Interrupt Enable [0] (in _UART3_CR6) More...

#define	_UART3_LASE ((uint8_t) (0x01 << 4))
	UART3 LIN automatic resynchronisation enable [0] (in _UART3_CR6) More...

#define	_UART3_LSLV ((uint8_t) (0x01 << 5))
	UART3 LIN Slave Enable [0] (in _UART3_CR6) More...

#define	_UART3_LDUM ((uint8_t) (0x01 << 7))
	UART3 LIN Divider Update Method [0] (in _UART3_CR6) More...

#define	_UART4 _SFR(UART4_t, UART4_AddressBase)
	UART4 struct/bit access. More...

#define	_UART4_SR _SFR(uint8_t, UART4_AddressBase+0x00)
	UART4 Status register. More...

#define	_UART4_DR _SFR(uint8_t, UART4_AddressBase+0x01)
	UART4 data register. More...

#define	_UART4_BRR1 _SFR(uint8_t, UART4_AddressBase+0x02)
	UART4 Baud rate register 1. More...

#define	_UART4_BRR2 _SFR(uint8_t, UART4_AddressBase+0x03)
	UART4 Baud rate register 2. More...

#define	_UART4_CR1 _SFR(uint8_t, UART4_AddressBase+0x04)
	UART4 Control register 1. More...

#define	_UART4_CR2 _SFR(uint8_t, UART4_AddressBase+0x05)
	UART4 Control register 2. More...

#define	_UART4_CR3 _SFR(uint8_t, UART4_AddressBase+0x06)
	UART4 Control register 3. More...

#define	_UART4_CR4 _SFR(uint8_t, UART4_AddressBase+0x07)
	UART4 Control register 4. More...

#define	_UART4_CR5 _SFR(uint8_t, UART4_AddressBase+0x08)
	UART4 Control register 5. More...

#define	_UART4_CR6 _SFR(uint8_t, UART4_AddressBase+0x09)
	UART4 Control register 6. More...

#define	_UART4_GTR _SFR(uint8_t, UART4_AddressBase+0x0A)
	UART4 guard time register. More...

#define	_UART4_PSCR _SFR(uint8_t, UART4_AddressBase+0x0B)
	UART4 prescaler register. More...

#define	_UART4_SR_RESET_VALUE ((uint8_t) 0xC0)
	UART4 Status register reset value. More...

#define	_UART4_BRR1_RESET_VALUE ((uint8_t) 0x00)
	UART4 Baud rate register 1 reset value. More...

#define	_UART4_BRR2_RESET_VALUE ((uint8_t) 0x00)
	UART4 Baud rate register 2 reset value. More...

#define	_UART4_CR1_RESET_VALUE ((uint8_t) 0x00)
	UART4 Control register 1 reset value. More...

#define	_UART4_CR2_RESET_VALUE ((uint8_t) 0x00)
	UART4 Control register 2 reset value. More...

#define	_UART4_CR3_RESET_VALUE ((uint8_t) 0x00)
	UART4 Control register 3 reset value. More...

#define	_UART4_CR4_RESET_VALUE ((uint8_t) 0x00)
	UART4 Control register 4 reset value. More...

#define	_UART4_CR5_RESET_VALUE ((uint8_t) 0x00)
	UART4 Control register 5 reset value. More...

#define	_UART4_CR6_RESET_VALUE ((uint8_t) 0x00)
	UART4 Control register 6 reset value. More...

#define	_UART4_GTR_RESET_VALUE ((uint8_t) 0x00)
	UART4 guard time register reset value. More...

#define	_UART4_PSCR_RESET_VALUE ((uint8_t) 0x00)
	UART4 prescaler register reset value. More...

#define	_UART4_PE ((uint8_t) (0x01 << 0))
	UART4 Parity error [0] (in _UART4_SR) More...

#define	_UART4_FE ((uint8_t) (0x01 << 1))
	UART4 Framing error [0] (in _UART4_SR) More...

#define	_UART4_NF ((uint8_t) (0x01 << 2))
	UART4 Noise flag [0] (in _UART4_SR) More...

#define	_UART4_OR_LHE ((uint8_t) (0x01 << 3))
	UART4 LIN Header Error (LIN slave mode) / Overrun error [0] (in _UART4_SR) More...

#define	_UART4_IDLE ((uint8_t) (0x01 << 4))
	UART4 IDLE line detected [0] (in _UART4_SR) More...

#define	_UART4_RXNE ((uint8_t) (0x01 << 5))
	UART4 Read data register not empty [0] (in _UART4_SR) More...

#define	_UART4_TC ((uint8_t) (0x01 << 6))
	UART4 Transmission complete [0] (in _UART4_SR) More...

#define	_UART4_TXE ((uint8_t) (0x01 << 7))
	UART4 Transmit data register empty [0] (in _UART4_SR) More...

#define	_UART4_PIEN ((uint8_t) (0x01 << 0))
	UART4 Parity interrupt enable [0] (in _UART4_CR1) More...

#define	_UART4_PS ((uint8_t) (0x01 << 1))
	UART4 Parity selection [0] (in _UART4_CR1) More...

#define	_UART4_PCEN ((uint8_t) (0x01 << 2))
	UART4 Parity control enable [0] (in _UART4_CR1) More...

#define	_UART4_WAKE ((uint8_t) (0x01 << 3))
	UART4 Wakeup method [0] (in _UART4_CR1) More...

#define	_UART4_M ((uint8_t) (0x01 << 4))
	UART4 word length [0] (in _UART4_CR1) More...

#define	_UART4_UARTD ((uint8_t) (0x01 << 5))
	UART4 Disable (for low power consumption) [0] (in _UART4_CR1) More...

#define	_UART4_T8 ((uint8_t) (0x01 << 6))
	UART4 Transmit Data bit 8 (in 9-bit mode) [0] (in _UART4_CR1) More...

#define	_UART4_R8 ((uint8_t) (0x01 << 7))
	UART4 Receive Data bit 8 (in 9-bit mode) [0] (in _UART4_CR1) More...

#define	_UART4_SBK ((uint8_t) (0x01 << 0))
	UART4 Send break [0] (in _UART4_CR2) More...

#define	_UART4_RWU ((uint8_t) (0x01 << 1))
	UART4 Receiver wakeup [0] (in _UART4_CR2) More...

#define	_UART4_REN ((uint8_t) (0x01 << 2))
	UART4 Receiver enable [0] (in _UART4_CR2) More...

#define	_UART4_TEN ((uint8_t) (0x01 << 3))
	UART4 Transmitter enable [0] (in _UART4_CR2) More...

#define	_UART4_ILIEN ((uint8_t) (0x01 << 4))
	UART4 IDLE Line interrupt enable [0] (in _UART4_CR2) More...

#define	_UART4_RIEN ((uint8_t) (0x01 << 5))
	UART4 Receiver interrupt enable [0] (in _UART4_CR2) More...

#define	_UART4_TCIEN ((uint8_t) (0x01 << 6))
	UART4 Transmission complete interrupt enable [0] (in _UART4_CR2) More...

#define	_UART4_TIEN ((uint8_t) (0x01 << 7))
	UART4 Transmitter interrupt enable [0] (in _UART4_CR2) More...

#define	_UART4_LBCL ((uint8_t) (0x01 << 0))
	UART4 Last bit clock pulse [0] (in _UART4_CR3) More...

#define	_UART4_CPHA ((uint8_t) (0x01 << 1))
	UART4 Clock phase [0] (in _UART4_CR3) More...

#define	_UART4_CPOL ((uint8_t) (0x01 << 2))
	UART4 Clock polarity [0] (in _UART4_CR3) More...

#define	_UART4_CKEN ((uint8_t) (0x01 << 3))
	UART4 Clock enable [0] (in _UART4_CR3) More...

#define	_UART4_STOP ((uint8_t) (0x03 << 4))
	UART4 STOP bits [1:0] (in _UART4_CR3) More...

#define	_UART4_STOP0 ((uint8_t) (0x01 << 4))
	UART4 STOP bits [0] (in _UART4_CR3) More...

#define	_UART4_STOP1 ((uint8_t) (0x01 << 5))
	UART4 STOP bits [1] (in _UART4_CR3) More...

#define	_UART4_LINEN ((uint8_t) (0x01 << 6))
	UART4 LIN mode enable [0] (in _UART4_CR3) More...

#define	_UART4_ADD ((uint8_t) (0x0F << 0))
	UART4 Address of the UART node [3:0] (in _UART4_CR4) More...

#define	_UART4_ADD0 ((uint8_t) (0x01 << 0))
	UART4 Address of the UART node [0] (in _UART4_CR4) More...

#define	_UART4_ADD1 ((uint8_t) (0x01 << 1))
	UART4 Address of the UART node [1] (in _UART4_CR4) More...

#define	_UART4_ADD2 ((uint8_t) (0x01 << 2))
	UART4 Address of the UART node [2] (in _UART4_CR4) More...

#define	_UART4_ADD3 ((uint8_t) (0x01 << 3))
	UART4 Address of the UART node [3] (in _UART4_CR4) More...

#define	_UART4_LBDF ((uint8_t) (0x01 << 4))
	UART4 LIN Break Detection Flag [0] (in _UART4_CR4) More...

#define	_UART4_LBDL ((uint8_t) (0x01 << 5))
	UART4 LIN Break Detection Length [0] (in _UART4_CR4) More...

#define	_UART4_LBDIEN ((uint8_t) (0x01 << 6))
	UART4 LIN Break Detection Interrupt Enable [0] (in _UART4_CR4) More...

#define	_UART4_IREN ((uint8_t) (0x01 << 1))
	UART4 IrDA mode Enable [0] (in _UART4_CR5) More...

#define	_UART4_IRLP ((uint8_t) (0x01 << 2))
	UART4 IrDA Low Power [0] (in _UART4_CR5) More...

#define	_UART4_HDSEL ((uint8_t) (0x01 << 3))
	UART4 Half-Duplex Selection [0] (in _UART4_CR5) More...

#define	_UART4_NACK ((uint8_t) (0x01 << 4))
	UART4 Smartcard NACK enable [0] (in _UART4_CR5) More...

#define	_UART4_SCEN ((uint8_t) (0x01 << 5))
	UART4 Smartcard mode enable [0] (in _UART4_CR5) More...

#define	_UART4_LSF ((uint8_t) (0x01 << 0))
	UART4 LIN Sync Field [0] (in _UART4_CR6) More...

#define	_UART4_LHDF ((uint8_t) (0x01 << 1))
	UART4 LIN Header Detection Flag [0] (in _UART4_CR6) More...

#define	_UART4_LHDIEN ((uint8_t) (0x01 << 2))
	UART4 LIN Header Detection Interrupt Enable [0] (in _UART4_CR6) More...

#define	_UART4_LASE ((uint8_t) (0x01 << 4))
	UART4 LIN automatic resynchronisation enable [0] (in _UART4_CR6) More...

#define	_UART4_LSLV ((uint8_t) (0x01 << 5))
	UART4 LIN Slave Enable [0] (in _UART4_CR6) More...

#define	_UART4_LDUM ((uint8_t) (0x01 << 7))
	UART4 LIN Divider Update Method [0] (in _UART4_CR6) More...

#define	_TIM1 _SFR(TIM1_t, TIM1_AddressBase)
	TIM1 struct/bit access. More...

#define	_TIM1_CR1 _SFR(uint8_t, TIM1_AddressBase+0x00)
	TIM1 control register 1. More...

#define	_TIM1_CR2 _SFR(uint8_t, TIM1_AddressBase+0x01)
	TIM1 control register 2. More...

#define	_TIM1_SMCR _SFR(uint8_t, TIM1_AddressBase+0x02)
	TIM1 Slave mode control register. More...

#define	_TIM1_ETR _SFR(uint8_t, TIM1_AddressBase+0x03)
	TIM1 External trigger register. More...

#define	_TIM1_IER _SFR(uint8_t, TIM1_AddressBase+0x04)
	TIM1 interrupt enable register. More...

#define	_TIM1_SR1 _SFR(uint8_t, TIM1_AddressBase+0x05)
	TIM1 status register 1. More...

#define	_TIM1_SR2 _SFR(uint8_t, TIM1_AddressBase+0x06)
	TIM1 status register 2. More...

#define	_TIM1_EGR _SFR(uint8_t, TIM1_AddressBase+0x07)
	TIM1 Event generation register. More...

#define	_TIM1_CCMR1 _SFR(uint8_t, TIM1_AddressBase+0x08)
	TIM1 Capture/compare mode register 1. More...

#define	_TIM1_CCMR2 _SFR(uint8_t, TIM1_AddressBase+0x09)
	TIM1 Capture/compare mode register 2. More...

#define	_TIM1_CCMR3 _SFR(uint8_t, TIM1_AddressBase+0x0A)
	TIM1 Capture/compare mode register 3. More...

#define	_TIM1_CCMR4 _SFR(uint8_t, TIM1_AddressBase+0x0B)
	TIM1 Capture/compare mode register 4. More...

#define	_TIM1_CCER1 _SFR(uint8_t, TIM1_AddressBase+0x0C)
	TIM1 Capture/compare enable register 1. More...

#define	_TIM1_CCER2 _SFR(uint8_t, TIM1_AddressBase+0x0D)
	TIM1 Capture/compare enable register 2. More...

#define	_TIM1_CNTRH _SFR(uint8_t, TIM1_AddressBase+0x0E)
	TIM1 counter register high byte. More...

#define	_TIM1_CNTRL _SFR(uint8_t, TIM1_AddressBase+0x0F)
	TIM1 counter register low byte. More...

#define	_TIM1_PSCRH _SFR(uint8_t, TIM1_AddressBase+0x10)
	TIM1 clock prescaler register high byte. More...

#define	_TIM1_PSCRL _SFR(uint8_t, TIM1_AddressBase+0x11)
	TIM1 clock prescaler register low byte. More...

#define	_TIM1_ARRH _SFR(uint8_t, TIM1_AddressBase+0x12)
	TIM1 auto-reload register high byte. More...

#define	_TIM1_ARRL _SFR(uint8_t, TIM1_AddressBase+0x13)
	TIM1 auto-reload register low byte. More...

#define	_TIM1_RCR _SFR(uint8_t, TIM1_AddressBase+0x14)
	TIM1 Repetition counter. More...

#define	_TIM1_CCR1H _SFR(uint8_t, TIM1_AddressBase+0x15)
	TIM1 16-bit capture/compare value 1 high byte. More...

#define	_TIM1_CCR1L _SFR(uint8_t, TIM1_AddressBase+0x16)
	TIM1 16-bit capture/compare value 1 low byte. More...

#define	_TIM1_CCR2H _SFR(uint8_t, TIM1_AddressBase+0x17)
	TIM1 16-bit capture/compare value 2 high byte. More...

#define	_TIM1_CCR2L _SFR(uint8_t, TIM1_AddressBase+0x18)
	TIM1 16-bit capture/compare value 2 low byte. More...

#define	_TIM1_CCR3H _SFR(uint8_t, TIM1_AddressBase+0x19)
	TIM1 16-bit capture/compare value 3 high byte. More...

#define	_TIM1_CCR3L _SFR(uint8_t, TIM1_AddressBase+0x1A)
	TIM1 16-bit capture/compare value 3 low byte. More...

#define	_TIM1_CCR4H _SFR(uint8_t, TIM1_AddressBase+0x1B)
	TIM1 16-bit capture/compare value 4 high byte. More...

#define	_TIM1_CCR4L _SFR(uint8_t, TIM1_AddressBase+0x1C)
	TIM1 16-bit capture/compare value 4 low byte. More...

#define	_TIM1_BKR _SFR(uint8_t, TIM1_AddressBase+0x1D)
	TIM1 Break register. More...

#define	_TIM1_DTR _SFR(uint8_t, TIM1_AddressBase+0x1E)
	TIM1 Dead-time register. More...

#define	_TIM1_OISR _SFR(uint8_t, TIM1_AddressBase+0x1F)
	TIM1 Output idle state register. More...

#define	_TIM1_CR1_RESET_VALUE ((uint8_t) 0x00)
	TIM1 control register 1 reset value. More...

#define	_TIM1_CR2_RESET_VALUE ((uint8_t) 0x00)
	TIM1 control register 2 reset value. More...

#define	_TIM1_SMCR_RESET_VALUE ((uint8_t) 0x00)
	TIM1 Slave mode control register reset value. More...

#define	_TIM1_ETR_RESET_VALUE ((uint8_t) 0x00)
	TIM1 External trigger register reset value. More...

#define	_TIM1_IER_RESET_VALUE ((uint8_t) 0x00)
	TIM1 interrupt enable register reset value. More...

#define	_TIM1_SR1_RESET_VALUE ((uint8_t) 0x00)
	TIM1 status register 1 reset value. More...

#define	_TIM1_SR2_RESET_VALUE ((uint8_t) 0x00)
	TIM1 status register 2 reset value. More...

#define	_TIM1_EGR_RESET_VALUE ((uint8_t) 0x00)
	TIM1 Event generation register reset value. More...

#define	_TIM1_CCMR1_RESET_VALUE ((uint8_t) 0x00)
	TIM1 Capture/compare mode register 1 reset value. More...

#define	_TIM1_CCMR2_RESET_VALUE ((uint8_t) 0x00)
	TIM1 Capture/compare mode register 2 reset value. More...

#define	_TIM1_CCMR3_RESET_VALUE ((uint8_t) 0x00)
	TIM1 Capture/compare mode register 3 reset value. More...

#define	_TIM1_CCMR4_RESET_VALUE ((uint8_t) 0x00)
	TIM1 Capture/compare mode register 4 reset value. More...

#define	_TIM1_CCER1_RESET_VALUE ((uint8_t) 0x00)
	TIM1 Capture/compare enable register 1 reset value. More...

#define	_TIM1_CCER2_RESET_VALUE ((uint8_t) 0x00)
	TIM1 Capture/compare enable register 2 reset value. More...

#define	_TIM1_CNTRH_RESET_VALUE ((uint8_t) 0x00)
	TIM1 counter register high byte reset value. More...

#define	_TIM1_CNTRL_RESET_VALUE ((uint8_t) 0x00)
	TIM1 counter register low byte reset value. More...

#define	_TIM1_PSCRH_RESET_VALUE ((uint8_t) 0x00)
	TIM1 clock prescaler register high byte reset value. More...

#define	_TIM1_PSCRL_RESET_VALUE ((uint8_t) 0x00)
	TIM1 clock prescaler register low byte reset value. More...

#define	_TIM1_ARRH_RESET_VALUE ((uint8_t) 0xFF)
	TIM1 auto-reload register high byte reset value. More...

#define	_TIM1_ARRL_RESET_VALUE ((uint8_t) 0xFF)
	TIM1 auto-reload register low byte reset value. More...

#define	_TIM1_RCR_RESET_VALUE ((uint8_t) 0x00)
	TIM1 Repetition counter reset value. More...

#define	_TIM1_CCR1H_RESET_VALUE ((uint8_t) 0x00)
	TIM1 16-bit capture/compare value 1 high byte reset value. More...

#define	_TIM1_CCR1L_RESET_VALUE ((uint8_t) 0x00)
	TIM1 16-bit capture/compare value 1 low byte reset value. More...

#define	_TIM1_CCR2H_RESET_VALUE ((uint8_t) 0x00)
	TIM1 16-bit capture/compare value 2 high byte reset value. More...

#define	_TIM1_CCR2L_RESET_VALUE ((uint8_t) 0x00)
	TIM1 16-bit capture/compare value 2 low byte reset value. More...

#define	_TIM1_CCR3H_RESET_VALUE ((uint8_t) 0x00)
	TIM1 16-bit capture/compare value 3 high byte reset value. More...

#define	_TIM1_CCR3L_RESET_VALUE ((uint8_t) 0x00)
	TIM1 16-bit capture/compare value 3 low byte reset value. More...

#define	_TIM1_CCR4H_RESET_VALUE ((uint8_t) 0x00)
	TIM1 16-bit capture/compare value 4 high byte reset value. More...

#define	_TIM1_CCR4L_RESET_VALUE ((uint8_t) 0x00)
	TIM1 16-bit capture/compare value 4 low byte reset value. More...

#define	_TIM1_BKR_RESET_VALUE ((uint8_t) 0x00)
	TIM1 Break register reset value. More...

#define	_TIM1_DTR_RESET_VALUE ((uint8_t) 0x00)
	TIM1 Dead-time register reset value. More...

#define	_TIM1_OISR_RESET_VALUE ((uint8_t) 0x00)
	TIM1 Output idle state register reset value. More...

#define	_TIM1_CEN ((uint8_t) (0x01 << 0))
	TIM1 Counter enable [0] (in _TIM1_CR1) More...

#define	_TIM1_UDIS ((uint8_t) (0x01 << 1))
	TIM1 Update disable [0] (in _TIM1_CR1) More...

#define	_TIM1_URS ((uint8_t) (0x01 << 2))
	TIM1 Update request source [0] (in _TIM1_CR1) More...

#define	_TIM1_OPM ((uint8_t) (0x01 << 3))
	TIM1 One-pulse mode [0] (in _TIM1_CR1) More...

#define	_TIM1_DIR ((uint8_t) (0x01 << 4))
	TIM1 Direction [0] (in _TIM1_CR1) More...

#define	_TIM1_CMS ((uint8_t) (0x03 << 5))
	TIM1 Center-aligned mode selection [1:0] (in _TIM1_CR1) More...

#define	_TIM1_CMS0 ((uint8_t) (0x01 << 5))
	TIM1 Center-aligned mode selection [0] (in _TIM1_CR1) More...

#define	_TIM1_CMS1 ((uint8_t) (0x01 << 6))
	TIM1 Center-aligned mode selection [1] (in _TIM1_CR1) More...

#define	_TIM1_ARPE ((uint8_t) (0x01 << 7))
	TIM1 Auto-reload preload enable [0] (in _TIM1_CR1) More...

#define	_TIM1_CCPC ((uint8_t) (0x01 << 0))
	TIM1 Capture/compare preloaded control [0] (in _TIM1_CR2) More...

#define	_TIM1_COMS ((uint8_t) (0x01 << 2))
	TIM1 Capture/compare control update selection [0] (in _TIM1_CR2) More...

#define	_TIM1_MMS ((uint8_t) (0x07 << 4))
	TIM1 Master mode selection [2:0] (in _TIM1_CR2) More...

#define	_TIM1_MMS0 ((uint8_t) (0x01 << 4))
	TIM1 Master mode selection [0] (in _TIM1_CR2) More...

#define	_TIM1_MMS1 ((uint8_t) (0x01 << 5))
	TIM1 Master mode selection [1] (in _TIM1_CR2) More...

#define	_TIM1_MMS2 ((uint8_t) (0x01 << 6))
	TIM1 Master mode selection [2] (in _TIM1_CR2) More...

#define	_TIM1_SMS ((uint8_t) (0x07 << 0))
	TIM1 Clock/trigger/slave mode selection [2:0] (in _TIM1_SMCR) More...

#define	_TIM1_SMS0 ((uint8_t) (0x01 << 0))
	TIM1 Clock/trigger/slave mode selection [0] (in _TIM1_SMCR) More...

#define	_TIM1_SMS1 ((uint8_t) (0x01 << 1))
	TIM1 Clock/trigger/slave mode selection [1] (in _TIM1_SMCR) More...

#define	_TIM1_SMS2 ((uint8_t) (0x01 << 2))
	TIM1 Clock/trigger/slave mode selection [2] (in _TIM1_SMCR) More...

#define	_TIM1_TS ((uint8_t) (0x07 << 4))
	TIM1 Trigger selection [2:0] (in _TIM1_SMCR) More...

#define	_TIM1_TS0 ((uint8_t) (0x01 << 4))
	TIM1 Trigger selection [0] (in _TIM1_SMCR) More...

#define	_TIM1_TS1 ((uint8_t) (0x01 << 5))
	TIM1 Trigger selection [1] (in _TIM1_SMCR) More...

#define	_TIM1_TS2 ((uint8_t) (0x01 << 6))
	TIM1 Trigger selection [2] (in _TIM1_SMCR) More...

#define	_TIM1_MSM ((uint8_t) (0x01 << 7))
	TIM1 Master/slave mode [0] (in _TIM1_SMCR) More...

#define	_TIM1_ETF ((uint8_t) (0x0F << 0))
	TIM1 External trigger filter [3:0] (in _TIM1_ETR) More...

#define	_TIM1_ETF0 ((uint8_t) (0x01 << 0))
	TIM1 External trigger filter [0] (in _TIM1_ETR) More...

#define	_TIM1_ETF1 ((uint8_t) (0x01 << 1))
	TIM1 External trigger filter [1] (in _TIM1_ETR) More...

#define	_TIM1_ETF2 ((uint8_t) (0x01 << 2))
	TIM1 External trigger filter [2] (in _TIM1_ETR) More...

#define	_TIM1_ETF3 ((uint8_t) (0x01 << 3))
	TIM1 External trigger filter [3] (in _TIM1_ETR) More...

#define	_TIM1_ETPS ((uint8_t) (0x03 << 4))
	TIM1 External trigger prescaler [1:0] (in _TIM1_ETR) More...

#define	_TIM1_ETPS0 ((uint8_t) (0x01 << 4))
	TIM1 External trigger prescaler [0] (in _TIM1_ETR) More...

#define	_TIM1_ETPS1 ((uint8_t) (0x01 << 5))
	TIM1 External trigger prescaler [1] (in _TIM1_ETR) More...

#define	_TIM1_ECE ((uint8_t) (0x01 << 6))
	TIM1 External clock enable [0] (in _TIM1_ETR) More...

#define	_TIM1_ETP ((uint8_t) (0x01 << 7))
	TIM1 External trigger polarity [0] (in _TIM1_ETR) More...

#define	_TIM1_UIE ((uint8_t) (0x01 << 0))
	TIM1 Update interrupt enable [0] (in _TIM1_IER) More...

#define	_TIM1_CC1IE ((uint8_t) (0x01 << 1))
	TIM1 Capture/compare 1 interrupt enable [0] (in _TIM1_IER) More...

#define	_TIM1_CC2IE ((uint8_t) (0x01 << 2))
	TIM1 Capture/compare 2 interrupt enable [0] (in _TIM1_IER) More...

#define	_TIM1_CC3IE ((uint8_t) (0x01 << 3))
	TIM1 Capture/compare 3 interrupt enable [0] (in _TIM1_IER) More...

#define	_TIM1_CC4IE ((uint8_t) (0x01 << 4))
	TIM1 Capture/compare 4 interrupt enable [0] (in _TIM1_IER) More...

#define	_TIM1_COMIE ((uint8_t) (0x01 << 5))
	TIM1 Commutation interrupt enable [0] (in _TIM1_IER) More...

#define	_TIM1_TIE ((uint8_t) (0x01 << 6))
	TIM1 Trigger interrupt enable [0] (in _TIM1_IER) More...

#define	_TIM1_BIE ((uint8_t) (0x01 << 7))
	TIM1 Break interrupt enable [0] (in _TIM1_IER) More...

#define	_TIM1_UIF ((uint8_t) (0x01 << 0))
	TIM1 Update interrupt flag [0] (in _TIM1_SR1) More...

#define	_TIM1_CC1IF ((uint8_t) (0x01 << 1))
	TIM1 Capture/compare 1 interrupt flag [0] (in _TIM1_SR1) More...

#define	_TIM1_CC2IF ((uint8_t) (0x01 << 2))
	TIM1 Capture/compare 2 interrupt flag [0] (in _TIM1_SR1) More...

#define	_TIM1_CC3IF ((uint8_t) (0x01 << 3))
	TIM1 Capture/compare 3 interrupt flag [0] (in _TIM1_SR1) More...

#define	_TIM1_CC4IF ((uint8_t) (0x01 << 4))
	TIM1 Capture/compare 4 interrupt flag [0] (in _TIM1_SR1) More...

#define	_TIM1_COMIF ((uint8_t) (0x01 << 5))
	TIM1 Commutation interrupt flag [0] (in _TIM1_SR1) More...

#define	_TIM1_TIF ((uint8_t) (0x01 << 6))
	TIM1 Trigger interrupt flag [0] (in _TIM1_SR1) More...

#define	_TIM1_BIF ((uint8_t) (0x01 << 7))
	TIM1 Break interrupt flag [0] (in _TIM1_SR1) More...

#define	_TIM1_CC1OF ((uint8_t) (0x01 << 1))
	TIM1 Capture/compare 1 overcapture flag [0] (in _TIM1_SR2) More...

#define	_TIM1_CC2OF ((uint8_t) (0x01 << 2))
	TIM1 Capture/compare 2 overcapture flag [0] (in _TIM1_SR2) More...

#define	_TIM1_CC3OF ((uint8_t) (0x01 << 3))
	TIM1 Capture/compare 3 overcapture flag [0] (in _TIM1_SR2) More...

#define	_TIM1_CC4OF ((uint8_t) (0x01 << 4))
	TIM1 Capture/compare 4 overcapture flag [0] (in _TIM1_SR2) More...

#define	_TIM1_UG ((uint8_t) (0x01 << 0))
	TIM1 Update generation [0] (in _TIM1_EGR) More...

#define	_TIM1_CC1G ((uint8_t) (0x01 << 1))
	TIM1 Capture/compare 1 generation [0] (in _TIM1_EGR) More...

#define	_TIM1_CC2G ((uint8_t) (0x01 << 2))
	TIM1 Capture/compare 2 generation [0] (in _TIM1_EGR) More...

#define	_TIM1_CC3G ((uint8_t) (0x01 << 3))
	TIM1 Capture/compare 3 generation [0] (in _TIM1_EGR) More...

#define	_TIM1_CC4G ((uint8_t) (0x01 << 4))
	TIM1 Capture/compare 4 generation [0] (in _TIM1_EGR) More...

#define	_TIM1_COMG ((uint8_t) (0x01 << 5))
	TIM1 Capture/compare control update generation [0] (in _TIM1_EGR) More...

#define	_TIM1_TG ((uint8_t) (0x01 << 6))
	TIM1 Trigger generation [0] (in _TIM1_EGR) More...

#define	_TIM1_BG ((uint8_t) (0x01 << 7))
	TIM1 Break generation [0] (in _TIM1_EGR) More...

#define	_TIM1_CC1S ((uint8_t) (0x03 << 0))
	TIM1 Compare 1 selection [1:0] (in _TIM1_CCMR1) More...

#define	_TIM1_CC1S0 ((uint8_t) (0x01 << 0))
	TIM1 Compare 1 selection [0] (in _TIM1_CCMR1) More...

#define	_TIM1_CC1S1 ((uint8_t) (0x01 << 1))
	TIM1 Compare 1 selection [1] (in _TIM1_CCMR1) More...

#define	_TIM1_OC1FE ((uint8_t) (0x01 << 2))
	TIM1 Output compare 1 fast enable [0] (in _TIM1_CCMR1) More...

#define	_TIM1_OC1PE ((uint8_t) (0x01 << 3))
	TIM1 Output compare 1 preload enable [0] (in _TIM1_CCMR1) More...

#define	_TIM1_OC1M ((uint8_t) (0x07 << 4))
	TIM1 Output compare 1 mode [2:0] (in _TIM1_CCMR1) More...

#define	_TIM1_OC1M0 ((uint8_t) (0x01 << 4))
	TIM1 Output compare 1 mode [0] (in _TIM1_CCMR1) More...

#define	_TIM1_OC1M1 ((uint8_t) (0x01 << 5))
	TIM1 Output compare 1 mode [1] (in _TIM1_CCMR1) More...

#define	_TIM1_OC1M2 ((uint8_t) (0x01 << 6))
	TIM1 Output compare 1 mode [2] (in _TIM1_CCMR1) More...

#define	_TIM1_OC1CE ((uint8_t) (0x01 << 7))
	TIM1 Output compare 1 clear enable [0] (in _TIM1_CCMR1) More...

#define	_TIM1_IC1PSC ((uint8_t) (0x03 << 2))
	TIM1 Input capture 1 prescaler [1:0] (in _TIM1_CCMR1) More...

#define	_TIM1_IC1PSC0 ((uint8_t) (0x01 << 2))
	TIM1 Input capture 1 prescaler [0] (in _TIM1_CCMR1) More...

#define	_TIM1_IC1PSC1 ((uint8_t) (0x01 << 3))
	TIM1 Input capture 1 prescaler [1] (in _TIM1_CCMR1) More...

#define	_TIM1_IC1F ((uint8_t) (0x0F << 4))
	TIM1 Output compare 1 mode [3:0] (in _TIM1_CCMR1) More...

#define	_TIM1_IC1F0 ((uint8_t) (0x01 << 4))
	TIM1 Input capture 1 filter [0] (in _TIM1_CCMR1) More...

#define	_TIM1_IC1F1 ((uint8_t) (0x01 << 5))
	TIM1 Input capture 1 filter [1] (in _TIM1_CCMR1) More...

#define	_TIM1_IC1F2 ((uint8_t) (0x01 << 6))
	TIM1 Input capture 1 filter [2] (in _TIM1_CCMR1) More...

#define	_TIM1_IC1F3 ((uint8_t) (0x01 << 7))
	TIM1 Input capture 1 filter [3] (in _TIM1_CCMR1) More...

#define	_TIM1_CC2S ((uint8_t) (0x03 << 0))
	TIM1 Compare 2 selection [1:0] (in _TIM1_CCMR2) More...

#define	_TIM1_CC2S0 ((uint8_t) (0x01 << 0))
	TIM1 Compare 2 selection [0] (in _TIM1_CCMR2) More...

#define	_TIM1_CC2S1 ((uint8_t) (0x01 << 1))
	TIM1 Compare 2 selection [1] (in _TIM1_CCMR2) More...

#define	_TIM1_OC2FE ((uint8_t) (0x01 << 2))
	TIM1 Output compare 2 fast enable [0] (in _TIM1_CCMR2) More...

#define	_TIM1_OC2PE ((uint8_t) (0x01 << 3))
	TIM1 Output compare 2 preload enable [0] (in _TIM1_CCMR2) More...

#define	_TIM1_OC2M ((uint8_t) (0x07 << 4))
	TIM1 Output compare 2 mode [2:0] (in _TIM1_CCMR2) More...

#define	_TIM1_OC2M0 ((uint8_t) (0x01 << 4))
	TIM1 Output compare 2 mode [0] (in _TIM1_CCMR2) More...

#define	_TIM1_OC2M1 ((uint8_t) (0x01 << 5))
	TIM1 Output compare 2 mode [1] (in _TIM1_CCMR2) More...

#define	_TIM1_OC2M2 ((uint8_t) (0x01 << 6))
	TIM1 Output compare 2 mode [2] (in _TIM1_CCMR2) More...

#define	_TIM1_OC2CE ((uint8_t) (0x01 << 7))
	TIM1 Output compare 2 clear enable [0] (in _TIM1_CCMR2) More...

#define	_TIM1_IC2PSC ((uint8_t) (0x03 << 2))
	TIM1 Input capture 2 prescaler [1:0] (in _TIM1_CCMR2) More...

#define	_TIM1_IC2PSC0 ((uint8_t) (0x01 << 2))
	TIM1 Input capture 2 prescaler [0] (in _TIM1_CCMR2) More...

#define	_TIM1_IC2PSC1 ((uint8_t) (0x01 << 3))
	TIM1 Input capture 2 prescaler [1] (in _TIM1_CCMR2) More...

#define	_TIM1_IC2F ((uint8_t) (0x0F << 4))
	TIM1 Output compare 2 mode [3:0] (in _TIM1_CCMR2) More...

#define	_TIM1_IC2F0 ((uint8_t) (0x01 << 4))
	TIM1 Input capture 2 filter [0] (in _TIM1_CCMR2) More...

#define	_TIM1_IC2F1 ((uint8_t) (0x01 << 5))
	TIM1 Input capture 2 filter [1] (in _TIM1_CCMR2) More...

#define	_TIM1_IC2F2 ((uint8_t) (0x01 << 6))
	TIM1 Input capture 2 filter [2] (in _TIM1_CCMR2) More...

#define	_TIM1_IC2F3 ((uint8_t) (0x01 << 7))
	TIM1 Input capture 2 filter [3] (in _TIM1_CCMR2) More...

#define	_TIM1_CC3S ((uint8_t) (0x03 << 0))
	TIM1 Compare 3 selection [1:0] (in _TIM1_CCMR3) More...

#define	_TIM1_CC3S0 ((uint8_t) (0x01 << 0))
	TIM1 Compare 3 selection [0] (in _TIM1_CCMR3) More...

#define	_TIM1_CC3S1 ((uint8_t) (0x01 << 1))
	TIM1 Compare 3 selection [1] (in _TIM1_CCMR3) More...

#define	_TIM1_OC3FE ((uint8_t) (0x01 << 2))
	TIM1 Output compare 3 fast enable [0] (in _TIM1_CCMR3) More...

#define	_TIM1_OC3PE ((uint8_t) (0x01 << 3))
	TIM1 Output compare 3 preload enable [0] (in _TIM1_CCMR3) More...

#define	_TIM1_OC3M ((uint8_t) (0x07 << 4))
	TIM1 Output compare 3 mode [2:0] (in _TIM1_CCMR3) More...

#define	_TIM1_OC3M0 ((uint8_t) (0x01 << 4))
	TIM1 Output compare 3 mode [0] (in _TIM1_CCMR3) More...

#define	_TIM1_OC3M1 ((uint8_t) (0x01 << 5))
	TIM1 Output compare 3 mode [1] (in _TIM1_CCMR3) More...

#define	_TIM1_OC3M2 ((uint8_t) (0x01 << 6))
	TIM1 Output compare 3 mode [2] (in _TIM1_CCMR3) More...

#define	_TIM1_OC3CE ((uint8_t) (0x01 << 7))
	TIM1 Output compare 3 clear enable [0] (in _TIM1_CCMR3) More...

#define	_TIM1_IC3PSC ((uint8_t) (0x03 << 2))
	TIM1 Input capture 3 prescaler [1:0] (in _TIM1_CCMR3) More...

#define	_TIM1_IC3PSC0 ((uint8_t) (0x01 << 2))
	TIM1 Input capture 3 prescaler [0] (in _TIM1_CCMR3) More...

#define	_TIM1_IC3PSC1 ((uint8_t) (0x01 << 3))
	TIM1 Input capture 3 prescaler [1] (in _TIM1_CCMR3) More...

#define	_TIM1_IC3F ((uint8_t) (0x0F << 4))
	TIM1 Output compare 3 mode [3:0] (in _TIM1_CCMR3) More...

#define	_TIM1_IC3F0 ((uint8_t) (0x01 << 4))
	TIM1 Input capture 3 filter [0] (in _TIM1_CCMR3) More...

#define	_TIM1_IC3F1 ((uint8_t) (0x01 << 5))
	TIM1 Input capture 3 filter [1] (in _TIM1_CCMR3) More...

#define	_TIM1_IC3F2 ((uint8_t) (0x01 << 6))
	TIM1 Input capture 3 filter [2] (in _TIM1_CCMR3) More...

#define	_TIM1_IC3F3 ((uint8_t) (0x01 << 7))
	TIM1 Input capture 3 filter [3] (in _TIM1_CCMR3) More...

#define	_TIM1_CC4S ((uint8_t) (0x03 << 0))
	TIM1 Compare 4 selection [1:0] (in _TIM1_CCMR4) More...

#define	_TIM1_CC4S0 ((uint8_t) (0x01 << 0))
	TIM1 Compare 4 selection [0] (in _TIM1_CCMR4) More...

#define	_TIM1_CC4S1 ((uint8_t) (0x01 << 1))
	TIM1 Compare 4 selection [1] (in _TIM1_CCMR4) More...

#define	_TIM1_OC4FE ((uint8_t) (0x01 << 2))
	TIM1 Output compare 4 fast enable [0] (in _TIM1_CCMR4) More...

#define	_TIM1_OC4PE ((uint8_t) (0x01 << 3))
	TIM1 Output compare 4 preload enable [0] (in _TIM1_CCMR4) More...

#define	_TIM1_OC4M ((uint8_t) (0x07 << 4))
	TIM1 Output compare 4 mode [2:0] (in _TIM1_CCMR4) More...

#define	_TIM1_OC4M0 ((uint8_t) (0x01 << 4))
	TIM1 Output compare 4 mode [0] (in _TIM1_CCMR4) More...

#define	_TIM1_OC4M1 ((uint8_t) (0x01 << 5))
	TIM1 Output compare 4 mode [1] (in _TIM1_CCMR4) More...

#define	_TIM1_OC4M2 ((uint8_t) (0x01 << 6))
	TIM1 Output compare 4 mode [2] (in _TIM1_CCMR4) More...

#define	_TIM1_OC4CE ((uint8_t) (0x01 << 7))
	TIM1 Output compare 4 clear enable [0] (in _TIM1_CCMR4) More...

#define	_TIM1_IC4PSC ((uint8_t) (0x03 << 2))
	TIM1 Input capture 4 prescaler [1:0] (in _TIM1_CCMR4) More...

#define	_TIM1_IC4PSC0 ((uint8_t) (0x01 << 2))
	TIM1 Input capture 4 prescaler [0] (in _TIM1_CCMR4) More...

#define	_TIM1_IC4PSC1 ((uint8_t) (0x01 << 3))
	TIM1 Input capture 4 prescaler [1] (in _TIM1_CCMR4) More...

#define	_TIM1_IC4F ((uint8_t) (0x0F << 4))
	TIM1 Output compare 4 mode [3:0] (in _TIM1_CCMR4) More...

#define	_TIM1_IC4F0 ((uint8_t) (0x01 << 4))
	TIM1 Input capture 4 filter [0] (in _TIM1_CCMR4) More...

#define	_TIM1_IC4F1 ((uint8_t) (0x01 << 5))
	TIM1 Input capture 4 filter [1] (in _TIM1_CCMR4) More...

#define	_TIM1_IC4F2 ((uint8_t) (0x01 << 6))
	TIM1 Input capture 4 filter [2] (in _TIM1_CCMR4) More...

#define	_TIM1_IC4F3 ((uint8_t) (0x01 << 7))
	TIM1 Input capture 4 filter [3] (in _TIM1_CCMR4) More...

#define	_TIM1_CC1E ((uint8_t) (0x01 << 0))
	TIM1 Capture/compare 1 output enable [0] (in _TIM1_CCER1) More...

#define	_TIM1_CC1P ((uint8_t) (0x01 << 1))
	TIM1 Capture/compare 1 output polarity [0] (in _TIM1_CCER1) More...

#define	_TIM1_CC1NE ((uint8_t) (0x01 << 2))
	TIM1 Capture/compare 1 complementary output enable [0] (in _TIM1_CCER1) More...

#define	_TIM1_CC1NP ((uint8_t) (0x01 << 3))
	TIM1 Capture/compare 1 complementary output polarity [0] (in _TIM1_CCER1) More...

#define	_TIM1_CC2E ((uint8_t) (0x01 << 4))
	TIM1 Capture/compare 2 output enable [0] (in _TIM1_CCER1) More...

#define	_TIM1_CC2P ((uint8_t) (0x01 << 5))
	TIM1 Capture/compare 2 output polarity [0] (in _TIM1_CCER1) More...

#define	_TIM1_CC2NE ((uint8_t) (0x01 << 6))
	TIM1 Capture/compare 2 complementary output enable [0] (in _TIM1_CCER1) More...

#define	_TIM1_CC2NP ((uint8_t) (0x01 << 7))
	TIM1 Capture/compare 2 complementary output polarity [0] (in _TIM1_CCER1) More...

#define	_TIM1_CC3E ((uint8_t) (0x01 << 0))
	TIM1 Capture/compare 3 output enable [0] (in _TIM1_CCER2) More...

#define	_TIM1_CC3P ((uint8_t) (0x01 << 1))
	TIM1 Capture/compare 3 output polarity [0] (in _TIM1_CCER2) More...

#define	_TIM1_CC3NE ((uint8_t) (0x01 << 2))
	TIM1 Capture/compare 3 complementary output enable [0] (in _TIM1_CCER2) More...

#define	_TIM1_CC3NP ((uint8_t) (0x01 << 3))
	TIM1 Capture/compare 3 complementary output polarity [0] (in _TIM1_CCER2) More...

#define	_TIM1_CC4E ((uint8_t) (0x01 << 4))
	TIM1 Capture/compare 4 output enable [0] (in _TIM1_CCER2) More...

#define	_TIM1_CC4P ((uint8_t) (0x01 << 5))
	TIM1 Capture/compare 4 output polarity [0] (in _TIM1_CCER2) More...

#define	_TIM1_LOCK ((int8_t) (0x03 << 0))
	TIM1 Lock configuration [1:0] (in _TIM1_BKR) More...

#define	_TIM1_LOCK0 ((uint8_t) (0x01 << 0))
	TIM1 Lock configuration [0] (in _TIM1_BKR) More...

#define	_TIM1_LOCK1 ((uint8_t) (0x01 << 1))
	TIM1 Lock configuration [1] (in _TIM1_BKR) More...

#define	_TIM1_OSSI ((uint8_t) (0x01 << 2))
	TIM1 Off state selection for idle mode [0] (in _TIM1_BKR) More...

#define	_TIM1_OSSR ((uint8_t) (0x01 << 3))
	TIM1 Off state selection for Run mode [0] (in _TIM1_BKR) More...

#define	_TIM1_BKE ((uint8_t) (0x01 << 4))
	TIM1 Break enable [0] (in _TIM1_BKR) More...

#define	_TIM1_BKP ((uint8_t) (0x01 << 5))
	TIM1 Break polarity [0] (in _TIM1_BKR) More...

#define	_TIM1_AOE ((uint8_t) (0x01 << 6))
	TIM1 Automatic output enable [0] (in _TIM1_BKR) More...

#define	_TIM1_MOE ((uint8_t) (0x01 << 7))
	TIM1 Main output enable [0] (in _TIM1_BKR) More...

#define	_TIM1_OIS1 ((uint8_t) (0x01 << 0))
	TIM1 Output idle state 1 (OC1 output) [0] (in _TIM1_OISR) More...

#define	_TIM1_OIS1N ((uint8_t) (0x01 << 1))
	TIM1 Output idle state 1 (OC1N output) [0] (in _TIM1_OISR) More...

#define	_TIM1_OIS2 ((uint8_t) (0x01 << 2))
	TIM1 Output idle state 2 (OC2 output) [0] (in _TIM1_OISR) More...

#define	_TIM1_OIS2N ((uint8_t) (0x01 << 3))
	TIM1 Output idle state 2 (OC2N output) [0] (in _TIM1_OISR) More...

#define	_TIM1_OIS3 ((uint8_t) (0x01 << 4))
	TIM1 Output idle state 3 (OC3 output) [0] (in _TIM1_OISR) More...

#define	_TIM1_OIS3N ((uint8_t) (0x01 << 5))
	TIM1 Output idle state 3 (OC3N output) [0] (in _TIM1_OISR) More...

#define	_TIM1_OIS4 ((uint8_t) (0x01 << 6))
	TIM1 Output idle state 4 (OC4 output) [0] (in _TIM1_OISR) More...

#define	_TIM2 _SFR(TIM2_t, TIM2_AddressBase)
	TIM2 struct/bit access. More...

#define	_TIM2_CR1 _SFR(uint8_t, TIM2_AddressBase+0x00)
	TIM2 control register 1. More...

#define	_TIM2_IER _SFR(uint8_t, TIM2_AddressBase+0x01)
	TIM2 interrupt enable register. More...

#define	_TIM2_SR1 _SFR(uint8_t, TIM2_AddressBase+0x02)
	TIM2 status register 1. More...

#define	_TIM2_SR2 _SFR(uint8_t, TIM2_AddressBase+0x03)
	TIM2 status register 2. More...

#define	_TIM2_EGR _SFR(uint8_t, TIM2_AddressBase+0x04)
	TIM2 Event generation register. More...

#define	_TIM2_CCMR1 _SFR(uint8_t, TIM2_AddressBase+0x05)
	TIM2 Capture/compare mode register 1. More...

#define	_TIM2_CCMR2 _SFR(uint8_t, TIM2_AddressBase+0x06)
	TIM2 Capture/compare mode register 2. More...

#define	_TIM2_CCMR3 _SFR(uint8_t, TIM2_AddressBase+0x07)
	TIM2 Capture/compare mode register 3. More...

#define	_TIM2_CCER1 _SFR(uint8_t, TIM2_AddressBase+0x08)
	TIM2 Capture/compare enable register 1. More...

#define	_TIM2_CCER2 _SFR(uint8_t, TIM2_AddressBase+0x09)
	TIM2 Capture/compare enable register 2. More...

#define	_TIM2_CNTRH _SFR(uint8_t, TIM2_AddressBase+0x0A)
	TIM2 counter register high byte. More...

#define	_TIM2_CNTRL _SFR(uint8_t, TIM2_AddressBase+0x0B)
	TIM2 counter register low byte. More...

#define	_TIM2_PSCR _SFR(uint8_t, TIM2_AddressBase+0x0C)
	TIM2 clock prescaler register. More...

#define	_TIM2_ARRH _SFR(uint8_t, TIM2_AddressBase+0x0D)
	TIM2 auto-reload register high byte. More...

#define	_TIM2_ARRL _SFR(uint8_t, TIM2_AddressBase+0x0E)
	TIM2 auto-reload register low byte. More...

#define	_TIM2_CCR1H _SFR(uint8_t, TIM2_AddressBase+0x0F)
	TIM2 16-bit capture/compare value 1 high byte. More...

#define	_TIM2_CCR1L _SFR(uint8_t, TIM2_AddressBase+0x10)
	TIM2 16-bit capture/compare value 1 low byte. More...

#define	_TIM2_CCR2H _SFR(uint8_t, TIM2_AddressBase+0x11)
	TIM2 16-bit capture/compare value 2 high byte. More...

#define	_TIM2_CCR2L _SFR(uint8_t, TIM2_AddressBase+0x12)
	TIM2 16-bit capture/compare value 2 low byte. More...

#define	_TIM2_CCR3H _SFR(uint8_t, TIM2_AddressBase+0x13)
	TIM2 16-bit capture/compare value 3 high byte. More...

#define	_TIM2_CCR3L _SFR(uint8_t, TIM2_AddressBase+0x14)
	TIM2 16-bit capture/compare value 3 low byte. More...

#define	_TIM2_CR1_RESET_VALUE ((uint8_t) 0x00)
	TIM2 control register 1 reset value. More...

#define	_TIM2_IER_RESET_VALUE ((uint8_t) 0x00)
	TIM2 interrupt enable register reset value. More...

#define	_TIM2_SR1_RESET_VALUE ((uint8_t) 0x00)
	TIM2 status register 1 reset value. More...

#define	_TIM2_SR2_RESET_VALUE ((uint8_t) 0x00)
	TIM2 status register 2 reset value. More...

#define	_TIM2_EGR_RESET_VALUE ((uint8_t) 0x00)
	TIM2 Event generation register reset value. More...

#define	_TIM2_CCMR1_RESET_VALUE ((uint8_t) 0x00)
	TIM2 Capture/compare mode register 1 reset value. More...

#define	_TIM2_CCMR2_RESET_VALUE ((uint8_t) 0x00)
	TIM2 Capture/compare mode register 2 reset value. More...

#define	_TIM2_CCMR3_RESET_VALUE ((uint8_t) 0x00)
	TIM2 Capture/compare mode register 3 reset value. More...

#define	_TIM2_CCER1_RESET_VALUE ((uint8_t) 0x00)
	TIM2 Capture/compare enable register 1 reset value. More...

#define	_TIM2_CCER2_RESET_VALUE ((uint8_t) 0x00)
	TIM2 Capture/compare enable register 2 reset value. More...

#define	_TIM2_CNTRH_RESET_VALUE ((uint8_t) 0x00)
	TIM2 counter register high byte reset value. More...

#define	_TIM2_CNTRL_RESET_VALUE ((uint8_t) 0x00)
	TIM2 counter register low byte reset value. More...

#define	_TIM2_PSCR_RESET_VALUE ((uint8_t) 0x00)
	TIM2 clock prescaler register reset value. More...

#define	_TIM2_ARRH_RESET_VALUE ((uint8_t) 0xFF)
	TIM2 auto-reload register high byte reset value. More...

#define	_TIM2_ARRL_RESET_VALUE ((uint8_t) 0xFF)
	TIM2 auto-reload register low byte reset value. More...

#define	_TIM2_CCR1H_RESET_VALUE ((uint8_t) 0x00)
	TIM2 16-bit capture/compare value 1 high byte reset value. More...

#define	_TIM2_CCR1L_RESET_VALUE ((uint8_t) 0x00)
	TIM2 16-bit capture/compare value 1 low byte reset value. More...

#define	_TIM2_CCR2H_RESET_VALUE ((uint8_t) 0x00)
	TIM2 16-bit capture/compare value 2 high byte reset value. More...

#define	_TIM2_CCR2L_RESET_VALUE ((uint8_t) 0x00)
	TIM2 16-bit capture/compare value 2 low byte reset value. More...

#define	_TIM2_CCR3H_RESET_VALUE ((uint8_t) 0x00)
	TIM2 16-bit capture/compare value 3 high byte reset value. More...

#define	_TIM2_CCR3L_RESET_VALUE ((uint8_t) 0x00)
	TIM2 16-bit capture/compare value 3 low byte reset value. More...

#define	_TIM2_CEN ((uint8_t) (0x01 << 0))
	TIM2 Counter enable [0] (in _TIM2_CR1) More...

#define	_TIM2_UDIS ((uint8_t) (0x01 << 1))
	TIM2 Update disable [0] (in _TIM2_CR1) More...

#define	_TIM2_URS ((uint8_t) (0x01 << 2))
	TIM2 Update request source [0] (in _TIM2_CR1) More...

#define	_TIM2_OPM ((uint8_t) (0x01 << 3))
	TIM2 One-pulse mode [0] (in _TIM2_CR1) More...

#define	_TIM2_ARPE ((uint8_t) (0x01 << 7))
	TIM2 Auto-reload preload enable [0] (in _TIM2_CR1) More...

#define	_TIM2_UIE ((uint8_t) (0x01 << 0))
	TIM2 Update interrupt enable [0] (in _TIM2_IER) More...

#define	_TIM2_CC1IE ((uint8_t) (0x01 << 1))
	TIM2 Capture/compare 1 interrupt enable [0] (in _TIM2_IER) More...

#define	_TIM2_CC2IE ((uint8_t) (0x01 << 2))
	TIM2 Capture/compare 2 interrupt enable [0] (in _TIM2_IER) More...

#define	_TIM2_CC3IE ((uint8_t) (0x01 << 3))
	TIM2 Capture/compare 3 interrupt enable [0] (in _TIM2_IER) More...

#define	_TIM2_UIF ((uint8_t) (0x01 << 0))
	TIM2 Update interrupt flag [0] (in _TIM2_SR1) More...

#define	_TIM2_CC1IF ((uint8_t) (0x01 << 1))
	TIM2 Capture/compare 1 interrupt flag [0] (in _TIM2_SR1) More...

#define	_TIM2_CC2IF ((uint8_t) (0x01 << 2))
	TIM2 Capture/compare 2 interrupt flag [0] (in _TIM2_SR1) More...

#define	_TIM2_CC3IF ((uint8_t) (0x01 << 3))
	TIM2 Capture/compare 3 interrupt flag [0] (in _TIM2_SR1) More...

#define	_TIM2_CC1OF ((uint8_t) (0x01 << 1))
	TIM2 Capture/compare 1 overcapture flag [0] (in _TIM2_SR2) More...

#define	_TIM2_CC2OF ((uint8_t) (0x01 << 2))
	TIM2 Capture/compare 2 overcapture flag [0] (in _TIM2_SR2) More...

#define	_TIM2_CC3OF ((uint8_t) (0x01 << 3))
	TIM2 Capture/compare 3 overcapture flag [0] (in _TIM2_SR2) More...

#define	_TIM2_UG ((uint8_t) (0x01 << 0))
	TIM2 Update generation [0] (in _TIM2_EGR) More...

#define	_TIM2_CC1G ((uint8_t) (0x01 << 1))
	TIM2 Capture/compare 1 generation [0] (in _TIM2_EGR) More...

#define	_TIM2_CC2G ((uint8_t) (0x01 << 2))
	TIM2 Capture/compare 2 generation [0] (in _TIM2_EGR) More...

#define	_TIM2_CC3G ((uint8_t) (0x01 << 3))
	TIM2 Capture/compare 3 generation [0] (in _TIM2_EGR) More...

#define	_TIM2_CC1S ((uint8_t) (0x03 << 0))
	TIM2 Compare 1 selection [1:0] (in _TIM2_CCMR1) More...

#define	_TIM2_CC1S0 ((uint8_t) (0x01 << 0))
	TIM2 Compare 1 selection [0] (in _TIM2_CCMR1) More...

#define	_TIM2_CC1S1 ((uint8_t) (0x01 << 1))
	TIM2 Compare 1 selection [1] (in _TIM2_CCMR1) More...

#define	_TIM2_OC1PE ((uint8_t) (0x01 << 3))
	TIM2 Output compare 1 preload enable [0] (in _TIM2_CCMR1) More...

#define	_TIM2_OC1M ((uint8_t) (0x07 << 4))
	TIM2 Output compare 1 mode [2:0] (in _TIM2_CCMR1) More...

#define	_TIM2_OC1M0 ((uint8_t) (0x01 << 4))
	TIM2 Output compare 1 mode [0] (in _TIM2_CCMR1) More...

#define	_TIM2_OC1M1 ((uint8_t) (0x01 << 5))
	TIM2 Output compare 1 mode [1] (in _TIM2_CCMR1) More...

#define	_TIM2_OC1M2 ((uint8_t) (0x01 << 6))
	TIM2 Output compare 1 mode [2] (in _TIM2_CCMR1) More...

#define	_TIM2_IC1PSC ((uint8_t) (0x03 << 2))
	TIM2 Input capture 1 prescaler [1:0] (in _TIM2_CCMR1) More...

#define	_TIM2_IC1PSC0 ((uint8_t) (0x01 << 2))
	TIM2 Input capture 1 prescaler [0] (in _TIM2_CCMR1) More...

#define	_TIM2_IC1PSC1 ((uint8_t) (0x01 << 3))
	TIM2 Input capture 1 prescaler [1] (in _TIM2_CCMR1) More...

#define	_TIM2_IC1F ((uint8_t) (0x0F << 4))
	TIM2 Output compare 1 mode [3:0] (in _TIM2_CCMR1) More...

#define	_TIM2_IC1F0 ((uint8_t) (0x01 << 4))
	TIM2 Output compare 1 mode [0] (in _TIM2_CCMR1) More...

#define	_TIM2_IC1F1 ((uint8_t) (0x01 << 5))
	TIM2 Output compare 1 mode [1] (in _TIM2_CCMR1) More...

#define	_TIM2_IC1F2 ((uint8_t) (0x01 << 6))
	TIM2 Output compare 1 mode [2] (in _TIM2_CCMR1) More...

#define	_TIM2_IC1F3 ((uint8_t) (0x01 << 7))
	TIM2 Output compare 1 mode [3] (in _TIM2_CCMR1) More...

#define	_TIM2_CC2S ((uint8_t) (0x03 << 0))
	TIM2 Compare 2 selection [1:0] (in _TIM2_CCMR2) More...

#define	_TIM2_CC2S0 ((uint8_t) (0x01 << 0))
	TIM2 Compare 2 selection [0] (in _TIM2_CCMR2) More...

#define	_TIM2_CC2S1 ((uint8_t) (0x01 << 1))
	TIM2 Compare 2 selection [1] (in _TIM2_CCMR2) More...

#define	_TIM2_OC2PE ((uint8_t) (0x01 << 3))
	TIM2 Output compare 2 preload enable [0] (in _TIM2_CCMR2) More...

#define	_TIM2_OC2M ((uint8_t) (0x07 << 4))
	TIM2 Output compare 2 mode [2:0] (in _TIM2_CCMR2) More...

#define	_TIM2_OC2M0 ((uint8_t) (0x01 << 4))
	TIM2 Output compare 2 mode [0] (in _TIM2_CCMR2) More...

#define	_TIM2_OC2M1 ((uint8_t) (0x01 << 5))
	TIM2 Output compare 2 mode [1] (in _TIM2_CCMR2) More...

#define	_TIM2_OC2M2 ((uint8_t) (0x01 << 6))
	TIM2 Output compare 2 mode [2] (in _TIM2_CCMR2) More...

#define	_TIM2_IC2PSC ((uint8_t) (0x03 << 2))
	TIM2 Input capture 2 prescaler [1:0] (in _TIM2_CCMR2) More...

#define	_TIM2_IC2PSC0 ((uint8_t) (0x01 << 2))
	TIM2 Input capture 2 prescaler [0] (in _TIM2_CCMR2) More...

#define	_TIM2_IC2PSC1 ((uint8_t) (0x01 << 3))
	TIM2 Input capture 2 prescaler [1] (in _TIM2_CCMR2) More...

#define	_TIM2_IC2F ((uint8_t) (0x0F << 4))
	TIM2 Output compare 2 mode [3:0] (in _TIM2_CCMR2) More...

#define	_TIM2_IC2F0 ((uint8_t) (0x01 << 4))
	TIM2 Output compare 2 mode [0] (in _TIM2_CCMR2) More...

#define	_TIM2_IC2F1 ((uint8_t) (0x01 << 5))
	TIM2 Output compare 2 mode [1] (in _TIM2_CCMR2) More...

#define	_TIM2_IC2F2 ((uint8_t) (0x01 << 6))
	TIM2 Output compare 2 mode [2] (in _TIM2_CCMR2) More...

#define	_TIM2_IC2F3 ((uint8_t) (0x01 << 7))
	TIM2 Output compare 2 mode [3] (in _TIM2_CCMR2) More...

#define	_TIM2_CC3S ((uint8_t) (0x03 << 0))
	TIM2 Compare 3 selection [1:0] (in _TIM2_CCMR3) More...

#define	_TIM2_CC3S0 ((uint8_t) (0x01 << 0))
	TIM2 Compare 3 selection [0] (in _TIM2_CCMR3) More...

#define	_TIM2_CC3S1 ((uint8_t) (0x01 << 1))
	TIM2 Compare 3 selection [1] (in _TIM2_CCMR3) More...

#define	_TIM2_OC3PE ((uint8_t) (0x01 << 3))
	TIM2 Output compare 3 preload enable [0] (in _TIM2_CCMR3) More...

#define	_TIM2_OC3M ((uint8_t) (0x07 << 4))
	TIM2 Output compare 3 mode [2:0] (in _TIM2_CCMR3) More...

#define	_TIM2_OC3M0 ((uint8_t) (0x01 << 4))
	TIM2 Output compare 3 mode [0] (in _TIM2_CCMR3) More...

#define	_TIM2_OC3M1 ((uint8_t) (0x01 << 5))
	TIM2 Output compare 3 mode [1] (in _TIM2_CCMR3) More...

#define	_TIM2_OC3M2 ((uint8_t) (0x01 << 6))
	TIM2 Output compare 3 mode [2] (in _TIM2_CCMR3) More...

#define	_TIM2_IC3PSC ((uint8_t) (0x03 << 2))
	TIM2 Input capture 3 prescaler [1:0] (in _TIM2_CCMR3) More...

#define	_TIM2_IC3PSC0 ((uint8_t) (0x01 << 2))
	TIM2 Input capture 3 prescaler [0] (in _TIM2_CCMR3) More...

#define	_TIM2_IC3PSC1 ((uint8_t) (0x01 << 3))
	TIM2 Input capture 3 prescaler [1] (in _TIM2_CCMR3) More...

#define	_TIM2_IC3F ((uint8_t) (0x0F << 4))
	TIM2 Output compare 3 mode [3:0] (in _TIM2_CCMR3) More...

#define	_TIM2_IC3F0 ((uint8_t) (0x01 << 4))
	TIM2 Output compare 3 mode [0] (in _TIM2_CCMR3) More...

#define	_TIM2_IC3F1 ((uint8_t) (0x01 << 5))
	TIM2 Output compare 3 mode [1] (in _TIM2_CCMR3) More...

#define	_TIM2_IC3F2 ((uint8_t) (0x01 << 6))
	TIM2 Output compare 3 mode [2] (in _TIM2_CCMR3) More...

#define	_TIM2_IC3F3 ((uint8_t) (0x01 << 7))
	TIM2 Output compare 3 mode [3] (in _TIM2_CCMR3) More...

#define	_TIM2_CC1E ((uint8_t) (0x01 << 0))
	TIM2 Capture/compare 1 output enable [0] (in _TIM2_CCER1) More...

#define	_TIM2_CC1P ((uint8_t) (0x01 << 1))
	TIM2 Capture/compare 1 output polarity [0] (in _TIM2_CCER1) More...

#define	_TIM2_CC2E ((uint8_t) (0x01 << 4))
	TIM2 Capture/compare 2 output enable [0] (in _TIM2_CCER1) More...

#define	_TIM2_CC2P ((uint8_t) (0x01 << 5))
	TIM2 Capture/compare 2 output polarity [0] (in _TIM2_CCER1) More...

#define	_TIM2_CC3E ((uint8_t) (0x01 << 0))
	TIM2 Capture/compare 3 output enable [0] (in _TIM2_CCER2) More...

#define	_TIM2_CC3P ((uint8_t) (0x01 << 1))
	TIM2 Capture/compare 3 output polarity [0] (in _TIM2_CCER2) More...

#define	_TIM2_PSC ((uint8_t) (0x0F << 0))
	TIM2 prescaler [3:0] (in _TIM2_PSCR) More...

#define	_TIM2_PSC0 ((uint8_t) (0x01 << 0))
	TIM2 prescaler [0] (in _TIM2_PSCR) More...

#define	_TIM2_PSC1 ((uint8_t) (0x01 << 1))
	TIM2 prescaler [1] (in _TIM2_PSCR) More...

#define	_TIM2_PSC2 ((uint8_t) (0x01 << 2))
	TIM2 prescaler [2] (in _TIM2_PSCR) More...

#define	_TIM2_PSC3 ((uint8_t) (0x01 << 3))
	TIM2 prescaler [3] (in _TIM2_PSCR) More...

#define	_TIM3 _SFR(TIM3_t, TIM3_AddressBase)
	TIM3 struct/bit access. More...

#define	_TIM3_CR1 _SFR(uint8_t, TIM3_AddressBase+0x00)
	TIM3 control register 1. More...

#define	_TIM3_IER _SFR(uint8_t, TIM3_AddressBase+0x01)
	TIM3 interrupt enable register. More...

#define	_TIM3_SR1 _SFR(uint8_t, TIM3_AddressBase+0x02)
	TIM3 status register 1. More...

#define	_TIM3_SR2 _SFR(uint8_t, TIM3_AddressBase+0x03)
	TIM3 status register 2. More...

#define	_TIM3_EGR _SFR(uint8_t, TIM3_AddressBase+0x04)
	TIM3 Event generation register. More...

#define	_TIM3_CCMR1 _SFR(uint8_t, TIM3_AddressBase+0x05)
	TIM3 Capture/compare mode register 1. More...

#define	_TIM3_CCMR2 _SFR(uint8_t, TIM3_AddressBase+0x06)
	TIM3 Capture/compare mode register 2. More...

#define	_TIM3_CCER1 _SFR(uint8_t, TIM3_AddressBase+0x08)
	TIM3 Capture/compare enable register 1. More...

#define	_TIM3_CNTRH _SFR(uint8_t, TIM3_AddressBase+0x0A)
	TIM3 counter register high byte. More...

#define	_TIM3_CNTRL _SFR(uint8_t, TIM3_AddressBase+0x0B)
	TIM3 counter register low byte. More...

#define	_TIM3_PSCR _SFR(uint8_t, TIM3_AddressBase+0x0C)
	TIM3 clock prescaler register. More...

#define	_TIM3_ARRH _SFR(uint8_t, TIM3_AddressBase+0x0D)
	TIM3 auto-reload register high byte. More...

#define	_TIM3_ARRL _SFR(uint8_t, TIM3_AddressBase+0x0E)
	TIM3 auto-reload register low byte. More...

#define	_TIM3_CCR1H _SFR(uint8_t, TIM3_AddressBase+0x0F)
	TIM3 16-bit capture/compare value 1 high byte. More...

#define	_TIM3_CCR1L _SFR(uint8_t, TIM3_AddressBase+0x10)
	TIM3 16-bit capture/compare value 1 low byte. More...

#define	_TIM3_CCR2H _SFR(uint8_t, TIM3_AddressBase+0x11)
	TIM3 16-bit capture/compare value 2 high byte. More...

#define	_TIM3_CCR2L _SFR(uint8_t, TIM3_AddressBase+0x12)
	TIM3 16-bit capture/compare value 2 low byte. More...

#define	_TIM3_CR1_RESET_VALUE ((uint8_t) 0x00)
	TIM3 control register 1 reset value. More...

#define	_TIM3_IER_RESET_VALUE ((uint8_t) 0x00)
	TIM3 interrupt enable register reset value. More...

#define	_TIM3_SR1_RESET_VALUE ((uint8_t) 0x00)
	TIM3 status register 1 reset value. More...

#define	_TIM3_SR2_RESET_VALUE ((uint8_t) 0x00)
	TIM3 status register 2 reset value. More...

#define	_TIM3_EGR_RESET_VALUE ((uint8_t) 0x00)
	TIM3 Event generation register reset value. More...

#define	_TIM3_CCMR1_RESET_VALUE ((uint8_t) 0x00)
	TIM3 Capture/compare mode register 1 reset value. More...

#define	_TIM3_CCMR2_RESET_VALUE ((uint8_t) 0x00)
	TIM3 Capture/compare mode register 2 reset value. More...

#define	_TIM3_CCER1_RESET_VALUE ((uint8_t) 0x00)
	TIM3 Capture/compare enable register 1 reset value. More...

#define	_TIM3_CNTRH_RESET_VALUE ((uint8_t) 0x00)
	TIM3 counter register high byte reset value. More...

#define	_TIM3_CNTRL_RESET_VALUE ((uint8_t) 0x00)
	TIM3 counter register low byte reset value. More...

#define	_TIM3_PSCR_RESET_VALUE ((uint8_t) 0x00)
	TIM3 clock prescaler register reset value. More...

#define	_TIM3_ARRH_RESET_VALUE ((uint8_t) 0xFF)
	TIM3 auto-reload register high byte reset value. More...

#define	_TIM3_ARRL_RESET_VALUE ((uint8_t) 0xFF)
	TIM3 auto-reload register low byte reset value. More...

#define	_TIM3_CCR1H_RESET_VALUE ((uint8_t) 0x00)
	TIM3 16-bit capture/compare value 1 high byte reset value. More...

#define	_TIM3_CCR1L_RESET_VALUE ((uint8_t) 0x00)
	TIM3 16-bit capture/compare value 1 low byte reset value. More...

#define	_TIM3_CCR2H_RESET_VALUE ((uint8_t) 0x00)
	TIM3 16-bit capture/compare value 2 high byte reset value. More...

#define	_TIM3_CCR2L_RESET_VALUE ((uint8_t) 0x00)
	TIM3 16-bit capture/compare value 2 low byte reset value. More...

#define	_TIM3_CEN ((uint8_t) (0x01 << 0))
	TIM3 Counter enable [0] (in _TIM3_CR1) More...

#define	_TIM3_UDIS ((uint8_t) (0x01 << 1))
	TIM3 Update disable [0] (in _TIM3_CR1) More...

#define	_TIM3_URS ((uint8_t) (0x01 << 2))
	TIM3 Update request source [0] (in _TIM3_CR1) More...

#define	_TIM3_OPM ((uint8_t) (0x01 << 3))
	TIM3 One-pulse mode [0] (in _TIM3_CR1) More...

#define	_TIM3_ARPE ((uint8_t) (0x01 << 7))
	TIM3 Auto-reload preload enable [0] (in _TIM3_CR1) More...

#define	_TIM3_UIE ((uint8_t) (0x01 << 0))
	TIM3 Update interrupt enable [0] (in _TIM3_IER) More...

#define	_TIM3_CC1IE ((uint8_t) (0x01 << 1))
	TIM3 Capture/compare 1 interrupt enable [0] (in _TIM3_IER) More...

#define	_TIM3_CC2IE ((uint8_t) (0x01 << 2))
	TIM3 Capture/compare 2 interrupt enable [0] (in _TIM3_IER) More...

#define	_TIM3_UIF ((uint8_t) (0x01 << 0))
	TIM3 Update interrupt flag [0] (in _TIM3_SR1) More...

#define	_TIM3_CC1IF ((uint8_t) (0x01 << 1))
	TIM3 Capture/compare 1 interrupt flag [0] (in _TIM3_SR1) More...

#define	_TIM3_CC2IF ((uint8_t) (0x01 << 2))
	TIM3 Capture/compare 2 interrupt flag [0] (in _TIM3_SR1) More...

#define	_TIM3_CC1OF ((uint8_t) (0x01 << 1))
	TIM3 Capture/compare 1 overcapture flag [0] (in _TIM3_SR2) More...

#define	_TIM3_CC2OF ((uint8_t) (0x01 << 2))
	TIM3 Capture/compare 2 overcapture flag [0] (in _TIM3_SR2) More...

#define	_TIM3_UG ((uint8_t) (0x01 << 0))
	TIM3 Update generation [0] (in _TIM3_EGR) More...

#define	_TIM3_CC1G ((uint8_t) (0x01 << 1))
	TIM3 Capture/compare 1 generation [0] (in _TIM3_EGR) More...

#define	_TIM3_CC2G ((uint8_t) (0x01 << 2))
	TIM3 Capture/compare 2 generation [0] (in _TIM3_EGR) More...

#define	_TIM3_CC1S ((uint8_t) (0x03 << 0))
	TIM3 Compare 1 selection [1:0] (in _TIM3_CCMR1) More...

#define	_TIM3_CC1S0 ((uint8_t) (0x01 << 0))
	TIM3 Compare 1 selection [0] (in _TIM3_CCMR1) More...

#define	_TIM3_CC1S1 ((uint8_t) (0x01 << 1))
	TIM3 Compare 1 selection [1] (in _TIM3_CCMR1) More...

#define	_TIM3_OC1PE ((uint8_t) (0x01 << 3))
	TIM3 Output compare 1 preload enable [0] (in _TIM3_CCMR1) More...

#define	_TIM3_OC1M ((uint8_t) (0x07 << 4))
	TIM3 Output compare 1 mode [2:0] (in _TIM3_CCMR1) More...

#define	_TIM3_OC1M0 ((uint8_t) (0x01 << 4))
	TIM3 Output compare 1 mode [0] (in _TIM3_CCMR1) More...

#define	_TIM3_OC1M1 ((uint8_t) (0x01 << 5))
	TIM3 Output compare 1 mode [1] (in _TIM3_CCMR1) More...

#define	_TIM3_OC1M2 ((uint8_t) (0x01 << 6))
	TIM3 Output compare 1 mode [2] (in _TIM3_CCMR1) More...

#define	_TIM3_IC1PSC ((uint8_t) (0x03 << 2))
	TIM3 Input capture 1 prescaler [1:0] (in _TIM3_CCMR1) More...

#define	_TIM3_IC1PSC0 ((uint8_t) (0x01 << 2))
	TIM3 Input capture 1 prescaler [0] (in _TIM3_CCMR1) More...

#define	_TIM3_IC1PSC1 ((uint8_t) (0x01 << 3))
	TIM3 Input capture 1 prescaler [1] (in _TIM3_CCMR1) More...

#define	_TIM3_IC1F ((uint8_t) (0x0F << 4))
	TIM3 Output compare 1 mode [3:0] (in _TIM3_CCMR1) More...

#define	_TIM3_IC1F0 ((uint8_t) (0x01 << 4))
	TIM3 Output compare 1 mode [0] (in _TIM3_CCMR1) More...

#define	_TIM3_IC1F1 ((uint8_t) (0x01 << 5))
	TIM3 Output compare 1 mode [1] (in _TIM3_CCMR1) More...

#define	_TIM3_IC1F2 ((uint8_t) (0x01 << 6))
	TIM3 Output compare 1 mode [2] (in _TIM3_CCMR1) More...

#define	_TIM3_IC1F3 ((uint8_t) (0x01 << 7))
	TIM3 Output compare 1 mode [3] (in _TIM3_CCMR1) More...

#define	_TIM3_CC2S ((uint8_t) (0x03 << 0))
	TIM3 Compare 2 selection [1:0] (in _TIM3_CCMR2) More...

#define	_TIM3_CC2S0 ((uint8_t) (0x01 << 0))
	TIM3 Compare 2 selection [0] (in _TIM3_CCMR2) More...

#define	_TIM3_CC2S1 ((uint8_t) (0x01 << 1))
	TIM3 Compare 2 selection [1] (in _TIM3_CCMR2) More...

#define	_TIM3_OC2PE ((uint8_t) (0x01 << 3))
	TIM3 Output compare 2 preload enable [0] (in _TIM3_CCMR2) More...

#define	_TIM3_OC2M ((uint8_t) (0x07 << 4))
	TIM3 Output compare 2 mode [2:0] (in _TIM3_CCMR2) More...

#define	_TIM3_OC2M0 ((uint8_t) (0x01 << 4))
	TIM3 Output compare 2 mode [0] (in _TIM3_CCMR2) More...

#define	_TIM3_OC2M1 ((uint8_t) (0x01 << 5))
	TIM3 Output compare 2 mode [1] (in _TIM3_CCMR2) More...

#define	_TIM3_OC2M2 ((uint8_t) (0x01 << 6))
	TIM3 Output compare 2 mode [2] (in _TIM3_CCMR2) More...

#define	_TIM3_IC2PSC ((uint8_t) (0x03 << 2))
	TIM3 Input capture 2 prescaler [1:0] (in _TIM3_CCMR2) More...

#define	_TIM3_IC2PSC0 ((uint8_t) (0x01 << 2))
	TIM3 Input capture 2 prescaler [0] (in _TIM3_CCMR2) More...

#define	_TIM3_IC2PSC1 ((uint8_t) (0x01 << 3))
	TIM3 Input capture 2 prescaler [1] (in _TIM3_CCMR2) More...

#define	_TIM3_IC2F ((uint8_t) (0x0F << 4))
	TIM3 Output compare 2 mode [3:0] (in _TIM3_CCMR2) More...

#define	_TIM3_IC2F0 ((uint8_t) (0x01 << 4))
	TIM3 Output compare 2 mode [0] (in _TIM3_CCMR2) More...

#define	_TIM3_IC2F1 ((uint8_t) (0x01 << 5))
	TIM3 Output compare 2 mode [1] (in _TIM3_CCMR2) More...

#define	_TIM3_IC2F2 ((uint8_t) (0x01 << 6))
	TIM3 Output compare 2 mode [2] (in _TIM3_CCMR2) More...

#define	_TIM3_IC2F3 ((uint8_t) (0x01 << 7))
	TIM3 Output compare 2 mode [3] (in _TIM3_CCMR2) More...

#define	_TIM3_CC1E ((uint8_t) (0x01 << 0))
	TIM3 Capture/compare 1 output enable [0] (in _TIM3_CCER1) More...

#define	_TIM3_CC1P ((uint8_t) (0x01 << 1))
	TIM3 Capture/compare 1 output polarity [0] (in _TIM3_CCER1) More...

#define	_TIM3_CC2E ((uint8_t) (0x01 << 4))
	TIM3 Capture/compare 2 output enable [0] (in _TIM3_CCER1) More...

#define	_TIM3_CC2P ((uint8_t) (0x01 << 5))
	TIM3 Capture/compare 2 output polarity [0] (in _TIM3_CCER1) More...

#define	_TIM3_PSC ((uint8_t) (0x0F << 0))
	TIM3 clock prescaler [3:0] (in _TIM3_PSCR) More...

#define	_TIM3_PSC0 ((uint8_t) (0x01 << 0))
	TIM3 clock prescaler [0] (in _TIM3_PSCR) More...

#define	_TIM3_PSC1 ((uint8_t) (0x01 << 1))
	TIM3 clock prescaler [1] (in _TIM3_PSCR) More...

#define	_TIM3_PSC2 ((uint8_t) (0x01 << 2))
	TIM3 clock prescaler [2] (in _TIM3_PSCR) More...

#define	_TIM3_PSC3 ((uint8_t) (0x01 << 3))
	TIM3 clock prescaler [3] (in _TIM3_PSCR) More...

#define	_TIM4 _SFR(TIM4_t, TIM4_AddressBase)
	TIM4 struct/bit access. More...

#define	_TIM4_CR _SFR(uint8_t, TIM4_AddressBase+0x00)
	TIM4 control register. More...

#define	_TIM4_IER _SFR(uint8_t, TIM4_AddressBase+0x01)
	TIM4 interrupt enable register. More...

#define	_TIM4_SR _SFR(uint8_t, TIM4_AddressBase+0x02)
	TIM4 status register. More...

#define	_TIM4_EGR _SFR(uint8_t, TIM4_AddressBase+0x03)
	TIM4 event generation register. More...

#define	_TIM4_CNTR _SFR(uint8_t, TIM4_AddressBase+0x04)
	TIM4 counter register. More...

#define	_TIM4_PSCR _SFR(uint8_t, TIM4_AddressBase+0x05)
	TIM4 clock prescaler register. More...

#define	_TIM4_ARR _SFR(uint8_t, TIM4_AddressBase+0x06)
	TIM4 auto-reload register. More...

#define	_TIM4_CR_RESET_VALUE ((uint8_t) 0x00)
	TIM4 control register reset value. More...

#define	_TIM4_IER_RESET_VALUE ((uint8_t) 0x00)
	TIM4 interrupt enable register reset value. More...

#define	_TIM4_SR_RESET_VALUE ((uint8_t) 0x00)
	TIM4 status register reset value. More...

#define	_TIM4_EGR_RESET_VALUE ((uint8_t) 0x00)
	TIM4 event generation register reset value. More...

#define	_TIM4_CNTR_RESET_VALUE ((uint8_t) 0x00)
	TIM4 counter register reset value. More...

#define	_TIM4_PSCR_RESET_VALUE ((uint8_t) 0x00)
	TIM4 clock prescaler register reset value. More...

#define	_TIM4_ARR_RESET_VALUE ((uint8_t) 0xFF)
	TIM4 auto-reload register reset value. More...

#define	_TIM4_CEN ((uint8_t) (0x01 << 0))
	TIM4 Counter enable [0] (in _TIM4_CR) More...

#define	_TIM4_UDIS ((uint8_t) (0x01 << 1))
	TIM4 Update disable [0] (in _TIM4_CR) More...

#define	_TIM4_URS ((uint8_t) (0x01 << 2))
	TIM4 Update request source [0] (in _TIM4_CR) More...

#define	_TIM4_OPM ((uint8_t) (0x01 << 3))
	TIM4 One-pulse mode [0] (in _TIM4_CR) More...

#define	_TIM4_ARPE ((uint8_t) (0x01 << 7))
	TIM4 Auto-reload preload enable [0] (in _TIM4_CR) More...

#define	_TIM4_UIE ((uint8_t) (0x01 << 0))
	TIM4 Update interrupt enable [0] (in _TIM4_IER) More...

#define	_TIM4_UIF ((uint8_t) (0x01 << 0))
	TIM4 Update interrupt flag [0] (in _TIM4_SR) More...

#define	_TIM4_UG ((uint8_t) (0x01 << 0))
	TIM4 Update generation [0] (in _TIM4_EGR) More...

#define	_TIM4_PSC ((uint8_t) (0x07 << 0))
	TIM4 clock prescaler [2:0] (in _TIM4_PSCR) More...

#define	_TIM4_PSC0 ((uint8_t) (0x01 << 0))
	TIM4 clock prescaler [0] (in _TIM4_PSCR) More...

#define	_TIM4_PSC1 ((uint8_t) (0x01 << 1))
	TIM4 clock prescaler [1] (in _TIM4_PSCR) More...

#define	_TIM4_PSC2 ((uint8_t) (0x01 << 2))
	TIM4 clock prescaler [2] (in _TIM4_PSCR) More...

#define	_TIM5 _SFR(TIM5_t, TIM5_AddressBase)
	TIM5 struct/bit access. More...

#define	_TIM5_CR1 _SFR(uint8_t, TIM5_AddressBase+0x00)
	TIM5 control register 1. More...

#define	_TIM5_CR2 _SFR(uint8_t, TIM5_AddressBase+0x01)
	TIM5 control register 2. More...

#define	_TIM5_SMCR _SFR(uint8_t, TIM5_AddressBase+0x02)
	TIM5 Slave mode control register. More...

#define	_TIM5_IER _SFR(uint8_t, TIM5_AddressBase+0x03)
	TIM5 interrupt enable register. More...

#define	_TIM5_SR1 _SFR(uint8_t, TIM5_AddressBase+0x04)
	TIM5 status register 1. More...

#define	_TIM5_SR2 _SFR(uint8_t, TIM5_AddressBase+0x05)
	TIM5 status register 2. More...

#define	_TIM5_EGR _SFR(uint8_t, TIM5_AddressBase+0x06)
	TIM5 Event generation register. More...

#define	_TIM5_CCMR1 _SFR(uint8_t, TIM5_AddressBase+0x07)
	TIM5 Capture/compare mode register 1. More...

#define	_TIM5_CCMR2 _SFR(uint8_t, TIM5_AddressBase+0x08)
	TIM5 Capture/compare mode register 2. More...

#define	_TIM5_CCMR3 _SFR(uint8_t, TIM5_AddressBase+0x09)
	TIM5 Capture/compare mode register 3. More...

#define	_TIM5_CCER1 _SFR(uint8_t, TIM5_AddressBase+0x0A)
	TIM5 Capture/compare enable register 1. More...

#define	_TIM5_CCER2 _SFR(uint8_t, TIM5_AddressBase+0x0B)
	TIM5 Capture/compare enable register 2. More...

#define	_TIM5_CNTRH _SFR(uint8_t, TIM5_AddressBase+0x0C)
	TIM5 counter register high byte. More...

#define	_TIM5_CNTRL _SFR(uint8_t, TIM5_AddressBase+0x0D)
	TIM5 counter register low byte. More...

#define	_TIM5_PSCR _SFR(uint8_t, TIM5_AddressBase+0x0E)
	TIM5 clock prescaler register. More...

#define	_TIM5_ARRH _SFR(uint8_t, TIM5_AddressBase+0x0F)
	TIM5 auto-reload register high byte. More...

#define	_TIM5_ARRL _SFR(uint8_t, TIM5_AddressBase+0x10)
	TIM5 auto-reload register low byte. More...

#define	_TIM5_CCR1H _SFR(uint8_t, TIM5_AddressBase+0x11)
	TIM5 16-bit capture/compare value 1 high byte. More...

#define	_TIM5_CCR1L _SFR(uint8_t, TIM5_AddressBase+0x12)
	TIM5 16-bit capture/compare value 1 low byte. More...

#define	_TIM5_CCR2H _SFR(uint8_t, TIM5_AddressBase+0x13)
	TIM5 16-bit capture/compare value 2 high byte. More...

#define	_TIM5_CCR2L _SFR(uint8_t, TIM5_AddressBase+0x14)
	TIM5 16-bit capture/compare value 2 low byte. More...

#define	_TIM5_CCR3H _SFR(uint8_t, TIM5_AddressBase+0x15)
	TIM5 16-bit capture/compare value 3 high byte. More...

#define	_TIM5_CCR3L _SFR(uint8_t, TIM5_AddressBase+0x16)
	TIM5 16-bit capture/compare value 3 low byte. More...

#define	_TIM5_CR1_RESET_VALUE ((uint8_t) 0x00)
	TIM5 control register 1 reset value. More...

#define	_TIM5_CR2_RESET_VALUE ((uint8_t) 0x00)
	TIM5 control register 2 reset value. More...

#define	_TIM5_SMCR_RESET_VALUE ((uint8_t) 0x00)
	TIM5 Slave mode control register reset value. More...

#define	_TIM5_IER_RESET_VALUE ((uint8_t) 0x00)
	TIM5 interrupt enable register reset value. More...

#define	_TIM5_SR1_RESET_VALUE ((uint8_t) 0x00)
	TIM5 status register 1 reset value. More...

#define	_TIM5_SR2_RESET_VALUE ((uint8_t) 0x00)
	TIM5 status register 2 reset value. More...

#define	_TIM5_EGR_RESET_VALUE ((uint8_t) 0x00)
	TIM5 Event generation register reset value. More...

#define	_TIM5_CCMR1_RESET_VALUE ((uint8_t) 0x00)
	TIM5 Capture/compare mode register 1 reset value. More...

#define	_TIM5_CCMR2_RESET_VALUE ((uint8_t) 0x00)
	TIM5 Capture/compare mode register 2 reset value. More...

#define	_TIM5_CCMR3_RESET_VALUE ((uint8_t) 0x00)
	TIM5 Capture/compare mode register 3 reset value. More...

#define	_TIM5_CCER1_RESET_VALUE ((uint8_t) 0x00)
	TIM5 Capture/compare enable register 1 reset value. More...

#define	_TIM5_CCER2_RESET_VALUE ((uint8_t) 0x00)
	TIM5 Capture/compare enable register 2 reset value. More...

#define	_TIM5_CNTRH_RESET_VALUE ((uint8_t) 0x00)
	TIM5 counter register high byte reset value. More...

#define	_TIM5_CNTRL_RESET_VALUE ((uint8_t) 0x00)
	TIM5 counter register low byte reset value. More...

#define	_TIM5_PSCR_RESET_VALUE ((uint8_t) 0x00)
	TIM5 clock prescaler register reset value. More...

#define	_TIM5_ARRH_RESET_VALUE ((uint8_t) 0xFF)
	TIM5 auto-reload register high byte reset value. More...

#define	_TIM5_ARRL_RESET_VALUE ((uint8_t) 0xFF)
	TIM5 auto-reload register low byte reset value. More...

#define	_TIM5_CCR1H_RESET_VALUE ((uint8_t) 0x00)
	TIM5 16-bit capture/compare value 1 high byte reset value. More...

#define	_TIM5_CCR1L_RESET_VALUE ((uint8_t) 0x00)
	TIM5 16-bit capture/compare value 1 low byte reset value. More...

#define	_TIM5_CCR2H_RESET_VALUE ((uint8_t) 0x00)
	TIM5 16-bit capture/compare value 2 high byte reset value. More...

#define	_TIM5_CCR2L_RESET_VALUE ((uint8_t) 0x00)
	TIM5 16-bit capture/compare value 2 low byte reset value. More...

#define	_TIM5_CCR3H_RESET_VALUE ((uint8_t) 0x00)
	TIM5 16-bit capture/compare value 3 high byte reset value. More...

#define	_TIM5_CCR3L_RESET_VALUE ((uint8_t) 0x00)
	TIM5 16-bit capture/compare value 3 low byte reset value. More...

#define	_TIM5_CEN ((uint8_t) (0x01 << 0))
	TIM5 Counter enable [0] (in _TIM5_CR1) More...

#define	_TIM5_UDIS ((uint8_t) (0x01 << 1))
	TIM5 Update disable [0] (in _TIM5_CR1) More...

#define	_TIM5_URS ((uint8_t) (0x01 << 2))
	TIM5 Update request source [0] (in _TIM5_CR1) More...

#define	_TIM5_OPM ((uint8_t) (0x01 << 3))
	TIM5 One-pulse mode [0] (in _TIM5_CR1) More...

#define	_TIM5_ARPE ((uint8_t) (0x01 << 7))
	TIM5 Auto-reload preload enable [0] (in _TIM5_CR1) More...

#define	_TIM5_CCPC ((uint8_t) (0x01 << 0))
	TIM5 Capture/compare preloaded control [0] (in _TIM5_CR2) More...

#define	_TIM5_COMS ((uint8_t) (0x01 << 2))
	TIM5 Capture/compare control update selection [0] (in _TIM5_CR2) More...

#define	_TIM5_MMS ((uint8_t) (0x07 << 4))
	TIM5 Master mode selection [2:0] (in _TIM5_CR2) More...

#define	_TIM5_MMS0 ((uint8_t) (0x01 << 4))
	TIM5 Master mode selection [0] (in _TIM5_CR2) More...

#define	_TIM5_MMS1 ((uint8_t) (0x01 << 5))
	TIM5 Master mode selection [1] (in _TIM5_CR2) More...

#define	_TIM5_MMS2 ((uint8_t) (0x01 << 6))
	TIM5 Master mode selection [2] (in _TIM5_CR2) More...

#define	_TIM5_SMS ((uint8_t) (0x07 << 0))
	TIM5 Clock/trigger/slave mode selection [2:0] (in _TIM5_SMCR) More...

#define	_TIM5_SMS0 ((uint8_t) (0x01 << 0))
	TIM5 Clock/trigger/slave mode selection [0] (in _TIM5_SMCR) More...

#define	_TIM5_SMS1 ((uint8_t) (0x01 << 1))
	TIM5 Clock/trigger/slave mode selection [1] (in _TIM5_SMCR) More...

#define	_TIM5_SMS2 ((uint8_t) (0x01 << 2))
	TIM5 Clock/trigger/slave mode selection [2] (in _TIM5_SMCR) More...

#define	_TIM5_TS ((uint8_t) (0x07 << 4))
	TIM5 Trigger selection [2:0] (in _TIM5_SMCR) More...

#define	_TIM5_TS0 ((uint8_t) (0x01 << 4))
	TIM5 Trigger selection [0] (in _TIM5_SMCR) More...

#define	_TIM5_TS1 ((uint8_t) (0x01 << 5))
	TIM5 Trigger selection [1] (in _TIM5_SMCR) More...

#define	_TIM5_TS2 ((uint8_t) (0x01 << 6))
	TIM5 Trigger selection [2] (in _TIM5_SMCR) More...

#define	_TIM5_MSM ((uint8_t) (0x01 << 7))
	TIM5 Master/slave mode [0] (in _TIM5_SMCR) More...

#define	_TIM5_UIE ((uint8_t) (0x01 << 0))
	TIM5 Update interrupt enable [0] (in _TIM5_IER) More...

#define	_TIM5_CC1IE ((uint8_t) (0x01 << 1))
	TIM5 Capture/compare 1 interrupt enable [0] (in _TIM5_IER) More...

#define	_TIM5_CC2IE ((uint8_t) (0x01 << 2))
	TIM5 Capture/compare 2 interrupt enable [0] (in _TIM5_IER) More...

#define	_TIM5_CC3IE ((uint8_t) (0x01 << 3))
	TIM5 Capture/compare 3 interrupt enable [0] (in _TIM5_IER) More...

#define	_TIM5_TIE ((uint8_t) (0x01 << 6))
	TIM5 Trigger interrupt enable [0] (in _TIM5_IER) More...

#define	_TIM5_UIF ((uint8_t) (0x01 << 0))
	TIM5 Update interrupt flag [0] (in _TIM5_SR1) More...

#define	_TIM5_CC1IF ((uint8_t) (0x01 << 1))
	TIM5 Capture/compare 1 interrupt flag [0] (in _TIM5_SR1) More...

#define	_TIM5_CC2IF ((uint8_t) (0x01 << 2))
	TIM5 Capture/compare 2 interrupt flag [0] (in _TIM5_SR1) More...

#define	_TIM5_CC3IF ((uint8_t) (0x01 << 3))
	TIM5 Capture/compare 3 interrupt flag [0] (in _TIM5_SR1) More...

#define	_TIM5_TIF ((uint8_t) (0x01 << 6))
	TIM5 Trigger interrupt flag [0] (in _TIM5_SR1) More...

#define	_TIM5_CC1OF ((uint8_t) (0x01 << 1))
	TIM5 Capture/compare 1 overcapture flag [0] (in _TIM5_SR2) More...

#define	_TIM5_CC2OF ((uint8_t) (0x01 << 2))
	TIM5 Capture/compare 2 overcapture flag [0] (in _TIM5_SR2) More...

#define	_TIM5_CC3OF ((uint8_t) (0x01 << 3))
	TIM5 Capture/compare 3 overcapture flag [0] (in _TIM5_SR2) More...

#define	_TIM5_UG ((uint8_t) (0x01 << 0))
	TIM5 Update generation [0] (in _TIM5_EGR) More...

#define	_TIM5_CC1G ((uint8_t) (0x01 << 1))
	TIM5 Capture/compare 1 generation [0] (in _TIM5_EGR) More...

#define	_TIM5_CC2G ((uint8_t) (0x01 << 2))
	TIM5 Capture/compare 2 generation [0] (in _TIM5_EGR) More...

#define	_TIM5_CC3G ((uint8_t) (0x01 << 3))
	TIM5 Capture/compare 3 generation [0] (in _TIM5_EGR) More...

#define	_TIM5_TG ((uint8_t) (0x01 << 6))
	TIM5 Trigger generation [0] (in _TIM5_EGR) More...

#define	_TIM5_CC1S ((uint8_t) (0x03 << 0))
	TIM5 Compare 1 selection [1:0] (in _TIM5_CCMR1) More...

#define	_TIM5_CC1S0 ((uint8_t) (0x01 << 0))
	TIM5 Compare 1 selection [0] (in _TIM5_CCMR1) More...

#define	_TIM5_CC1S1 ((uint8_t) (0x01 << 1))
	TIM5 Compare 1 selection [1] (in _TIM5_CCMR1) More...

#define	_TIM5_OC1PE ((uint8_t) (0x01 << 3))
	TIM5 Output compare 1 preload enable [0] (in _TIM5_CCMR1) More...

#define	_TIM5_OC1M ((uint8_t) (0x07 << 4))
	TIM5 Output compare 1 mode [2:0] (in _TIM5_CCMR1) More...

#define	_TIM5_OC1M0 ((uint8_t) (0x01 << 4))
	TIM5 Output compare 1 mode [0] (in _TIM5_CCMR1) More...

#define	_TIM5_OC1M1 ((uint8_t) (0x01 << 5))
	TIM5 Output compare 1 mode [1] (in _TIM5_CCMR1) More...

#define	_TIM5_OC1M2 ((uint8_t) (0x01 << 6))
	TIM5 Output compare 1 mode [2] (in _TIM5_CCMR1) More...

#define	_TIM5_IC1PSC ((uint8_t) (0x03 << 2))
	TIM5 Input capture 1 prescaler [1:0] (in _TIM5_CCMR1) More...

#define	_TIM5_IC1PSC0 ((uint8_t) (0x01 << 2))
	TIM5 Input capture 1 prescaler [0] (in _TIM5_CCMR1) More...

#define	_TIM5_IC1PSC1 ((uint8_t) (0x01 << 3))
	TIM5 Input capture 1 prescaler [1] (in _TIM5_CCMR1) More...

#define	_TIM5_IC1F ((uint8_t) (0x0F << 4))
	TIM5 Output compare 1 mode [3:0] (in _TIM5_CCMR1) More...

#define	_TIM5_IC1F0 ((uint8_t) (0x01 << 4))
	TIM5 Input capture 1 filter [0] (in _TIM5_CCMR1) More...

#define	_TIM5_IC1F1 ((uint8_t) (0x01 << 5))
	TIM5 Input capture 1 filter [1] (in _TIM5_CCMR1) More...

#define	_TIM5_IC1F2 ((uint8_t) (0x01 << 6))
	TIM5 Input capture 1 filter [2] (in _TIM5_CCMR1) More...

#define	_TIM5_IC1F3 ((uint8_t) (0x01 << 7))
	TIM5 Input capture 1 filter [3] (in _TIM5_CCMR1) More...

#define	_TIM5_CC2S ((uint8_t) (0x03 << 0))
	TIM5 Compare 2 selection [1:0] (in _TIM5_CCMR2) More...

#define	_TIM5_CC2S0 ((uint8_t) (0x01 << 0))
	TIM5 Compare 2 selection [0] (in _TIM5_CCMR2) More...

#define	_TIM5_CC2S1 ((uint8_t) (0x01 << 1))
	TIM5 Compare 2 selection [1] (in _TIM5_CCMR2) More...

#define	_TIM5_OC2PE ((uint8_t) (0x01 << 3))
	TIM5 Output compare 2 preload enable [0] (in _TIM5_CCMR2) More...

#define	_TIM5_OC2M ((uint8_t) (0x07 << 4))
	TIM5 Output compare 2 mode [2:0] (in _TIM5_CCMR2) More...

#define	_TIM5_OC2M0 ((uint8_t) (0x01 << 4))
	TIM5 Output compare 2 mode [0] (in _TIM5_CCMR2) More...

#define	_TIM5_OC2M1 ((uint8_t) (0x01 << 5))
	TIM5 Output compare 2 mode [1] (in _TIM5_CCMR2) More...

#define	_TIM5_OC2M2 ((uint8_t) (0x01 << 6))
	TIM5 Output compare 2 mode [2] (in _TIM5_CCMR2) More...

#define	_TIM5_IC2PSC ((uint8_t) (0x03 << 2))
	TIM5 Input capture 2 prescaler [1:0] (in _TIM5_CCMR2) More...

#define	_TIM5_IC2PSC0 ((uint8_t) (0x01 << 2))
	TIM5 Input capture 2 prescaler [0] (in _TIM5_CCMR2) More...

#define	_TIM5_IC2PSC1 ((uint8_t) (0x01 << 3))
	TIM5 Input capture 2 prescaler [1] (in _TIM5_CCMR2) More...

#define	_TIM5_IC2F ((uint8_t) (0x0F << 4))
	TIM5 Output compare 2 mode [3:0] (in _TIM5_CCMR2) More...

#define	_TIM5_IC2F0 ((uint8_t) (0x01 << 4))
	TIM5 Input capture 2 filter [0] (in _TIM5_CCMR2) More...

#define	_TIM5_IC2F1 ((uint8_t) (0x01 << 5))
	TIM5 Input capture 2 filter [1] (in _TIM5_CCMR2) More...

#define	_TIM5_IC2F2 ((uint8_t) (0x01 << 6))
	TIM5 Input capture 2 filter [2] (in _TIM5_CCMR2) More...

#define	_TIM5_IC2F3 ((uint8_t) (0x01 << 7))
	TIM5 Input capture 2 filter [3] (in _TIM5_CCMR2) More...

#define	_TIM5_CC3S ((uint8_t) (0x03 << 0))
	TIM5 Compare 3 selection [1:0] (in _TIM5_CCMR3) More...

#define	_TIM5_CC3S0 ((uint8_t) (0x01 << 0))
	TIM5 Compare 3 selection [0] (in _TIM5_CCMR3) More...

#define	_TIM5_CC3S1 ((uint8_t) (0x01 << 1))
	TIM5 Compare 3 selection [1] (in _TIM5_CCMR3) More...

#define	_TIM5_OC3PE ((uint8_t) (0x01 << 3))
	TIM5 Output compare 3 preload enable [0] (in _TIM5_CCMR3) More...

#define	_TIM5_OC3M ((uint8_t) (0x07 << 4))
	TIM5 Output compare 3 mode [2:0] (in _TIM5_CCMR3) More...

#define	_TIM5_OC3M0 ((uint8_t) (0x01 << 4))
	TIM5 Output compare 3 mode [0] (in _TIM5_CCMR3) More...

#define	_TIM5_OC3M1 ((uint8_t) (0x01 << 5))
	TIM5 Output compare 3 mode [1] (in _TIM5_CCMR3) More...

#define	_TIM5_OC3M2 ((uint8_t) (0x01 << 6))
	TIM5 Output compare 3 mode [2] (in _TIM5_CCMR3) More...

#define	_TIM5_IC3PSC ((uint8_t) (0x03 << 2))
	TIM5 Input capture 3 prescaler [1:0] (in _TIM5_CCMR3) More...

#define	_TIM5_IC3PSC0 ((uint8_t) (0x01 << 2))
	TIM5 Input capture 3 prescaler [0] (in _TIM5_CCMR3) More...

#define	_TIM5_IC3PSC1 ((uint8_t) (0x01 << 3))
	TIM5 Input capture 3 prescaler [1] (in _TIM5_CCMR3) More...

#define	_TIM5_IC3F ((uint8_t) (0x0F << 4))
	TIM5 Output compare 3 mode [3:0] (in _TIM5_CCMR3) More...

#define	_TIM5_IC3F0 ((uint8_t) (0x01 << 4))
	TIM5 Input capture 3 filter [0] (in _TIM5_CCMR3) More...

#define	_TIM5_IC3F1 ((uint8_t) (0x01 << 5))
	TIM5 Input capture 3 filter [1] (in _TIM5_CCMR3) More...

#define	_TIM5_IC3F2 ((uint8_t) (0x01 << 6))
	TIM5 Input capture 3 filter [2] (in _TIM5_CCMR3) More...

#define	_TIM5_IC3F3 ((uint8_t) (0x01 << 7))
	TIM5 Input capture 3 filter [3] (in _TIM5_CCMR3) More...

#define	_TIM5_CC1E ((uint8_t) (0x01 << 0))
	TIM5 Capture/compare 1 output enable [0] (in _TIM5_CCER1) More...

#define	_TIM5_CC1P ((uint8_t) (0x01 << 1))
	TIM5 Capture/compare 1 output polarity [0] (in _TIM5_CCER1) More...

#define	_TIM5_CC2E ((uint8_t) (0x01 << 4))
	TIM5 Capture/compare 2 output enable [0] (in _TIM5_CCER1) More...

#define	_TIM5_CC2P ((uint8_t) (0x01 << 5))
	TIM5 Capture/compare 2 output polarity [0] (in _TIM5_CCER1) More...

#define	_TIM5_CC3E ((uint8_t) (0x01 << 0))
	TIM5 Capture/compare 3 output enable [0] (in _TIM5_CCER2) More...

#define	_TIM5_CC3P ((uint8_t) (0x01 << 1))
	TIM5 Capture/compare 3 output polarity [0] (in _TIM5_CCER2) More...

#define	_TIM5_PSC ((uint8_t) (0x0F << 0))
	TIM5 clock prescaler [3:0] (in _TIM5_PSCR) More...

#define	_TIM5_PSC0 ((uint8_t) (0x01 << 0))
	TIM5 clock prescaler [0] (in _TIM5_PSCR) More...

#define	_TIM5_PSC1 ((uint8_t) (0x01 << 1))
	TIM5 clock prescaler [1] (in _TIM5_PSCR) More...

#define	_TIM5_PSC2 ((uint8_t) (0x01 << 2))
	TIM5 clock prescaler [2] (in _TIM5_PSCR) More...

#define	_TIM5_PSC3 ((uint8_t) (0x01 << 3))
	TIM5 clock prescaler [3] (in _TIM5_PSCR) More...

#define	_TIM6 _SFR(TIM6_t, TIM6_AddressBase)
	TIM6 struct/bit access. More...

#define	_TIM6_CR _SFR(uint8_t, TIM6_AddressBase+0x00)
	TIM6 control register. More...

#define	_TIM6_IER _SFR(uint8_t, TIM6_AddressBase+0x01)
	TIM6 interrupt enable register. More...

#define	_TIM6_SR _SFR(uint8_t, TIM6_AddressBase+0x02)
	TIM6 status register. More...

#define	_TIM6_EGR _SFR(uint8_t, TIM6_AddressBase+0x03)
	TIM6 event generation register. More...

#define	_TIM6_CNTR _SFR(uint8_t, TIM6_AddressBase+0x04)
	TIM6 counter register. More...

#define	_TIM6_PSCR _SFR(uint8_t, TIM6_AddressBase+0x05)
	TIM6 clock prescaler register. More...

#define	_TIM6_ARR _SFR(uint8_t, TIM6_AddressBase+0x06)
	TIM6 auto-reload register. More...

#define	_TIM6_CR_RESET_VALUE ((uint8_t) 0x00)
	TIM6 control register reset value. More...

#define	_TIM6_IER_RESET_VALUE ((uint8_t) 0x00)
	TIM6 interrupt enable register reset value. More...

#define	_TIM6_SR_RESET_VALUE ((uint8_t) 0x00)
	TIM6 status register reset value. More...

#define	_TIM6_EGR_RESET_VALUE ((uint8_t) 0x00)
	TIM6 event generation register reset value. More...

#define	_TIM6_CNTR_RESET_VALUE ((uint8_t) 0x00)
	TIM6 counter register reset value. More...

#define	_TIM6_PSCR_RESET_VALUE ((uint8_t) 0x00)
	TIM6 clock prescaler register reset value. More...

#define	_TIM6_ARR_RESET_VALUE ((uint8_t) 0xFF)
	TIM6 auto-reload register reset value. More...

#define	_TIM6_CEN ((uint8_t) (0x01 << 0))
	TIM6 Counter enable [0] (in _TIM6_CR1) More...

#define	_TIM6_UDIS ((uint8_t) (0x01 << 1))
	TIM6 Update disable [0] (in _TIM6_CR1) More...

#define	_TIM6_URS ((uint8_t) (0x01 << 2))
	TIM6 Update request source [0] (in _TIM6_CR1) More...

#define	_TIM6_OPM ((uint8_t) (0x01 << 3))
	TIM6 One-pulse mode [0] (in _TIM6_CR1) More...

#define	_TIM6_ARPE ((uint8_t) (0x01 << 7))
	TIM6 Auto-reload preload enable [0] (in _TIM6_CR1) More...

#define	_TIM6_MMS ((uint8_t) (0x07 << 4))
	TIM6 Master mode selection [2:0] (in _TIM6_CR2) More...

#define	_TIM6_MMS0 ((uint8_t) (0x01 << 4))
	TIM6 Master mode selection [0] (in _TIM6_CR2) More...

#define	_TIM6_MMS1 ((uint8_t) (0x01 << 5))
	TIM6 Master mode selection [1] (in _TIM6_CR2) More...

#define	_TIM6_MMS2 ((uint8_t) (0x01 << 6))
	TIM6 Master mode selection [2] (in _TIM6_CR2) More...

#define	_TIM6_SMS ((uint8_t) (0x07 << 0))
	TIM6 Clock/trigger/slave mode selection [2:0] (in _TIM6_SMCR) More...

#define	_TIM6_SMS0 ((uint8_t) (0x01 << 0))
	TIM6 Clock/trigger/slave mode selection [0] (in _TIM6_SMCR) More...

#define	_TIM6_SMS1 ((uint8_t) (0x01 << 1))
	TIM6 Clock/trigger/slave mode selection [1] (in _TIM6_SMCR) More...

#define	_TIM6_SMS2 ((uint8_t) (0x01 << 2))
	TIM6 Clock/trigger/slave mode selection [2] (in _TIM6_SMCR) More...

#define	_TIM6_TS ((uint8_t) (0x07 << 4))
	TIM6 Trigger selection [2:0] (in _TIM6_SMCR) More...

#define	_TIM6_TS0 ((uint8_t) (0x01 << 4))
	TIM6 Trigger selection [0] (in _TIM6_SMCR) More...

#define	_TIM6_TS1 ((uint8_t) (0x01 << 5))
	TIM6 Trigger selection [1] (in _TIM6_SMCR) More...

#define	_TIM6_TS2 ((uint8_t) (0x01 << 6))
	TIM6 Trigger selection [2] (in _TIM6_SMCR) More...

#define	_TIM6_UIE ((uint8_t) (0x01 << 0))
	TIM6 Update interrupt enable [0] (in _TIM6_IER) More...

#define	_TIM6_UIF ((uint8_t) (0x01 << 0))
	TIM6 Update interrupt flag [0] (in _TIM6_SR) More...

#define	_TIM6_UG ((uint8_t) (0x01 << 0))
	TIM6 Update generation [0] (in _TIM6_EGR) More...

#define	_TIM6_PSC ((uint8_t) (0x07 << 0))
	TIM6 clock prescaler [2:0] (in _TIM6_PSCR) More...

#define	_TIM6_PSC0 ((uint8_t) (0x01 << 0))
	TIM6 clock prescaler [0] (in _TIM6_PSCR) More...

#define	_TIM6_PSC1 ((uint8_t) (0x01 << 1))
	TIM6 clock prescaler [1] (in _TIM6_PSCR) More...

#define	_TIM6_PSC2 ((uint8_t) (0x01 << 2))
	TIM6 clock prescaler [2] (in _TIM6_PSCR) More...

#define	_ADC1 _SFR(ADC1_t, ADC1_AddressBase)
	ADC1 struct/bit access. More...

#define	_ADC1_DB0RH _SFR(uint8_t, ADC1_AddressBase+0x00)
	ADC1 10-bit Data Buffer Register 0. More...

#define	_ADC1_DB0RL _SFR(uint8_t, ADC1_AddressBase+0x01)
	ADC1 10-bit Data Buffer Register 0. More...

#define	_ADC1_DB1RH _SFR(uint8_t, ADC1_AddressBase+0x02)
	ADC1 10-bit Data Buffer Register 1. More...

#define	_ADC1_DB1RL _SFR(uint8_t, ADC1_AddressBase+0x03)
	ADC1 10-bit Data Buffer Register 1. More...

#define	_ADC1_DB2RH _SFR(uint8_t, ADC1_AddressBase+0x04)
	ADC1 10-bit Data Buffer Register 2. More...

#define	_ADC1_DB2RL _SFR(uint8_t, ADC1_AddressBase+0x05)
	ADC1 10-bit Data Buffer Register 2. More...

#define	_ADC1_DB3RH _SFR(uint8_t, ADC1_AddressBase+0x06)
	ADC1 10-bit Data Buffer Register 3. More...

#define	_ADC1_DB3RL _SFR(uint8_t, ADC1_AddressBase+0x07)
	ADC1 10-bit Data Buffer Register 3. More...

#define	_ADC1_DB4RH _SFR(uint8_t, ADC1_AddressBase+0x08)
	ADC1 10-bit Data Buffer Register 4. More...

#define	_ADC1_DB4RL _SFR(uint8_t, ADC1_AddressBase+0x09)
	ADC1 10-bit Data Buffer Register 4. More...

#define	_ADC1_DB5RH _SFR(uint8_t, ADC1_AddressBase+0x0A)
	ADC1 10-bit Data Buffer Register 5. More...

#define	_ADC1_DB5RL _SFR(uint8_t, ADC1_AddressBase+0x0B)
	ADC1 10-bit Data Buffer Register 5. More...

#define	_ADC1_DB6RH _SFR(uint8_t, ADC1_AddressBase+0x0C)
	ADC1 10-bit Data Buffer Register 6. More...

#define	_ADC1_DB6RL _SFR(uint8_t, ADC1_AddressBase+0x0D)
	ADC1 10-bit Data Buffer Register 6. More...

#define	_ADC1_DB7RH _SFR(uint8_t, ADC1_AddressBase+0x0E)
	ADC1 10-bit Data Buffer Register 7. More...

#define	_ADC1_DB7RL _SFR(uint8_t, ADC1_AddressBase+0x0F)
	ADC1 10-bit Data Buffer Register 7. More...

#define	_ADC1_DB8RH _SFR(uint8_t, ADC1_AddressBase+0x10)
	ADC1 10-bit Data Buffer Register 8. More...

#define	_ADC1_DB8RL _SFR(uint8_t, ADC1_AddressBase+0x11)
	ADC1 10-bit Data Buffer Register 8. More...

#define	_ADC1_DB9RH _SFR(uint8_t, ADC1_AddressBase+0x12)
	ADC1 10-bit Data Buffer Register 9. More...

#define	_ADC1_DB9RL _SFR(uint8_t, ADC1_AddressBase+0x13)
	ADC1 10-bit Data Buffer Register 9. More...

#define	_ADC1_CSR _SFR(uint8_t, ADC1_AddressBase+0x20)
	ADC1 control/status register. More...

#define	_ADC1_CR1 _SFR(uint8_t, ADC1_AddressBase+0x21)
	ADC1 Configuration Register 1. More...

#define	_ADC1_CR2 _SFR(uint8_t, ADC1_AddressBase+0x22)
	ADC1 Configuration Register 2. More...

#define	_ADC1_CR3 _SFR(uint8_t, ADC1_AddressBase+0x23)
	ADC1 Configuration Register 3. More...

#define	_ADC1_DRH _SFR(uint8_t, ADC1_AddressBase+0x24)
	ADC1 (unbuffered) 10-bit measurement result. More...

#define	_ADC1_DRL _SFR(uint8_t, ADC1_AddressBase+0x25)
	ADC1 (unbuffered) 10-bit measurement result. More...

#define	_ADC1_TDRH _SFR(uint8_t, ADC1_AddressBase+0x26)
	ADC1 Schmitt trigger disable register. More...

#define	_ADC1_TDRL _SFR(uint8_t, ADC1_AddressBase+0x27)
	ADC1 Schmitt trigger disable register. More...

#define	_ADC1_HTRH _SFR(uint8_t, ADC1_AddressBase+0x28)
	ADC1 watchdog high threshold register. More...

#define	_ADC1_HTRL _SFR(uint8_t, ADC1_AddressBase+0x29)
	ADC1 watchdog high threshold register. More...

#define	_ADC1_LTRH _SFR(uint8_t, ADC1_AddressBase+0x2A)
	ADC1 watchdog low threshold register. More...

#define	_ADC1_LTRL _SFR(uint8_t, ADC1_AddressBase+0x2B)
	ADC1 watchdog low threshold register. More...

#define	_ADC1_AWSRH _SFR(uint8_t, ADC1_AddressBase+0x2C)
	ADC1 watchdog status register. More...

#define	_ADC1_AWSRL _SFR(uint8_t, ADC1_AddressBase+0x2D)
	ADC1 watchdog status register. More...

#define	_ADC1_AWCRH _SFR(uint8_t, ADC1_AddressBase+0x2E)
	ADC1 watchdog control register. More...

#define	_ADC1_AWCRL _SFR(uint8_t, ADC1_AddressBase+0x2F)
	ADC1 watchdog control register. More...

#define	_ADC1_CSR_RESET_VALUE ((uint8_t) 0x00)
	ADC1 control/status register reset value. More...

#define	_ADC1_CR1_RESET_VALUE ((uint8_t) 0x00)
	ADC1 Configuration Register 1 reset value. More...

#define	_ADC1_CR2_RESET_VALUE ((uint8_t) 0x00)
	ADC1 Configuration Register 2 reset value. More...

#define	_ADC1_CR3_RESET_VALUE ((uint8_t) 0x00)
	ADC1 Configuration Register 3 reset value. More...

#define	_ADC1_TDRH_RESET_VALUE ((uint8_t) 0x00)
	ADC1 Schmitt trigger disable register reset value. More...

#define	_ADC1_TDRL_RESET_VALUE ((uint8_t) 0x00)
	ADC1 Schmitt trigger disable register reset value. More...

#define	_ADC1_HTRH_RESET_VALUE ((uint8_t) 0xFF)
	ADC1 watchdog high threshold register reset value. More...

#define	_ADC1_HTRL_RESET_VALUE ((uint8_t) 0x03)
	ADC1 watchdog high threshold register reset value. More...

#define	_ADC1_LTRH_RESET_VALUE ((uint8_t) 0x00)
	ADC1 watchdog low threshold register reset value. More...

#define	_ADC1_LTRL_RESET_VALUE ((uint8_t) 0x00)
	ADC1 watchdog low threshold register reset value. More...

#define	_ADC1_AWCRH_RESET_VALUE ((uint8_t) 0x00)
	ADC1 watchdog control register reset value. More...

#define	_ADC1_AWCRL_RESET_VALUE ((uint8_t) 0x00)
	ADC1 watchdog control register reset value. More...

#define	_ADC1_CH ((uint8_t) (0x0F << 0))
	ADC1 Channel selection bits [3:0] (in _ADC1_CSR) More...

#define	_ADC1_CH0 ((uint8_t) (0x01 << 0))
	ADC1 Channel selection bits [0] (in _ADC1_CSR) More...

#define	_ADC1_CH1 ((uint8_t) (0x01 << 1))
	ADC1 Channel selection bits [1] (in _ADC1_CSR) More...

#define	_ADC1_CH2 ((uint8_t) (0x01 << 2))
	ADC1 Channel selection bits [2] (in _ADC1_CSR) More...

#define	_ADC1_CH3 ((uint8_t) (0x01 << 3))
	ADC1 Channel selection bits [3] (in _ADC1_CSR) More...

#define	_ADC1_AWDIE ((uint8_t) (0x01 << 4))
	ADC1 Analog watchdog interrupt enable [0] (in _ADC1_CSR) More...

#define	_ADC1_EOCIE ((uint8_t) (0x01 << 5))
	ADC1 Interrupt enable for EOC [0] (in _ADC1_CSR) More...

#define	_ADC1_AWD ((uint8_t) (0x01 << 6))
	ADC1 Analog Watchdog flag [0] (in _ADC1_CSR) More...

#define	_ADC1_EOC ((uint8_t) (0x01 << 7))
	ADC1 End of conversion [0] (in _ADC1_CSR) More...

#define	_ADC1_ADON ((uint8_t) (0x01 << 0))
	ADC1 Conversion on/off [0] (in _ADC1_CR1) More...

#define	_ADC1_CONT ((uint8_t) (0x01 << 1))
	ADC1 Continuous conversion [0] (in _ADC1_CR1) More...

#define	_ADC1_SPSEL ((uint8_t) (0x07 << 4)
	ADC1 clock prescaler selection [2:0] (in _ADC1_CR1) More...

#define	_ADC1_SPSEL0 ((uint8_t) (0x01 << 4)
	ADC1 clock prescaler selection [0] (in _ADC1_CR1) More...

#define	_ADC1_SPSEL1 ((uint8_t) (0x01 << 5)
	ADC1 clock prescaler selection [1] (in _ADC1_CR1) More...

#define	_ADC1_SPSEL2 ((uint8_t) (0x01 << 6)
	ADC1 clock prescaler selection [2] (in _ADC1_CR1) More...

#define	_ADC1_SCAN ((uint8_t) (0x01 << 1))
	ADC1 Scan mode enable [0] (in _ADC1_CR2) More...

#define	_ADC1_ALIGN ((uint8_t) (0x01 << 3))
	ADC1 Data alignment [0] (in _ADC1_CR2) More...

#define	_ADC1_EXTSEL ((uint8_t) (0x03 << 4)
	ADC1 External event selection [1:0] (in _ADC1_CR2) More...

#define	_ADC1_EXTSEL0 ((uint8_t) (0x01 << 4)
	ADC1 External event selection [0] (in _ADC1_CR2) More...

#define	_ADC1_EXTSEL1 ((uint8_t) (0x01 << 5)
	ADC1 External event selection [1] (in _ADC1_CR2) More...

#define	_ADC1_EXTTRIG ((uint8_t) (0x01 << 6))
	ADC1 External trigger enable [0] (in _ADC1_CR2) More...

#define	_ADC1_OVR ((uint8_t) (0x01 << 6))
	ADC1 Overrun flag [0] (in _ADC1_CR3) More...

#define	_ADC1_DBUF ((uint8_t) (0x01 << 7))
	ADC1 Data buffer enable [0] (in _ADC1_CR3) More...

#define	_ADC2 _SFR(ADC2_t, ADC2_AddressBase)
	ADC2 struct/bit access. More...

#define	_ADC2_CSR _SFR(uint8_t, ADC2_AddressBase+0x00)
	ADC2 control/status register. More...

#define	_ADC2_CR1 _SFR(uint8_t, ADC2_AddressBase+0x01)
	ADC2 Configuration Register 1. More...

#define	_ADC2_CR2 _SFR(uint8_t, ADC2_AddressBase+0x02)
	ADC2 Configuration Register 2. More...

#define	_ADC2_DRH _SFR(uint8_t, ADC2_AddressBase+0x04)
	ADC2 (unbuffered) 10-bit measurement result. More...

#define	_ADC2_DRL _SFR(uint8_t, ADC2_AddressBase+0x05)
	ADC2 (unbuffered) 10-bit measurement result. More...

#define	_ADC2_TDRH _SFR(uint8_t, ADC2_AddressBase+0x06)
	ADC2 Schmitt trigger disable register. More...

#define	_ADC2_TDRL _SFR(uint8_t, ADC2_AddressBase+0x07)
	ADC2 Schmitt trigger disable register. More...

#define	_ADC2_CSR_RESET_VALUE ((uint8_t) 0x00)
	ADC2 control/status register reset value. More...

#define	_ADC2_CR1_RESET_VALUE ((uint8_t) 0x00)
	ADC2 Configuration Register 1 reset value. More...

#define	_ADC2_CR2_RESET_VALUE ((uint8_t) 0x00)
	ADC2 Configuration Register 2 reset value. More...

#define	_ADC2_TDRL_RESET_VALUE ((uint8_t) 0x00)
	ADC2 Schmitt trigger disable register reset value. More...

#define	_ADC2_TDRH_RESET_VALUE ((uint8_t) 0x00)
	ADC2 Schmitt trigger disable register reset value. More...

#define	_ADC2_CH ((uint8_t) (0x0F << 0))
	ADC2 Channel selection bits [3:0] (in _ADC2_CSR) More...

#define	_ADC2_CH0 ((uint8_t) (0x01 << 0))
	ADC2 Channel selection bits [0] (in _ADC2_CSR) More...

#define	_ADC2_CH1 ((uint8_t) (0x01 << 1))
	ADC2 Channel selection bits [1] (in _ADC2_CSR) More...

#define	_ADC2_CH2 ((uint8_t) (0x01 << 2))
	ADC2 Channel selection bits [2] (in _ADC2_CSR) More...

#define	_ADC2_CH3 ((uint8_t) (0x01 << 3))
	ADC2 Channel selection bits [3] (in _ADC2_CSR) More...

#define	_ADC2_EOCIE ((uint8_t) (0x01 << 5))
	ADC2 Interrupt enable for EOC [0] (in _ADC2_CSR) More...

#define	_ADC2_EOC ((uint8_t) (0x01 << 7))
	ADC2 End of conversion [0] (in _ADC2_CSR) More...

#define	_ADC2_ADON ((uint8_t) (0x01 << 0))
	ADC2 Conversion on/off [0] (in _ADC2_CR1) More...

#define	_ADC2_CONT ((uint8_t) (0x01 << 1))
	ADC2 Continuous conversion [0] (in _ADC2_CR1) More...

#define	_ADC2_SPSEL ((uint8_t) (0x07 << 4)
	ADC2 clock prescaler selection [2:0] (in _ADC2_CR1) More...

#define	_ADC2_SPSEL0 ((uint8_t) (0x01 << 4)
	ADC2 clock prescaler selection [0] (in _ADC2_CR1) More...

#define	_ADC2_SPSEL1 ((uint8_t) (0x01 << 5)
	ADC2 clock prescaler selection [1] (in _ADC2_CR1) More...

#define	_ADC2_SPSEL2 ((uint8_t) (0x01 << 6)
	ADC2 clock prescaler selection [2] (in _ADC2_CR1) More...

#define	_ADC2_ALIGN ((uint8_t) (0x01 << 3))
	ADC2 Data alignment [0] (in _ADC2_CR2) More...

#define	_ADC2_EXTSEL ((uint8_t) (0x03 << 4)
	ADC2 External event selection [1:0] (in _ADC2_CR2) More...

#define	_ADC2_EXTSEL0 ((uint8_t) (0x01 << 4)
	ADC2 External event selection [0] (in _ADC2_CR2) More...

#define	_ADC2_EXTSEL1 ((uint8_t) (0x01 << 5)
	ADC2 External event selection [1] (in _ADC2_CR2) More...

#define	_ADC2_EXTTRIG ((uint8_t) (0x01 << 6))
	ADC2 External trigger enable [0] (in _ADC2_CR2) More...

#define	_CAN _SFR(CAN_t, CAN_AddressBase)
	CAN struct/bit access. More...

#define	_CAN_MCR _SFR(uint8_t, CAN_AddressBase+0x00)
	CAN master control register. More...

#define	_CAN_MSR _SFR(uint8_t, CAN_AddressBase+0x01)
	CAN master status register. More...

#define	_CAN_TSR _SFR(uint8_t, CAN_AddressBase+0x02)
	CAN transmit status register. More...

#define	_CAN_TPR _SFR(uint8_t, CAN_AddressBase+0x03)
	CAN transmit priority register. More...

#define	_CAN_RFR _SFR(uint8_t, CAN_AddressBase+0x04)
	CAN receive FIFO register. More...

#define	_CAN_IER _SFR(uint8_t, CAN_AddressBase+0x05)
	CAN interrupt enable register. More...

#define	_CAN_DGR _SFR(uint8_t, CAN_AddressBase+0x06)
	CAN diagnosis register. More...

#define	_CAN_PSR _SFR(uint8_t, CAN_AddressBase+0x07)
	CAN page selection for below paged registers. More...

#define	_CAN_MCSR _SFR(uint8_t, CAN_AddressBase+0x08+0x00)
	CAN message control/status register (page 0,1,5) More...

#define	_CAN_MDLCR _SFR(uint8_t, CAN_AddressBase+0x08+0x01)
	CAN mailbox data length control register (page 0,1,5,7) More...

#define	_CAN_MIDR1 _SFR(uint8_t, CAN_AddressBase+0x08+0x02)
	CAN mailbox identifier register 1 (page 0,1,5,7) More...

#define	_CAN_MIDR2 _SFR(uint8_t, CAN_AddressBase+0x08+0x03)
	CAN mailbox identifier register 2 (page 0,1,5,7) More...

#define	_CAN_MIDR3 _SFR(uint8_t, CAN_AddressBase+0x08+0x04)
	CAN mailbox identifier register 3 (page 0,1,5,7) More...

#define	_CAN_MIDR4 _SFR(uint8_t, CAN_AddressBase+0x08+0x05)
	CAN mailbox identifier register 4 (page 0,1,5,7) More...

#define	_CAN_MDAR1 _SFR(uint8_t, CAN_AddressBase+0x08+0x06)
	CAN mailbox data register 1 (page 0,1,5,7) */. More...

#define	_CAN_MDAR2 _SFR(uint8_t, CAN_AddressBase+0x08+0x07)
	CAN mailbox data register 2 (page 0,1,5,7) */. More...

#define	_CAN_MDAR3 _SFR(uint8_t, CAN_AddressBase+0x08+0x08)
	CAN mailbox data register 3 (page 0,1,5,7) */. More...

#define	_CAN_MDAR4 _SFR(uint8_t, CAN_AddressBase+0x08+0x09)
	CAN mailbox data register 4 (page 0,1,5,7) */. More...

#define	_CAN_MDAR5 _SFR(uint8_t, CAN_AddressBase+0x08+0x0A)
	CAN mailbox data register 5 (page 0,1,5,7) */. More...

#define	_CAN_MDAR6 _SFR(uint8_t, CAN_AddressBase+0x08+0x0B)
	CAN mailbox data register 6 (page 0,1,5,7) */. More...

#define	_CAN_MDAR7 _SFR(uint8_t, CAN_AddressBase+0x08+0x0C)
	CAN mailbox data register 7 (page 0,1,5,7) */. More...

#define	_CAN_MDAR8 _SFR(uint8_t, CAN_AddressBase+0x08+0x0D)
	CAN mailbox data register 8 (page 0,1,5,7) */. More...

#define	_CAN_MTSRL _SFR(uint8_t, CAN_AddressBase+0x08+0x0E)
	CAN mailbox time stamp register low byte (page 0,1,5,7) */. More...

#define	_CAN_MTSRH _SFR(uint8_t, CAN_AddressBase+0x08+0x0F)
	CAN mailbox time stamp register high byte (page 0,1,5,7) */. More...

#define	_CAN_F0R1 _SFR(uint8_t, CAN_AddressBase+0x08+0x00)
	CAN acceptance filter 0/1 (page 2) More...

#define	_CAN_F0R2 _SFR(uint8_t, CAN_AddressBase+0x08+0x01)
	CAN acceptance filter 0/2 (page 2) More...

#define	_CAN_F0R3 _SFR(uint8_t, CAN_AddressBase+0x08+0x02)
	CAN acceptance filter 0/3 (page 2) More...

#define	_CAN_F0R4 _SFR(uint8_t, CAN_AddressBase+0x08+0x03)
	CAN acceptance filter 0/4 (page 2) More...

#define	_CAN_F0R5 _SFR(uint8_t, CAN_AddressBase+0x08+0x04)
	CAN acceptance filter 0/5 (page 2) More...

#define	_CAN_F0R6 _SFR(uint8_t, CAN_AddressBase+0x08+0x05)
	CAN acceptance filter 0/6 (page 2) More...

#define	_CAN_F0R7 _SFR(uint8_t, CAN_AddressBase+0x08+0x06)
	CAN acceptance filter 0/7 (page 2) More...

#define	_CAN_F0R8 _SFR(uint8_t, CAN_AddressBase+0x08+0x07)
	CAN acceptance filter 0/8 (page 2) More...

#define	_CAN_F1R1 _SFR(uint8_t, CAN_AddressBase+0x08+0x08)
	CAN acceptance filter 1/1 (page 2) More...

#define	_CAN_F1R2 _SFR(uint8_t, CAN_AddressBase+0x08+0x09)
	CAN acceptance filter 1/2 (page 2) More...

#define	_CAN_F1R3 _SFR(uint8_t, CAN_AddressBase+0x08+0x0A)
	CAN acceptance filter 1/3 (page 2) More...

#define	_CAN_F1R4 _SFR(uint8_t, CAN_AddressBase+0x08+0x0B)
	CAN acceptance filter 1/4 (page 2) More...

#define	_CAN_F1R5 _SFR(uint8_t, CAN_AddressBase+0x08+0x0C)
	CAN acceptance filter 1/5 (page 2) More...

#define	_CAN_F1R6 _SFR(uint8_t, CAN_AddressBase+0x08+0x0D)
	CAN acceptance filter 1/6 (page 2) More...

#define	_CAN_F1R7 _SFR(uint8_t, CAN_AddressBase+0x08+0x0E)
	CAN acceptance filter 1/7 (page 2) More...

#define	_CAN_F1R8 _SFR(uint8_t, CAN_AddressBase+0x08+0x0F)
	CAN acceptance filter 1/8 (page 2) More...

#define	_CAN_F2R1 _SFR(uint8_t, CAN_AddressBase+0x08+0x00)
	CAN acceptance filter 2/1 (page 3) More...

#define	_CAN_F2R2 _SFR(uint8_t, CAN_AddressBase+0x08+0x01)
	CAN acceptance filter 2/2 (page 3) More...

#define	_CAN_F2R3 _SFR(uint8_t, CAN_AddressBase+0x08+0x02)
	CAN acceptance filter 2/3 (page 3) More...

#define	_CAN_F2R4 _SFR(uint8_t, CAN_AddressBase+0x08+0x03)
	CAN acceptance filter 2/4 (page 3) More...

#define	_CAN_F2R5 _SFR(uint8_t, CAN_AddressBase+0x08+0x04)
	CAN acceptance filter 2/5 (page 3) More...

#define	_CAN_F2R6 _SFR(uint8_t, CAN_AddressBase+0x08+0x05)
	CAN acceptance filter 2/6 (page 3) More...

#define	_CAN_F2R7 _SFR(uint8_t, CAN_AddressBase+0x08+0x06)
	CAN acceptance filter 2/7 (page 3) More...

#define	_CAN_F2R8 _SFR(uint8_t, CAN_AddressBase+0x08+0x07)
	CAN acceptance filter 2/8 (page 3) More...

#define	_CAN_F3R1 _SFR(uint8_t, CAN_AddressBase+0x08+0x08)
	CAN acceptance filter 3/1 (page 3) More...

#define	_CAN_F3R2 _SFR(uint8_t, CAN_AddressBase+0x08+0x09)
	CAN acceptance filter 3/2 (page 3) More...

#define	_CAN_F3R3 _SFR(uint8_t, CAN_AddressBase+0x08+0x0A)
	CAN acceptance filter 3/3 (page 3) More...

#define	_CAN_F3R4 _SFR(uint8_t, CAN_AddressBase+0x08+0x0B)
	CAN acceptance filter 3/4 (page 3) More...

#define	_CAN_F3R5 _SFR(uint8_t, CAN_AddressBase+0x08+0x0C)
	CAN acceptance filter 3/5 (page 3) More...

#define	_CAN_F3R6 _SFR(uint8_t, CAN_AddressBase+0x08+0x0D)
	CAN acceptance filter 3/6 (page 3) More...

#define	_CAN_F3R7 _SFR(uint8_t, CAN_AddressBase+0x08+0x0E)
	CAN acceptance filter 3/7 (page 3) More...

#define	_CAN_F3R8 _SFR(uint8_t, CAN_AddressBase+0x08+0x0F)
	CAN acceptance filter 3/8 (page 3) More...

#define	_CAN_F4R1 _SFR(uint8_t, CAN_AddressBase+0x08+0x00)
	CAN acceptance filter 4/1 (page 4) More...

#define	_CAN_F4R2 _SFR(uint8_t, CAN_AddressBase+0x08+0x01)
	CAN acceptance filter 4/2 (page 4) More...

#define	_CAN_F4R3 _SFR(uint8_t, CAN_AddressBase+0x08+0x02)
	CAN acceptance filter 4/3 (page 4) More...

#define	_CAN_F4R4 _SFR(uint8_t, CAN_AddressBase+0x08+0x03)
	CAN acceptance filter 4/4 (page 4) More...

#define	_CAN_F4R5 _SFR(uint8_t, CAN_AddressBase+0x08+0x04)
	CAN acceptance filter 4/5 (page 4) More...

#define	_CAN_F4R6 _SFR(uint8_t, CAN_AddressBase+0x08+0x05)
	CAN acceptance filter 4/6 (page 4) More...

#define	_CAN_F4R7 _SFR(uint8_t, CAN_AddressBase+0x08+0x06)
	CAN acceptance filter 4/7 (page 4) More...

#define	_CAN_F4R8 _SFR(uint8_t, CAN_AddressBase+0x08+0x07)
	CAN acceptance filter 4/8 (page 4) More...

#define	_CAN_F5R1 _SFR(uint8_t, CAN_AddressBase+0x08+0x08)
	CAN acceptance filter 5/1 (page 4) More...

#define	_CAN_F5R2 _SFR(uint8_t, CAN_AddressBase+0x08+0x09)
	CAN acceptance filter 5/2 (page 4) More...

#define	_CAN_F5R3 _SFR(uint8_t, CAN_AddressBase+0x08+0x0A)
	CAN acceptance filter 5/3 (page 4) More...

#define	_CAN_F5R4 _SFR(uint8_t, CAN_AddressBase+0x08+0x0B)
	CAN acceptance filter 5/4 (page 4) More...

#define	_CAN_F5R5 _SFR(uint8_t, CAN_AddressBase+0x08+0x0C)
	CAN acceptance filter 5/5 (page 4) More...

#define	_CAN_F5R6 _SFR(uint8_t, CAN_AddressBase+0x08+0x0D)
	CAN acceptance filter 5/6 (page 4) More...

#define	_CAN_F5R7 _SFR(uint8_t, CAN_AddressBase+0x08+0x0E)
	CAN acceptance filter 5/7 (page 4) More...

#define	_CAN_F5R8 _SFR(uint8_t, CAN_AddressBase+0x08+0x0F)
	CAN acceptance filter 5/8 (page 4) More...

#define	_CAN_ESR _SFR(uint8_t, CAN_AddressBase+0x08+0x00)
	CAN error status register (page 6) More...

#define	_CAN_EIER _SFR(uint8_t, CAN_AddressBase+0x08+0x01)
	CAN error interrupt enable register (page 6) More...

#define	_CAN_TECR _SFR(uint8_t, CAN_AddressBase+0x08+0x02)
	CAN transmit error counter register (page 6) More...

#define	_CAN_RECR _SFR(uint8_t, CAN_AddressBase+0x08+0x03)
	CAN receive error counter register (page 6) More...

#define	_CAN_BTR1 _SFR(uint8_t, CAN_AddressBase+0x08+0x04)
	CAN bit timing register 1 (page 6) More...

#define	_CAN_BTR2 _SFR(uint8_t, CAN_AddressBase+0x08+0x05)
	CAN bit timing register 2 (page 6) More...

#define	_CAN_FMR1 _SFR(uint8_t, CAN_AddressBase+0x08+0x08)
	CAN filter mode register 1 (page 6) More...

#define	_CAN_FMR2 _SFR(uint8_t, CAN_AddressBase+0x08+0x09)
	CAN filter mode register 2 (page 6) More...

#define	_CAN_FCR1 _SFR(uint8_t, CAN_AddressBase+0x08+0x0A)
	CAN filter configuration register 1 (page 6) More...

#define	_CAN_FCR2 _SFR(uint8_t, CAN_AddressBase+0x08+0x0B)
	CAN filter configuration register 2 (page 6) More...

#define	_CAN_FCR3 _SFR(uint8_t, CAN_AddressBase+0x08+0x0C)
	CAN filter configuration register 3 (page 6) More...

#define	_CAN_MFMIR _SFR(uint8_t, CAN_AddressBase+0x08+0x00)
	CAN mailbox filter match index register (page 7) More...

#define	_CAN_MCR_RESET_VALUE ((uint8_t) 0x02)
	CAN master control register reset value. More...

#define	_CAN_MSR_RESET_VALUE ((uint8_t) 0x02)
	CAN master status register reset value. More...

#define	_CAN_TSR_RESET_VALUE ((uint8_t) 0x00)
	CAN transmit status register reset value. More...

#define	_CAN_TPR_RESET_VALUE ((uint8_t) 0x0C)
	CAN transmit priority register reset value. More...

#define	_CAN_RFR_RESET_VALUE ((uint8_t) 0x00)
	CAN receive FIFO register reset value. More...

#define	_CAN_IER_RESET_VALUE ((uint8_t) 0x00)
	CAN interrupt enable register reset value. More...

#define	_CAN_DGR_RESET_VALUE ((uint8_t) 0x0C)
	CAN diagnosis register reset value. More...

#define	_CAN_PSR_RESET_VALUE ((uint8_t) 0x00)
	CAN page selection reset value. More...

#define	_CAN_MCSR_RESET_VALUE ((uint8_t) 0x00)
	CAN message control/status register (page 0,1,5) reset value. More...

#define	_CAN_MDLCR_RESET_VALUE ((uint8_t) 0x00)
	CAN mailbox data length control register (page 0,1,5,7) reset value. More...

#define	_CAN_ESR_RESET_VALUE ((uint8_t) 0x00)
	CAN error status register (page 6) reset value. More...

#define	_CAN_EIER_RESET_VALUE ((uint8_t) 0x00)
	CAN error interrupt enable register (page 6) reset value. More...

#define	_CAN_TECR_RESET_VALUE ((uint8_t) 0x00)
	CAN transmit error counter register (page 6) reset value. More...

#define	_CAN_RECR_RESET_VALUE ((uint8_t) 0x00)
	CAN receive error counter register (page 6) reset value. More...

#define	_CAN_BTR1_RESET_VALUE ((uint8_t) 0x40)
	CAN bit timing register 1 (page 6) reset value. More...

#define	_CAN_BTR2_RESET_VALUE ((uint8_t) 0x23)
	CAN bit timing register 2 (page 6) reset value. More...

#define	_CAN_FMR1_RESET_VALUE ((uint8_t) 0x00)
	CAN filter mode register 1 (page 6) reset value. More...

#define	_CAN_FMR2_RESET_VALUE ((uint8_t) 0x00)
	CAN filter mode register 2 (page 6) reset value. More...

#define	_CAN_FCR_RESET_VALUE ((uint8_t) 0x00)
	CAN filter configuration register reset value. More...

#define	_CAN_MFMIR_RESET_VALUE ((uint8_t) 0x00)
	CAN mailbox filter match index register reset value. More...

#define	_CAN_INRQ ((uint8_t) (0x01 << 0))
	CAN Channel Initialization Request [0] (in _CAN_MCR) More...

#define	_CAN_SLEEP ((uint8_t) (0x01 << 1))
	CAN Channel Sleep Mode Request [0] (in _CAN_MCR) More...

#define	_CAN_TXFP ((uint8_t) (0x01 << 2))
	CAN Channel Transmit FIFO Priority [0] (in _CAN_MCR) More...

#define	_CAN_RFLM ((uint8_t) (0x01 << 3))
	CAN Channel Receive FIFO Locked Mode [0] (in _CAN_MCR) More...

#define	_CAN_NART ((uint8_t) (0x01 << 4))
	CAN Channel No Automatic Retransmission [0] (in _CAN_MCR) More...

#define	_CAN_AWUM ((uint8_t) (0x01 << 5))
	CAN Channel Automatic Wakeup Mode [0] (in _CAN_MCR) More...

#define	_CAN_ABOM ((uint8_t) (0x01 << 6))
	CAN Channel Automatic Bus-Off Management [0] (in _CAN_MCR) More...

#define	_CAN_TTCM ((uint8_t) (0x01 << 7))
	CAN Channel Time Triggered Communication Mode [0] (in _CAN_MCR) More...

#define	_CAN_INAK ((uint8_t) (0x01 << 0))
	CAN Initialization Acknowledge [0] (in _CAN_MSR) More...

#define	_CAN_SLAK ((uint8_t) (0x01 << 1))
	CAN Sleep Acknowledge [0] (in _CAN_MSR) More...

#define	_CAN_ERRI ((uint8_t) (0x01 << 2))
	CAN Error Interrupt [0] (in _CAN_MSR) More...

#define	_CAN_WKUI ((uint8_t) (0x01 << 3))
	CAN Wakeup Interrupt [0] (in _CAN_MSR) More...

#define	_CAN_TX ((uint8_t) (0x01 << 4))
	CAN Transmit [0] (in _CAN_MSR) More...

#define	_CAN_RX ((uint8_t) (0x01 << 5))
	CAN Receive [0] (in _CAN_MSR) More...

#define	_CAN_RQCP0 ((uint8_t) (0x01 << 0))
	CAN Request Completed for Mailbox 0 [0] (in _CAN_TSR) More...

#define	_CAN_RQCP1 ((uint8_t) (0x01 << 1))
	CAN Request Completed for Mailbox 1 [0] (in _CAN_TSR) More...

#define	_CAN_RQCP2 ((uint8_t) (0x01 << 2))
	CAN Request Completed for Mailbox 2 [0] (in _CAN_TSR) More...

#define	_CAN_TXOK0 ((uint8_t) (0x01 << 4))
	CAN Transmission ok for Mailbox 0 [0] (in _CAN_TSR) More...

#define	_CAN_TXOK1 ((uint8_t) (0x01 << 5))
	CAN Transmission ok for Mailbox 1 [0] (in _CAN_TSR) More...

#define	_CAN_TXOK2 ((uint8_t) (0x01 << 6))
	CAN Transmission ok for Mailbox 2 [0] (in _CAN_TSR) More...

#define	_CAN_CODE ((uint8_t) (0x03 << 0))
	CAN Mailbox Code [1:0] (in _CAN_TPR) More...

#define	_CAN_CODE0 ((uint8_t) (0x01 << 0))
	CAN Mailbox Code [0] (in _CAN_TPR) More...

#define	_CAN_CODE1 ((uint8_t) (0x01 << 1))
	CAN Mailbox Code [1] (in _CAN_TPR) More...

#define	_CAN_TME0 ((uint8_t) (0x01 << 2))
	CAN Transmit Mailbox 0 Empty [0] (in _CAN_TPR) More...

#define	_CAN_TME1 ((uint8_t) (0x01 << 3))
	CAN Transmit Mailbox 1 Empty [0] (in _CAN_TPR) More...

#define	_CAN_TME2 ((uint8_t) (0x01 << 4))
	CAN Transmit Mailbox 2 Empty [0] (in _CAN_TPR) More...

#define	_CAN_LOW0 ((uint8_t) (0x01 << 5))
	CAN Lowest Priority Flag for Mailbox 0 [0] (in _CAN_TPR) More...

#define	_CAN_LOW1 ((uint8_t) (0x01 << 6))
	CAN Lowest Priority Flag for Mailbox 1 [0] (in _CAN_TPR) More...

#define	_CAN_LOW2 ((uint8_t) (0x01 << 7))
	CAN Lowest Priority Flag for Mailbox 2 [0] (in _CAN_TPR) More...

#define	_CAN_FMP ((uint8_t) (0x03 << 0))
	CAN FIFO Message Pending [1:0] (in _CAN_RFR) More...

#define	_CAN_FMP0 ((uint8_t) (0x01 << 0))
	CAN FIFO Message Pending [0] (in _CAN_RFR) More...

#define	_CAN_FMP1 ((uint8_t) (0x01 << 1))
	CAN FIFO Message Pending [1] (in _CAN_RFR) More...

#define	_CAN_FULL ((uint8_t) (0x01 << 3))
	CAN FIFO Full [0] (in _CAN_RFR) More...

#define	_CAN_FOVR ((uint8_t) (0x01 << 4))
	CAN FIFO Overrun [0] (in _CAN_RFR) More...

#define	_CAN_RFOM ((uint8_t) (0x01 << 5))
	CAN Release FIFO Output Mailbox [0] (in _CAN_RFR) More...

#define	_CAN_TMEIE ((uint8_t) (0x01 << 0))
	CAN Transmit Mailbox Empty Interrupt Enable [0] (in _CAN_IER) More...

#define	_CAN_FMPIE ((uint8_t) (0x01 << 1))
	CAN FIFO Message Pending Interrupt Enable [0] (in _CAN_IER) More...

#define	_CAN_FFIE ((uint8_t) (0x01 << 2))
	CAN FIFO Full Interrupt Enable [0] (in _CAN_IER) More...

#define	_CAN_FOVIE ((uint8_t) (0x01 << 3))
	CAN FIFO Overrun Interrupt Enable [0] (in _CAN_IER) More...

#define	_CAN_WKUIE ((uint8_t) (0x01 << 7))
	CAN Wakeup Interrupt Enable [0] (in _CAN_IER) More...

#define	_CAN_LBKM ((uint8_t) (0x01 << 0))
	CAN Loop back mode [0] (in _CAN_DGR) More...

#define	_CAN_SILM ((uint8_t) (0x01 << 1))
	CAN Silent mode [0] (in _CAN_DGR) More...

#define	_CAN_SAMP ((uint8_t) (0x01 << 2))
	CAN Last sample point [0] (in _CAN_DGR) More...

#define	_CAN_RXS ((uint8_t) (0x01 << 3))
	CAN Rx Signal (=pin status) [0] (in _CAN_DGR) More...

#define	_CAN_TXM2E ((uint8_t) (0x01 << 4))
	CAN TX Mailbox 2 enable [0] (in _CAN_DGR) More...

#define	_CAN_PS ((uint8_t) (0x07 << 0))
	CAN Page select [2:0] (in _CAN_PSR) More...

#define	_CAN_PS0 ((uint8_t) (0x01 << 0))
	CAN Page select [0] (in _CAN_PSR) More...

#define	_CAN_PS1 ((uint8_t) (0x01 << 1))
	CAN Page select [1] (in _CAN_PSR) More...

#define	_CAN_PS2 ((uint8_t) (0x01 << 2))
	CAN Page select [2] (in _CAN_PSR) More...

#define	_CAN_TXRQ ((uint8_t) (0x01 << 0))
	CAN Transmission mailbox request [0] (in _CAN_MCSR, page 0,1,5) More...

#define	_CAN_ABRQ ((uint8_t) (0x01 << 1))
	CAN Abort request for mailbox [0] (in _CAN_MCSR, page 0,1,5) More...

#define	_CAN_RQCP ((uint8_t) (0x01 << 2))
	CAN Request completed [0] (in _CAN_MCSR, page 0,1,5) More...

#define	_CAN_TXOK ((uint8_t) (0x01 << 3))
	CAN Transmission OK [0] (in _CAN_MCSR, page 0,1,5) More...

#define	_CAN_ALST ((uint8_t) (0x01 << 4))
	CAN Arbitration lost [0] (in _CAN_MCSR, page 0,1,5) More...

#define	_CAN_TERR ((uint8_t) (0x01 << 5))
	CAN Transmission error [0] (in _CAN_MCSR, page 0,1,5) More...

#define	_CAN_DLC ((uint8_t) (0x0F << 0))
	CAN Data length code [3:0] (in _CAN_MDLCR, page 0,1,5,7) More...

#define	_CAN_DLC0 ((uint8_t) (0x01 << 0))
	CAN Data length code [0] (in _CAN_MDLCR, page 0,1,5,7) More...

#define	_CAN_DLC1 ((uint8_t) (0x01 << 1))
	CAN Data length code [1] (in _CAN_MDLCR, page 0,1,5,7) More...

#define	_CAN_DLC2 ((uint8_t) (0x01 << 2))
	CAN Data length code [2] (in _CAN_MDLCR, page 0,1,5,7) More...

#define	_CAN_DLC3 ((uint8_t) (0x01 << 3))
	CAN Data length code [3] (in _CAN_MDLCR, page 0,1,5,7) More...

#define	_CAN_TGT ((uint8_t) (0x01 << 7))
	CAN Transmit global time [0] (in _CAN_MDLCR, page 0,1,5,7) More...

#define	_CAN_RTR ((uint8_t) (0x01 << 5))
	CAN Remote transmission request [0] (in _CAN_MIDR1, page 0,1,5) More...

#define	_CAN_IDE ((uint8_t) (0x01 << 6))
	CAN Extended identifier [0] (in _CAN_MIDR1, page 0,1,5) More...

#define	_CAN_EWGF ((uint8_t) (0x01 << 0))
	CAN Error warning flag [0] (in _CAN_ESR, page 6) More...

#define	_CAN_EPVF ((uint8_t) (0x01 << 1))
	CAN Error passive flag [0] (in _CAN_ESR, page 6) More...

#define	_CAN_BOFF ((uint8_t) (0x01 << 2))
	CAN Bus off flag [0] (in _CAN_ESR, page 6) More...

#define	_CAN_LEC ((uint8_t) (0x07 << 4))
	CAN Last error code [2:0] (in _CAN_ESR, page 6) More...

#define	_CAN_LEC0 ((uint8_t) (0x01 << 4))
	CAN Last error code [0] (in _CAN_ESR, page 6) More...

#define	_CAN_LEC1 ((uint8_t) (0x01 << 5))
	CAN Last error code [1] (in _CAN_ESR, page 6) More...

#define	_CAN_LEC2 ((uint8_t) (0x01 << 6))
	CAN Last error code [3] (in _CAN_ESR, page 6) More...

#define	_CAN_EWGIE ((uint8_t) (0x01 << 0))
	CAN Error warning interrupt enable [0] (in _CAN_EIER, page 6) More...

#define	_CAN_EPVIE ((uint8_t) (0x01 << 1))
	CAN Error passive interrupt enable [0] (in _CAN_EIER, page 6) More...

#define	_CAN_BOFIE ((uint8_t) (0x01 << 2))
	CAN Bus-Off interrupt enable [0] (in _CAN_EIER, page 6) More...

#define	_CAN_LECIE ((uint8_t) (0x01 << 4))
	CAN Last error code interrupt enable [0] (in _CAN_EIER, page 6) More...

#define	_CAN_ERRIE ((uint8_t) (0x01 << 6))
	CAN Error interrupt enable [0] (in _CAN_EIER, page 6) More...

#define	_CAN_BRP ((uint8_t) (0x3F << 0))
	CAN Baud rate prescaler [5:0] (in _CAN_BTR1, page 6) More...

#define	_CAN_BRP0 ((uint8_t) (0x01 << 0))
	CAN Baud rate prescaler [0] (in _CAN_BTR1, page 6) More...

#define	_CAN_BRP1 ((uint8_t) (0x01 << 1))
	CAN Baud rate prescaler [1] (in _CAN_BTR1, page 6) More...

#define	_CAN_BRP2 ((uint8_t) (0x01 << 2))
	CAN Baud rate prescaler [2] (in _CAN_BTR1, page 6) More...

#define	_CAN_BRP3 ((uint8_t) (0x01 << 3))
	CAN Baud rate prescaler [3] (in _CAN_BTR1, page 6) More...

#define	_CAN_BRP4 ((uint8_t) (0x01 << 4))
	CAN Baud rate prescaler [4] (in _CAN_BTR1, page 6) More...

#define	_CAN_BRP5 ((uint8_t) (0x01 << 5))
	CAN Baud rate prescaler [5] (in _CAN_BTR1, page 6) More...

#define	_CAN_SJW ((uint8_t) (0x03 << 6))
	CAN Resynchronization jump width [1:0] (in _CAN_EIER, page 6) More...

#define	_CAN_SJW0 ((uint8_t) (0x01 << 6))
	CAN Resynchronization jump width [0] (in _CAN_EIER, page 6) More...

#define	_CAN_SJW1 ((uint8_t) (0x01 << 7))
	CAN Resynchronization jump width [1] (in _CAN_EIER, page 6) More...

#define	_CAN_BS1 ((uint8_t) (0x0F << 0))
	CAN Bit segment 1 [3:0] (in _CAN_BTR2, page 6) More...

#define	_CAN_BS10 ((uint8_t) (0x01 << 0))
	CAN Bit segment 1 [0] (in _CAN_BTR2, page 6) More...

#define	_CAN_BS11 ((uint8_t) (0x01 << 1))
	CAN Bit segment 1 [1] (in _CAN_BTR2, page 6) More...

#define	_CAN_BS12 ((uint8_t) (0x01 << 2))
	CAN Bit segment 1 [2] (in _CAN_BTR2, page 6) More...

#define	_CAN_BS13 ((uint8_t) (0x01 << 3))
	CAN Bit segment 1 [3] (in _CAN_BTR2, page 6) More...

#define	_CAN_BS2 ((uint8_t) (0x07 << 4))
	CAN Bit segment 2 [2:0] (in _CAN_BTR2, page 6) More...

#define	_CAN_BS20 ((uint8_t) (0x01 << 4))
	CAN Bit segment 2 [0] (in _CAN_BTR2, page 6) More...

#define	_CAN_BS21 ((uint8_t) (0x01 << 5))
	CAN Bit segment 2 [1] (in _CAN_BTR2, page 6) More...

#define	_CAN_BS22 ((uint8_t) (0x01 << 6))
	CAN Bit segment 2 [2] (in _CAN_BTR2, page 6) More...

#define	_CAN_FML0 ((uint8_t) (0x01 << 0))
	CAN Filter 0 mode low [0] (in _CAN_FMR1, page 6) More...

#define	_CAN_FMH0 ((uint8_t) (0x01 << 1))
	CAN Filter 0 mode high [0] (in _CAN_FMR1, page 6) More...

#define	_CAN_FML1 ((uint8_t) (0x01 << 2))
	CAN Filter 1 mode low [0] (in _CAN_FMR1, page 6) More...

#define	_CAN_FMH1 ((uint8_t) (0x01 << 3))
	CAN Filter 1 mode high [0] (in _CAN_FMR1, page 6) More...

#define	_CAN_FML2 ((uint8_t) (0x01 << 4))
	CAN Filter 2 mode low [0] (in _CAN_FMR1, page 6) More...

#define	_CAN_FMH2 ((uint8_t) (0x01 << 5))
	CAN Filter 2 mode high [0] (in _CAN_FMR1, page 6) More...

#define	_CAN_FML3 ((uint8_t) (0x01 << 6))
	CAN Filter 3 mode low [0] (in _CAN_FMR1, page 6) More...

#define	_CAN_FMH3 ((uint8_t) (0x01 << 7))
	CAN Filter 3 mode high [0] (in _CAN_FMR1, page 6) More...

#define	_CAN_FML4 ((uint8_t) (0x01 << 0))
	CAN Filter 4 mode low [0] (in _CAN_FMR2, page 6) More...

#define	_CAN_FMH4 ((uint8_t) (0x01 << 1))
	CAN Filter 4 mode high [0] (in _CAN_FMR2, page 6) More...

#define	_CAN_FML5 ((uint8_t) (0x01 << 2))
	CAN Filter 5 mode low [0] (in _CAN_FMR2, page 6) More...

#define	_CAN_FMH5 ((uint8_t) (0x01 << 3))
	CAN Filter 5 mode high [0] (in _CAN_FMR2, page 6) More...

#define	_CAN_FACT0 ((uint8_t) (0x01 << 0))
	CAN Filter 0 active [0] (in _CAN_FCR1, page 6) More...

#define	_CAN_FSC0 ((uint8_t) (0x03 << 1))
	CAN Filter 0 scale configuration [1:0] (in _CAN_FCR1, page 6) More...

#define	_CAN_FSC00 ((uint8_t) (0x01 << 1))
	CAN Filter 0 scale configuration [0] (in _CAN_FCR1, page 6) More...

#define	_CAN_FSC01 ((uint8_t) (0x01 << 2))
	CAN Filter 0 scale configuration [1] (in _CAN_FCR1, page 6) More...

#define	_CAN_FACT1 ((uint8_t) (0x01 << 4))
	CAN Filter 1 active [0] (in _CAN_FCR1, page 6) More...

#define	_CAN_FSC1 ((uint8_t) (0x03 << 5))
	CAN Filter 1 scale configuration [1:0] (in _CAN_FCR1, page 6) More...

#define	_CAN_FSC10 ((uint8_t) (0x01 << 5))
	CAN Filter 1 scale configuration [0] (in _CAN_FCR1, page 6) More...

#define	_CAN_FSC11 ((uint8_t) (0x01 << 6))
	CAN Filter 1 scale configuration [1] (in _CAN_FCR1, page 6) More...

#define	_CAN_FACT2 ((uint8_t) (0x01 << 0))
	CAN Filter 2 active [0] (in _CAN_FCR2, page 6) More...

#define	_CAN_FSC2 ((uint8_t) (0x03 << 1))
	CAN Filter 2 scale configuration [1:0] (in _CAN_FCR2, page 6) More...

#define	_CAN_FSC20 ((uint8_t) (0x01 << 1))
	CAN Filter 2 scale configuration [0] (in _CAN_FCR2, page 6) More...

#define	_CAN_FSC21 ((uint8_t) (0x01 << 2))
	CAN Filter 2 scale configuration [1] (in _CAN_FCR2, page 6) More...

#define	_CAN_FACT3 ((uint8_t) (0x01 << 4))
	CAN Filter 3 active [0] (in _CAN_FCR2, page 6) More...

#define	_CAN_FSC3 ((uint8_t) (0x03 << 5))
	CAN Filter 3 scale configuration [1:0] (in _CAN_FCR2, page 6) More...

#define	_CAN_FSC30 ((uint8_t) (0x01 << 5))
	CAN Filter 3 scale configuration [0] (in _CAN_FCR2, page 6) More...

#define	_CAN_FSC31 ((uint8_t) (0x01 << 6))
	CAN Filter 3 scale configuration [1] (in _CAN_FCR2, page 6) More...

#define	_CAN_FACT4 ((uint8_t) (0x01 << 0))
	CAN Filter 4 active [0] (in _CAN_FCR3, page 6) More...

#define	_CAN_FSC4 ((uint8_t) (0x03 << 1))
	CAN Filter 4 scale configuration [1:0] (in _CAN_FCR3, page 6) More...

#define	_CAN_FSC40 ((uint8_t) (0x01 << 1))
	CAN Filter 4 scale configuration [0] (in _CAN_FCR3, page 6) More...

#define	_CAN_FSC41 ((uint8_t) (0x01 << 2))
	CAN Filter 4 scale configuration [1] (in _CAN_FCR3, page 6) More...

#define	_CAN_FACT5 ((uint8_t) (0x01 << 4))
	CAN Filter 5 active [0] (in _CAN_FCR2, page 6) More...

#define	_CAN_FSC5 ((uint8_t) (0x03 << 5))
	CAN Filter 5 scale configuration [1:0] (in _CAN_FCR3, page 6) More...

#define	_CAN_FSC50 ((uint8_t) (0x01 << 5))
	CAN Filter 5 scale configuration [0] (in _CAN_FCR3, page 6) More...

#define	_CAN_FSC51 ((uint8_t) (0x01 << 6))
	CAN Filter 5 scale configuration [1] (in _CAN_FCR3, page 6) More...

#define	_CFG _SFR(CFG_t, CFG_AddressBase)
	CFG struct/bit access. More...

#define	_CFG_GCR _SFR(uint8_t, CFG_AddressBase+0x00)
	Global configuration register (CFG_GCR) More...

#define	_CFG_GCR_RESET_VALUE ((uint8_t)0x00)

#define	_CFG_SWD ((uint8_t) (0x01 << 0))
	SWIM disable [0]. More...

#define	_CFG_AL ((uint8_t) (0x01 << 1))
	Activation level [0]. More...

#define	_ITC _SFR(ITC_t, ITC_AddressBase)
	ITC struct/bit access. More...

#define	_ITC_SPR1 _SFR(uint8_t, ITC_AddressBase+0x00)
	Interrupt priority register 1/8. More...

#define	_ITC_SPR2 _SFR(uint8_t, ITC_AddressBase+0x01)
	Interrupt priority register 2/8. More...

#define	_ITC_SPR3 _SFR(uint8_t, ITC_AddressBase+0x02)
	Interrupt priority register 3/8. More...

#define	_ITC_SPR4 _SFR(uint8_t, ITC_AddressBase+0x03)
	Interrupt priority register 4/8. More...

#define	_ITC_SPR5 _SFR(uint8_t, ITC_AddressBase+0x04)
	Interrupt priority register 5/8. More...

#define	_ITC_SPR6 _SFR(uint8_t, ITC_AddressBase+0x05)
	Interrupt priority register 6/8. More...

#define	_ITC_SPR7 _SFR(uint8_t, ITC_AddressBase+0x06)
	Interrupt priority register 7/8. More...

#define	_ITC_SPR8 _SFR(uint8_t, ITC_AddressBase+0x07)
	Interrupt priority register 8/8. More...

#define	_ITC_SPR1_RESET_VALUE ((uint8_t) 0xFF)
	Interrupt priority register 1/8 reset value. More...

#define	_ITC_SPR2_RESET_VALUE ((uint8_t) 0xFF)
	Interrupt priority register 2/8 reset value. More...

#define	_ITC_SPR3_RESET_VALUE ((uint8_t) 0xFF)
	Interrupt priority register 3/8 reset value. More...

#define	_ITC_SPR4_RESET_VALUE ((uint8_t) 0xFF)
	Interrupt priority register 4/8 reset value. More...

#define	_ITC_SPR5_RESET_VALUE ((uint8_t) 0xFF)
	Interrupt priority register 5/8 reset value. More...

#define	_ITC_SPR6_RESET_VALUE ((uint8_t) 0xFF)
	Interrupt priority register 6/8 reset value. More...

#define	_ITC_SPR7_RESET_VALUE ((uint8_t) 0xFF)
	Interrupt priority register 7/8 reset value. More...

#define	_ITC_SPR8_RESET_VALUE ((uint8_t) 0x0F)
	Interrupt priority register 8/8 reset value. More...

#define	_ITC_VECT1SPR ((uint8_t) (0x03 << 2))
	ITC interrupt priority vector 1 [1:0] (in _ITC_SPR1) More...

#define	_ITC_VECT1SPR0 ((uint8_t) (0x01 << 2))
	ITC interrupt priority vector 1 [0] (in _ITC_SPR1) More...

#define	_ITC_VECT1SPR1 ((uint8_t) (0x01 << 3))
	ITC interrupt priority vector 1 [1] (in _ITC_SPR1) More...

#define	_ITC_VECT2SPR ((uint8_t) (0x03 << 4))
	ITC interrupt priority vector 2 [1:0] (in _ITC_SPR1) More...

#define	_ITC_VECT2SPR0 ((uint8_t) (0x01 << 4))
	ITC interrupt priority vector 2 [0] (in _ITC_SPR1) More...

#define	_ITC_VECT2SPR1 ((uint8_t) (0x01 << 5))
	ITC interrupt priority vector 2 [1] (in _ITC_SPR1) More...

#define	_ITC_VECT3SPR ((uint8_t) (0x03 << 6))
	ITC interrupt priority vector 3 [1:0] (in _ITC_SPR1) More...

#define	_ITC_VECT3SPR0 ((uint8_t) (0x01 << 6))
	ITC interrupt priority vector 3 [0] (in _ITC_SPR1) More...

#define	_ITC_VECT3SPR1 ((uint8_t) (0x01 << 7))
	ITC interrupt priority vector 3 [1] (in _ITC_SPR1) More...

#define	_ITC_VECT4SPR ((uint8_t) (0x03 << 0))
	ITC interrupt priority vector 4 [1:0] (in _ITC_SPR2) More...

#define	_ITC_VECT4SPR0 ((uint8_t) (0x01 << 0))
	ITC interrupt priority vector 4 [0] (in _ITC_SPR2) More...

#define	_ITC_VECT4SPR1 ((uint8_t) (0x01 << 1))
	ITC interrupt priority vector 4 [1] (in _ITC_SPR2) More...

#define	_ITC_VECT5SPR ((uint8_t) (0x03 << 2))
	ITC interrupt priority vector 5 [1:0] (in _ITC_SPR2) More...

#define	_ITC_VECT5SPR0 ((uint8_t) (0x01 << 2))
	ITC interrupt priority vector 5 [0] (in _ITC_SPR2) More...

#define	_ITC_VECT5SPR1 ((uint8_t) (0x01 << 3))
	ITC interrupt priority vector 5 [1] (in _ITC_SPR2) More...

#define	_ITC_VECT6SPR ((uint8_t) (0x03 << 4))
	ITC interrupt priority vector 6 [1:0] (in _ITC_SPR2) More...

#define	_ITC_VECT6SPR0 ((uint8_t) (0x01 << 4))
	ITC interrupt priority vector 6 [0] (in _ITC_SPR2) More...

#define	_ITC_VECT6SPR1 ((uint8_t) (0x01 << 5))
	ITC interrupt priority vector 6 [1] (in _ITC_SPR2) More...

#define	_ITC_VECT7SPR ((uint8_t) (0x03 << 6))
	ITC interrupt priority vector 7 [1:0] (in _ITC_SPR2) More...

#define	_ITC_VECT7SPR0 ((uint8_t) (0x01 << 6))
	ITC interrupt priority vector 7 [0] (in _ITC_SPR2) More...

#define	_ITC_VECT7SPR1 ((uint8_t) (0x01 << 7))
	ITC interrupt priority vector 7 [1] (in _ITC_SPR2) More...

#define	_ITC_VECT8SPR ((uint8_t) (0x03 << 0))
	ITC interrupt priority vector 8 [1:0] (in _ITC_SPR3) More...

#define	_ITC_VECT8SPR0 ((uint8_t) (0x01 << 0))
	ITC interrupt priority vector 8 [0] (in _ITC_SPR3) More...

#define	_ITC_VECT8SPR1 ((uint8_t) (0x01 << 1))
	ITC interrupt priority vector 8 [1] (in _ITC_SPR3) More...

#define	_ITC_VECT9SPR ((uint8_t) (0x03 << 2))
	ITC interrupt priority vector 9 [1:0] (in _ITC_SPR3) More...

#define	_ITC_VECT9SPR0 ((uint8_t) (0x01 << 2))
	ITC interrupt priority vector 9 [0] (in _ITC_SPR3) More...

#define	_ITC_VECT9SPR1 ((uint8_t) (0x01 << 3))
	ITC interrupt priority vector 9 [1] (in _ITC_SPR3) More...

#define	_ITC_VECT10SPR ((uint8_t) (0x03 << 4))
	ITC interrupt priority vector 10 [1:0] (in _ITC_SPR3) More...

#define	_ITC_VECT10SPR0 ((uint8_t) (0x01 << 4))
	ITC interrupt priority vector 10 [0] (in _ITC_SPR3) More...

#define	_ITC_VECT10SPR1 ((uint8_t) (0x01 << 5))
	ITC interrupt priority vector 10 [1] (in _ITC_SPR3) More...

#define	_ITC_VECT11SPR ((uint8_t) (0x03 << 6))
	ITC interrupt priority vector 11 [1:0] (in _ITC_SPR3) More...

#define	_ITC_VECT11SPR0 ((uint8_t) (0x01 << 6))
	ITC interrupt priority vector 11 [0] (in _ITC_SPR3) More...

#define	_ITC_VECT11SPR1 ((uint8_t) (0x01 << 7))
	ITC interrupt priority vector 11 [1] (in _ITC_SPR3) More...

#define	_ITC_VECT12SPR ((uint8_t) (0x03 << 0))
	ITC interrupt priority vector 12 [1:0] (in _ITC_SPR4) More...

#define	_ITC_VECT12SPR0 ((uint8_t) (0x01 << 0))
	ITC interrupt priority vector 12 [0] (in _ITC_SPR4) More...

#define	_ITC_VECT12SPR1 ((uint8_t) (0x01 << 1))
	ITC interrupt priority vector 12 [1] (in _ITC_SPR4) More...

#define	_ITC_VECT13SPR ((uint8_t) (0x03 << 2))
	ITC interrupt priority vector 13 [1:0] (in _ITC_SPR4) More...

#define	_ITC_VECT13SPR0 ((uint8_t) (0x01 << 2))
	ITC interrupt priority vector 13 [0] (in _ITC_SPR4) More...

#define	_ITC_VECT13SPR1 ((uint8_t) (0x01 << 3))
	ITC interrupt priority vector 13 [1] (in _ITC_SPR4) More...

#define	_ITC_VECT14SPR ((uint8_t) (0x03 << 4))
	ITC interrupt priority vector 14 [1:0] (in _ITC_SPR4) More...

#define	_ITC_VECT14SPR0 ((uint8_t) (0x01 << 4))
	ITC interrupt priority vector 14 [0] (in _ITC_SPR4) More...

#define	_ITC_VECT14SPR1 ((uint8_t) (0x01 << 5))
	ITC interrupt priority vector 14 [1] (in _ITC_SPR4) More...

#define	_ITC_VECT15SPR ((uint8_t) (0x03 << 6))
	ITC interrupt priority vector 15 [1:0] (in _ITC_SPR4) More...

#define	_ITC_VECT15SPR0 ((uint8_t) (0x01 << 6))
	ITC interrupt priority vector 15 [0] (in _ITC_SPR4) More...

#define	_ITC_VECT15SPR1 ((uint8_t) (0x01 << 7))
	ITC interrupt priority vector 15 [1] (in _ITC_SPR4) More...

#define	_ITC_VECT16SPR ((uint8_t) (0x03 << 0))
	ITC interrupt priority vector 16 [1:0] (in _ITC_SPR5) More...

#define	_ITC_VECT16SPR0 ((uint8_t) (0x01 << 0))
	ITC interrupt priority vector 16 [0] (in _ITC_SPR5) More...

#define	_ITC_VECT16SPR1 ((uint8_t) (0x01 << 1))
	ITC interrupt priority vector 16 [1] (in _ITC_SPR5) More...

#define	_ITC_VECT17SPR ((uint8_t) (0x03 << 2))
	ITC interrupt priority vector 17 [1:0] (in _ITC_SPR5) More...

#define	_ITC_VECT17SPR0 ((uint8_t) (0x01 << 2))
	ITC interrupt priority vector 17 [0] (in _ITC_SPR5) More...

#define	_ITC_VECT17SPR1 ((uint8_t) (0x01 << 3))
	ITC interrupt priority vector 17 [1] (in _ITC_SPR5) More...

#define	_ITC_VECT18SPR ((uint8_t) (0x03 << 4))
	ITC interrupt priority vector 18 [1:0] (in _ITC_SPR5) More...

#define	_ITC_VECT18SPR0 ((uint8_t) (0x01 << 4))
	ITC interrupt priority vector 18 [0] (in _ITC_SPR5) More...

#define	_ITC_VECT18SPR1 ((uint8_t) (0x01 << 5))
	ITC interrupt priority vector 18 [1] (in _ITC_SPR5) More...

#define	_ITC_VECT19SPR ((uint8_t) (0x03 << 6))
	ITC interrupt priority vector 19 [1:0] (in _ITC_SPR5) More...

#define	_ITC_VECT19SPR0 ((uint8_t) (0x01 << 6))
	ITC interrupt priority vector 19 [0] (in _ITC_SPR5) More...

#define	_ITC_VECT19SPR1 ((uint8_t) (0x01 << 7))
	ITC interrupt priority vector 19 [1] (in _ITC_SPR5) More...

#define	_ITC_VECT20SPR ((uint8_t) (0x03 << 0))
	ITC interrupt priority vector 20 [1:0] (in _ITC_SPR6) More...

#define	_ITC_VECT20SPR0 ((uint8_t) (0x01 << 0))
	ITC interrupt priority vector 20 [0] (in _ITC_SPR6) More...

#define	_ITC_VECT20SPR1 ((uint8_t) (0x01 << 1))
	ITC interrupt priority vector 20 [1] (in _ITC_SPR6) More...

#define	_ITC_VECT21SPR ((uint8_t) (0x03 << 2))
	ITC interrupt priority vector 21 [1:0] (in _ITC_SPR6) More...

#define	_ITC_VECT21SPR0 ((uint8_t) (0x01 << 2))
	ITC interrupt priority vector 21 [0] (in _ITC_SPR6) More...

#define	_ITC_VECT21SPR1 ((uint8_t) (0x01 << 3))
	ITC interrupt priority vector 21 [1] (in _ITC_SPR6) More...

#define	_ITC_VECT22SPR ((uint8_t) (0x03 << 4))
	ITC interrupt priority vector 22 [1:0] (in _ITC_SPR6) More...

#define	_ITC_VECT22SPR0 ((uint8_t) (0x01 << 4))
	ITC interrupt priority vector 22 [0] (in _ITC_SPR6) More...

#define	_ITC_VECT22SPR1 ((uint8_t) (0x01 << 5))
	ITC interrupt priority vector 22 [1] (in _ITC_SPR6) More...

#define	_ITC_VECT23SPR ((uint8_t) (0x03 << 6))
	ITC interrupt priority vector 23 [1:0] (in _ITC_SPR6) More...

#define	_ITC_VECT23SPR0 ((uint8_t) (0x01 << 6))
	ITC interrupt priority vector 23 [0] (in _ITC_SPR6) More...

#define	_ITC_VECT23SPR1 ((uint8_t) (0x01 << 7))
	ITC interrupt priority vector 23 [1] (in _ITC_SPR6) More...

#define	_ITC_VECT24SPR ((uint8_t) (0x03 << 0))
	ITC interrupt priority vector 24 [1:0] (in _ITC_SPR7) More...

#define	_ITC_VECT24SPR0 ((uint8_t) (0x01 << 0))
	ITC interrupt priority vector 24 [0] (in _ITC_SPR7) More...

#define	_ITC_VECT24SPR1 ((uint8_t) (0x01 << 1))
	ITC interrupt priority vector 24 [1] (in _ITC_SPR7) More...

#define	_ITC_VECT25SPR ((uint8_t) (0x03 << 2))
	ITC interrupt priority vector 25 [1:0] (in _ITC_SPR7) More...

#define	_ITC_VECT25SPR0 ((uint8_t) (0x01 << 2))
	ITC interrupt priority vector 25 [0] (in _ITC_SPR7) More...

#define	_ITC_VECT25SPR1 ((uint8_t) (0x01 << 3))
	ITC interrupt priority vector 25 [1] (in _ITC_SPR7) More...

#define	_ITC_VECT26SPR ((uint8_t) (0x03 << 4))
	ITC interrupt priority vector 26 [1:0] (in _ITC_SPR7) More...

#define	_ITC_VECT26SPR0 ((uint8_t) (0x01 << 4))
	ITC interrupt priority vector 26 [0] (in _ITC_SPR7) More...

#define	_ITC_VECT26SPR1 ((uint8_t) (0x01 << 5))
	ITC interrupt priority vector 26 [1] (in _ITC_SPR7) More...

#define	_ITC_VECT27SPR ((uint8_t) (0x03 << 6))
	ITC interrupt priority vector 27 [1:0] (in _ITC_SPR7) More...

#define	_ITC_VECT27SPR0 ((uint8_t) (0x01 << 6))
	ITC interrupt priority vector 27 [0] (in _ITC_SPR7) More...

#define	_ITC_VECT27SPR1 ((uint8_t) (0x01 << 7))
	ITC interrupt priority vector 27 [1] (in _ITC_SPR7) More...

#define	_ITC_VECT28SPR ((uint8_t) (0x03 << 0))
	ITC interrupt priority vector 28 [1:0] (in _ITC_SPR8) More...

#define	_ITC_VECT28SPR0 ((uint8_t) (0x01 << 0))
	ITC interrupt priority vector 28 [0] (in _ITC_SPR8) More...

#define	_ITC_VECT28SPR1 ((uint8_t) (0x01 << 1))
	ITC interrupt priority vector 28 [1] (in _ITC_SPR8) More...

#define	_ITC_VECT29SPR ((uint8_t) (0x03 << 2))
	ITC interrupt priority vector 29 [1:0] (in _ITC_SPR8) More...

#define	_ITC_VECT29SPR0 ((uint8_t) (0x01 << 2))
	ITC interrupt priority vector 29 [0] (in _ITC_SPR8) More...

#define	_ITC_VECT29SPR1 ((uint8_t) (0x01 << 3))
	ITC interrupt priority vector 29 [1] (in _ITC_SPR8) More...

#define	STM8S001J3

#define	STM8S001

#define	STM8_PFLASH_SIZE 8192

#define	STM8_RAM_SIZE 1024

#define	STM8_EEPROM_SIZE 128

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM4_AddressBase 0x5340

#define	ADC1_AddressBase 0x53E0

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	STM8S003F3

#define	STM8S003

#define	STM8_PFLASH_SIZE 8192

#define	STM8_RAM_SIZE 1024

#define	STM8_EEPROM_SIZE 128

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM4_AddressBase 0x5340

#define	ADC1_AddressBase 0x53E0

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	STM8S003K3

#define	STM8S003

#define	STM8_PFLASH_SIZE 8192

#define	STM8_RAM_SIZE 1024

#define	STM8_EEPROM_SIZE 128

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM4_AddressBase 0x5340

#define	ADC1_AddressBase 0x53E0

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	STM8S005C6

#define	STM8S005

#define	STM8_PFLASH_SIZE 32768

#define	STM8_RAM_SIZE 2048

#define	STM8_EEPROM_SIZE 128

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART2_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC1_AddressBase 0x53E0

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	STM8S005K6

#define	STM8S005

#define	STM8_PFLASH_SIZE 32768

#define	STM8_RAM_SIZE 2048

#define	STM8_EEPROM_SIZE 128

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART2_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC1_AddressBase 0x53E0

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	STM8S007C8

#define	STM8S007

#define	STM8_PFLASH_SIZE 65536

#define	STM8_RAM_SIZE 6144

#define	STM8_EEPROM_SIZE 128

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	PORTH_AddressBase 0x5023

#define	PORTI_AddressBase 0x5028

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	UART3_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC2_AddressBase 0x5400

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	STM8S103F2

#define	STM8S103

#define	STM8_PFLASH_SIZE 4096

#define	STM8_RAM_SIZE 1024

#define	STM8_EEPROM_SIZE 640

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM4_AddressBase 0x5340

#define	ADC1_AddressBase 0x53E0

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	UID_AddressBase 0x4865

#define	STM8S103F3

#define	STM8S103

#define	STM8_PFLASH_SIZE 8192

#define	STM8_RAM_SIZE 1024

#define	STM8_EEPROM_SIZE 640

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM4_AddressBase 0x5340

#define	ADC1_AddressBase 0x53E0

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	UID_AddressBase 0x4865

#define	STM8S103K3

#define	STM8S103

#define	STM8_PFLASH_SIZE 8192

#define	STM8_RAM_SIZE 1024

#define	STM8_EEPROM_SIZE 640

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM4_AddressBase 0x5340

#define	ADC1_AddressBase 0x53E0

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	UID_AddressBase 0x4865

#define	STM8S105C4

#define	STM8S105

#define	STM8_PFLASH_SIZE 16384

#define	STM8_RAM_SIZE 2048

#define	STM8_EEPROM_SIZE 1024

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART2_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC1_AddressBase 0x53E0

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	UID_AddressBase 0x48CD

#define	STM8S105C6

#define	STM8S105

#define	STM8_PFLASH_SIZE 32768

#define	STM8_RAM_SIZE 2048

#define	STM8_EEPROM_SIZE 1024

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART2_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC1_AddressBase 0x53E0

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	UID_AddressBase 0x48CD

#define	STM8S105K4

#define	STM8S105

#define	STM8_PFLASH_SIZE 16384

#define	STM8_RAM_SIZE 2048

#define	STM8_EEPROM_SIZE 1024

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART2_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC1_AddressBase 0x53E0

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	UID_AddressBase 0x48CD

#define	STM8S105K6

#define	STM8S105

#define	STM8_PFLASH_SIZE 32768

#define	STM8_RAM_SIZE 2048

#define	STM8_EEPROM_SIZE 1024

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART2_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC1_AddressBase 0x53E0

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	UID_AddressBase 0x48CD

#define	STM8S105S4

#define	STM8S105

#define	STM8_PFLASH_SIZE 16384

#define	STM8_RAM_SIZE 2048

#define	STM8_EEPROM_SIZE 1024

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART2_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC1_AddressBase 0x53E0

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	UID_AddressBase 0x48CD

#define	STM8S105S6

#define	STM8S105

#define	STM8_PFLASH_SIZE 32768

#define	STM8_RAM_SIZE 2048

#define	STM8_EEPROM_SIZE 1024

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART2_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC1_AddressBase 0x53E0

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	UID_AddressBase 0x48CD

#define	STM8S207C6

#define	STM8S207

#define	STM8_PFLASH_SIZE 32768

#define	STM8_RAM_SIZE 6144

#define	STM8_EEPROM_SIZE 1024

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	PORTH_AddressBase 0x5023

#define	PORTI_AddressBase 0x5028

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	UART3_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC2_AddressBase 0x5400

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	UID_AddressBase 0x48CD

#define	STM8S207C8

#define	STM8S207

#define	STM8_PFLASH_SIZE 65536

#define	STM8_RAM_SIZE 6144

#define	STM8_EEPROM_SIZE 1536

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	PORTH_AddressBase 0x5023

#define	PORTI_AddressBase 0x5028

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	UART3_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC2_AddressBase 0x5400

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	UID_AddressBase 0x48CD

#define	STM8S207CB

#define	STM8S207

#define	STM8_PFLASH_SIZE 131072

#define	STM8_RAM_SIZE 6144

#define	STM8_EEPROM_SIZE 2048

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	PORTH_AddressBase 0x5023

#define	PORTI_AddressBase 0x5028

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	UART3_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC2_AddressBase 0x5400

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	UID_AddressBase 0x48CD

#define	STM8S207K6

#define	STM8S207

#define	STM8_PFLASH_SIZE 32768

#define	STM8_RAM_SIZE 6144

#define	STM8_EEPROM_SIZE 1024

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	PORTH_AddressBase 0x5023

#define	PORTI_AddressBase 0x5028

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	UART3_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC2_AddressBase 0x5400

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	UID_AddressBase 0x48CD

#define	STM8S207K8

#define	STM8S207

#define	STM8_PFLASH_SIZE 65536

#define	STM8_RAM_SIZE 6144

#define	STM8_EEPROM_SIZE 1024

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	PORTH_AddressBase 0x5023

#define	PORTI_AddressBase 0x5028

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	UART3_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC2_AddressBase 0x5400

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	UID_AddressBase 0x48CD

#define	STM8S207M8

#define	STM8S207

#define	STM8_PFLASH_SIZE 65536

#define	STM8_RAM_SIZE 6144

#define	STM8_EEPROM_SIZE 2048

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	PORTH_AddressBase 0x5023

#define	PORTI_AddressBase 0x5028

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	UART3_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC2_AddressBase 0x5400

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	UID_AddressBase 0x48CD

#define	STM8S207MB

#define	STM8S207

#define	STM8_PFLASH_SIZE 131072

#define	STM8_RAM_SIZE 6144

#define	STM8_EEPROM_SIZE 2048

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	PORTH_AddressBase 0x5023

#define	PORTI_AddressBase 0x5028

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	UART3_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC2_AddressBase 0x5400

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	UID_AddressBase 0x48CD

#define	STM8S207R6

#define	STM8S207

#define	STM8_PFLASH_SIZE 32768

#define	STM8_RAM_SIZE 6144

#define	STM8_EEPROM_SIZE 1024

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	PORTH_AddressBase 0x5023

#define	PORTI_AddressBase 0x5028

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	UART3_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC2_AddressBase 0x5400

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	UID_AddressBase 0x48CD

#define	STM8S207R8

#define	STM8S207

#define	STM8_PFLASH_SIZE 65536

#define	STM8_RAM_SIZE 6144

#define	STM8_EEPROM_SIZE 1536

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	PORTH_AddressBase 0x5023

#define	PORTI_AddressBase 0x5028

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	UART3_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC2_AddressBase 0x5400

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	UID_AddressBase 0x48CD

#define	STM8S207RB

#define	STM8S207

#define	STM8_PFLASH_SIZE 131072

#define	STM8_RAM_SIZE 6144

#define	STM8_EEPROM_SIZE 2048

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	PORTH_AddressBase 0x5023

#define	PORTI_AddressBase 0x5028

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	UART3_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC2_AddressBase 0x5400

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	UID_AddressBase 0x48CD

#define	STM8S207S6

#define	STM8S207

#define	STM8_PFLASH_SIZE 32768

#define	STM8_RAM_SIZE 6144

#define	STM8_EEPROM_SIZE 1024

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	PORTH_AddressBase 0x5023

#define	PORTI_AddressBase 0x5028

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	UART3_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC2_AddressBase 0x5400

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	UID_AddressBase 0x48CD

#define	STM8S207S8

#define	STM8S207

#define	STM8_PFLASH_SIZE 65536

#define	STM8_RAM_SIZE 6144

#define	STM8_EEPROM_SIZE 1536

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	PORTH_AddressBase 0x5023

#define	PORTI_AddressBase 0x5028

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	UART3_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC2_AddressBase 0x5400

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	UID_AddressBase 0x48CD

#define	STM8S207SB

#define	STM8S207

#define	STM8_PFLASH_SIZE 131072

#define	STM8_RAM_SIZE 6144

#define	STM8_EEPROM_SIZE 1536

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	PORTH_AddressBase 0x5023

#define	PORTI_AddressBase 0x5028

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	UART3_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC2_AddressBase 0x5400

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	UID_AddressBase 0x48CD

#define	STM8S208C6

#define	STM8S208

#define	STM8_PFLASH_SIZE 32768

#define	STM8_RAM_SIZE 6144

#define	STM8_EEPROM_SIZE 2048

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	PORTH_AddressBase 0x5023

#define	PORTI_AddressBase 0x5028

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	UART3_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC2_AddressBase 0x5400

#define	CAN_AddressBase 0x5420

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	UID_AddressBase 0x48CD

#define	STM8S208C8

#define	STM8S208

#define	STM8_PFLASH_SIZE 65536

#define	STM8_RAM_SIZE 6144

#define	STM8_EEPROM_SIZE 2048

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	PORTH_AddressBase 0x5023

#define	PORTI_AddressBase 0x5028

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	UART3_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC2_AddressBase 0x5400

#define	CAN_AddressBase 0x5420

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	UID_AddressBase 0x48CD

#define	STM8S208CB

#define	STM8S208

#define	STM8_PFLASH_SIZE 131072

#define	STM8_RAM_SIZE 6144

#define	STM8_EEPROM_SIZE 2048

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	PORTH_AddressBase 0x5023

#define	PORTI_AddressBase 0x5028

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	UART3_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC2_AddressBase 0x5400

#define	CAN_AddressBase 0x5420

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	UID_AddressBase 0x48CD

#define	STM8S208MB

#define	STM8S208

#define	STM8_PFLASH_SIZE 131072

#define	STM8_RAM_SIZE 6144

#define	STM8_EEPROM_SIZE 2048

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	PORTH_AddressBase 0x5023

#define	PORTI_AddressBase 0x5028

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	UART3_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC2_AddressBase 0x5400

#define	CAN_AddressBase 0x5420

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	UID_AddressBase 0x48CD

#define	STM8S208R6

#define	STM8S208

#define	STM8_PFLASH_SIZE 32768

#define	STM8_RAM_SIZE 6144

#define	STM8_EEPROM_SIZE 2048

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	PORTH_AddressBase 0x5023

#define	PORTI_AddressBase 0x5028

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	UART3_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC2_AddressBase 0x5400

#define	CAN_AddressBase 0x5420

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	UID_AddressBase 0x48CD

#define	STM8S208R8

#define	STM8S208

#define	STM8_PFLASH_SIZE 65536

#define	STM8_RAM_SIZE 6144

#define	STM8_EEPROM_SIZE 2048

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	PORTH_AddressBase 0x5023

#define	PORTI_AddressBase 0x5028

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	UART3_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC2_AddressBase 0x5400

#define	CAN_AddressBase 0x5420

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	UID_AddressBase 0x48CD

#define	STM8S208RB

#define	STM8S208

#define	STM8_PFLASH_SIZE 131072

#define	STM8_RAM_SIZE 6144

#define	STM8_EEPROM_SIZE 2048

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	PORTH_AddressBase 0x5023

#define	PORTI_AddressBase 0x5028

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	UART3_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC2_AddressBase 0x5400

#define	CAN_AddressBase 0x5420

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	UID_AddressBase 0x48CD

#define	STM8S208S6

#define	STM8S208

#define	STM8_PFLASH_SIZE 32768

#define	STM8_RAM_SIZE 6144

#define	STM8_EEPROM_SIZE 1536

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	PORTH_AddressBase 0x5023

#define	PORTI_AddressBase 0x5028

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	UART3_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC2_AddressBase 0x5400

#define	CAN_AddressBase 0x5420

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	UID_AddressBase 0x48CD

#define	STM8S208S8

#define	STM8S208

#define	STM8_PFLASH_SIZE 65536

#define	STM8_RAM_SIZE 6144

#define	STM8_EEPROM_SIZE 1536

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	PORTH_AddressBase 0x5023

#define	PORTI_AddressBase 0x5028

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	UART3_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC2_AddressBase 0x5400

#define	CAN_AddressBase 0x5420

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	UID_AddressBase 0x48CD

#define	STM8S208SB

#define	STM8S208

#define	STM8_PFLASH_SIZE 131072

#define	STM8_RAM_SIZE 6144

#define	STM8_EEPROM_SIZE 1536

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	PORTG_AddressBase 0x501E

#define	PORTH_AddressBase 0x5023

#define	PORTI_AddressBase 0x5028

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	UART3_AddressBase 0x5240

#define	TIM1_AddressBase 0x5250

#define	TIM2_AddressBase 0x5300

#define	TIM3_AddressBase 0x5320

#define	TIM4_AddressBase 0x5340

#define	ADC2_AddressBase 0x5400

#define	CAN_AddressBase 0x5420

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	UID_AddressBase 0x48CD

#define	STM8S903F3

#define	STM8S903

#define	STM8_PFLASH_SIZE 8192

#define	STM8_RAM_SIZE 1024

#define	STM8_EEPROM_SIZE 640

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	TIM1_AddressBase 0x5250

#define	TIM5_AddressBase 0x5300

#define	TIM6_AddressBase 0x5340

#define	ADC1_AddressBase 0x53E0

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	UID_AddressBase 0x4865

#define	STM8S903K3

#define	STM8S903

#define	STM8_PFLASH_SIZE 8192

#define	STM8_RAM_SIZE 1024

#define	STM8_EEPROM_SIZE 640

#define	OPT_AddressBase 0x4800

#define	PORTA_AddressBase 0x5000

#define	PORTB_AddressBase 0x5005

#define	PORTC_AddressBase 0x500A

#define	PORTD_AddressBase 0x500F

#define	PORTE_AddressBase 0x5014

#define	PORTF_AddressBase 0x5019

#define	FLASH_AddressBase 0x505A

#define	EXTI_AddressBase 0x50A0

#define	RST_AddressBase 0x50B3

#define	CLK_AddressBase 0x50C0

#define	WWDG_AddressBase 0x50D1

#define	IWDG_AddressBase 0x50E0

#define	AWU_AddressBase 0x50F0

#define	BEEP_AddressBase 0x50F3

#define	SPI_AddressBase 0x5200

#define	I2C_AddressBase 0x5210

#define	UART1_AddressBase 0x5230

#define	TIM1_AddressBase 0x5250

#define	TIM5_AddressBase 0x5300

#define	TIM6_AddressBase 0x5340

#define	ADC1_AddressBase 0x53E0

#define	CFG_AddressBase 0x7F60

#define	ITC_AddressBase 0x7F70

#define	DM_AddressBase 0x7F90

#define	UID_AddressBase 0x4865

Detailed Description

Macro Definition Documentation

◆ __ADC1_VECTOR__

#define __ADC1_VECTOR__ 22

irq22 - ADC1 end of conversion (shared with __ADC2_VECTOR__)

Definition at line 301 of file STM8AF_STM8S.h.

◆ __AWU_VECTOR__

#define __AWU_VECTOR__ 1

irq1 - Auto Wake Up from Halt interrupt (AWU)

Definition at line 243 of file STM8AF_STM8S.h.

◆ __CAN_RX_VECTOR__

#define __CAN_RX_VECTOR__ 8

irq8 - CAN receive interrupt (shared with __PORTF_VECTOR__)

Definition at line 251 of file STM8AF_STM8S.h.

◆ __CAN_TX_VECTOR__

#define __CAN_TX_VECTOR__ 9

irq9 - CAN transmit interrupt

Definition at line 257 of file STM8AF_STM8S.h.

◆ __CLK_VECTOR__

#define __CLK_VECTOR__ 2

irq2 - Clock Controller interrupt

Definition at line 244 of file STM8AF_STM8S.h.

◆ __FLASH_VECTOR__

#define __FLASH_VECTOR__ 24

irq24 - flash interrupt

Definition at line 310 of file STM8AF_STM8S.h.

◆ __I2C_VECTOR__

#define __I2C_VECTOR__ 19

irq19 - I2C interrupt

Definition at line 285 of file STM8AF_STM8S.h.

◆ __PORTA_VECTOR__

#define __PORTA_VECTOR__ 3

irq3 - External interrupt 0 (GPIOA)

Definition at line 245 of file STM8AF_STM8S.h.

◆ __PORTB_VECTOR__

#define __PORTB_VECTOR__ 4

irq4 - External interrupt 1 (GPIOB)

Definition at line 246 of file STM8AF_STM8S.h.

◆ __PORTC_VECTOR__

#define __PORTC_VECTOR__ 5

irq5 - External interrupt 2 (GPIOC)

Definition at line 247 of file STM8AF_STM8S.h.

◆ __PORTD_VECTOR__

#define __PORTD_VECTOR__ 6

irq6 - External interrupt 3 (GPIOD)

Definition at line 248 of file STM8AF_STM8S.h.

◆ __PORTE_VECTOR__

#define __PORTE_VECTOR__ 7

irq7 - External interrupt 4 (GPIOE)

Definition at line 249 of file STM8AF_STM8S.h.

◆ __PORTF_VECTOR__

#define __PORTF_VECTOR__ 8

irq8 - External interrupt 5 (GPIOF, shared with __CAN_RX_VECTOR__)

Definition at line 254 of file STM8AF_STM8S.h.

◆ __SPI_VECTOR__

#define __SPI_VECTOR__ 10

irq10 - SPI End of transfer interrupt

Definition at line 259 of file STM8AF_STM8S.h.

◆ __TIM1_CAPCOM_VECTOR__

#define __TIM1_CAPCOM_VECTOR__ 12

irq12 - TIM1 Capture/Compare interrupt

Definition at line 261 of file STM8AF_STM8S.h.

◆ __TIM1_UPD_OVF_VECTOR__

#define __TIM1_UPD_OVF_VECTOR__ 11

irq11 - TIM1 Update/Overflow/Trigger/Break interrupt

Definition at line 260 of file STM8AF_STM8S.h.

◆ __TIM2_CAPCOM_VECTOR__

#define __TIM2_CAPCOM_VECTOR__ 14

irq14 - TIM2 Capture/Compare interrupt (shared with __TIM5_CAPCOM_VECTOR__)

Definition at line 269 of file STM8AF_STM8S.h.

◆ __TIM2_UPD_OVF_VECTOR__

#define __TIM2_UPD_OVF_VECTOR__ 13

irq13 - TIM2 Update/overflow interrupt (shared with __TIM5_UPD_OVF_VECTOR__)

Definition at line 263 of file STM8AF_STM8S.h.

◆ __TIM3_CAPCOM_VECTOR__

#define __TIM3_CAPCOM_VECTOR__ 16

irq16 - TIM3 Capture/Compare interrupt

Definition at line 277 of file STM8AF_STM8S.h.

◆ __TIM3_UPD_OVF_VECTOR__

#define __TIM3_UPD_OVF_VECTOR__ 15

irq15 - TIM3 Update/overflow interrupt

Definition at line 274 of file STM8AF_STM8S.h.

◆ __TIM4_UPD_OVF_VECTOR__

#define __TIM4_UPD_OVF_VECTOR__ 23

irq23 - TIM4 Update/Overflow interrupt (shared with __TIM6_UPD_OVF_VECTOR__)

Definition at line 306 of file STM8AF_STM8S.h.

◆ __TIM5_UPD_OVF_VECTOR__

#define __TIM5_UPD_OVF_VECTOR__ 13

irq13 - TIM5 Update/overflow interrupt (shared with __TIM2_UPD_OVF_VECTOR__)

Definition at line 266 of file STM8AF_STM8S.h.

◆ __TLI_VECTOR__

#define __TLI_VECTOR__ 0

irq0 - External Top Level interrupt (TLI) for pin PD7

Definition at line 242 of file STM8AF_STM8S.h.

◆ __UART1_RXF_VECTOR__

#define __UART1_RXF_VECTOR__ 18

irq18 - USART/UART1 receive (RX full) interrupt

Definition at line 283 of file STM8AF_STM8S.h.

◆ __UART1_TXE_VECTOR__

#define __UART1_TXE_VECTOR__ 17

irq17 - USART/UART1 send (TX empty) interrupt

Definition at line 280 of file STM8AF_STM8S.h.

◆ __UART2_RXF_VECTOR__

#define __UART2_RXF_VECTOR__ 21

irq21 - UART2 receive (RX full) interrupt (shared with __UART3_RXF_VECTOR__ and __UART4_RXF_VECTOR__)

Definition at line 294 of file STM8AF_STM8S.h.

◆ __UART2_TXE_VECTOR__

#define __UART2_TXE_VECTOR__ 20

irq20 - UART2 send (TX empty) interrupt (shared with __UART3_TXE_VECTOR__ and __UART4_TXE_VECTOR__)

Definition at line 287 of file STM8AF_STM8S.h.

◆ _ADC1

#define _ADC1 _SFR(ADC1_t, ADC1_AddressBase)

ADC1 struct/bit access.

Definition at line 4794 of file STM8AF_STM8S.h.

◆ _ADC1_ADON

#define _ADC1_ADON ((uint8_t) (0x01 << 0))

ADC1 Conversion on/off [0] (in _ADC1_CR1)

Definition at line 4859 of file STM8AF_STM8S.h.

◆ _ADC1_ALIGN

#define _ADC1_ALIGN ((uint8_t) (0x01 << 3))

ADC1 Data alignment [0] (in _ADC1_CR2)

Definition at line 4872 of file STM8AF_STM8S.h.

◆ _ADC1_AWCRH

#define _ADC1_AWCRH _SFR(uint8_t, ADC1_AddressBase+0x2E)

ADC1 watchdog control register.

Definition at line 4830 of file STM8AF_STM8S.h.

◆ _ADC1_AWCRH_RESET_VALUE

#define _ADC1_AWCRH_RESET_VALUE ((uint8_t) 0x00)

ADC1 watchdog control register reset value.

Definition at line 4844 of file STM8AF_STM8S.h.

◆ _ADC1_AWCRL

#define _ADC1_AWCRL _SFR(uint8_t, ADC1_AddressBase+0x2F)

ADC1 watchdog control register.

Definition at line 4831 of file STM8AF_STM8S.h.

◆ _ADC1_AWCRL_RESET_VALUE

#define _ADC1_AWCRL_RESET_VALUE ((uint8_t) 0x00)

ADC1 watchdog control register reset value.

Definition at line 4845 of file STM8AF_STM8S.h.

◆ _ADC1_AWD

#define _ADC1_AWD ((uint8_t) (0x01 << 6))

ADC1 Analog Watchdog flag [0] (in _ADC1_CSR)

Definition at line 4855 of file STM8AF_STM8S.h.

◆ _ADC1_AWDIE

#define _ADC1_AWDIE ((uint8_t) (0x01 << 4))

ADC1 Analog watchdog interrupt enable [0] (in _ADC1_CSR)

Definition at line 4853 of file STM8AF_STM8S.h.

◆ _ADC1_AWSRH

#define _ADC1_AWSRH _SFR(uint8_t, ADC1_AddressBase+0x2C)

ADC1 watchdog status register.

Definition at line 4828 of file STM8AF_STM8S.h.

◆ _ADC1_AWSRL

#define _ADC1_AWSRL _SFR(uint8_t, ADC1_AddressBase+0x2D)

ADC1 watchdog status register.

Definition at line 4829 of file STM8AF_STM8S.h.

◆ _ADC1_CH

#define _ADC1_CH ((uint8_t) (0x0F << 0))

ADC1 Channel selection bits [3:0] (in _ADC1_CSR)

Definition at line 4848 of file STM8AF_STM8S.h.

◆ _ADC1_CH0

#define _ADC1_CH0 ((uint8_t) (0x01 << 0))

ADC1 Channel selection bits [0] (in _ADC1_CSR)

Definition at line 4849 of file STM8AF_STM8S.h.

◆ _ADC1_CH1

#define _ADC1_CH1 ((uint8_t) (0x01 << 1))

ADC1 Channel selection bits [1] (in _ADC1_CSR)

Definition at line 4850 of file STM8AF_STM8S.h.

◆ _ADC1_CH2

#define _ADC1_CH2 ((uint8_t) (0x01 << 2))

ADC1 Channel selection bits [2] (in _ADC1_CSR)

Definition at line 4851 of file STM8AF_STM8S.h.

◆ _ADC1_CH3

#define _ADC1_CH3 ((uint8_t) (0x01 << 3))

ADC1 Channel selection bits [3] (in _ADC1_CSR)

Definition at line 4852 of file STM8AF_STM8S.h.

◆ _ADC1_CONT

#define _ADC1_CONT ((uint8_t) (0x01 << 1))

ADC1 Continuous conversion [0] (in _ADC1_CR1)

Definition at line 4860 of file STM8AF_STM8S.h.

◆ _ADC1_CR1

#define _ADC1_CR1 _SFR(uint8_t, ADC1_AddressBase+0x21)

ADC1 Configuration Register 1.

Definition at line 4817 of file STM8AF_STM8S.h.

◆ _ADC1_CR1_RESET_VALUE

#define _ADC1_CR1_RESET_VALUE ((uint8_t) 0x00)

ADC1 Configuration Register 1 reset value.

Definition at line 4835 of file STM8AF_STM8S.h.

◆ _ADC1_CR2

#define _ADC1_CR2 _SFR(uint8_t, ADC1_AddressBase+0x22)

ADC1 Configuration Register 2.

Definition at line 4818 of file STM8AF_STM8S.h.

◆ _ADC1_CR2_RESET_VALUE

#define _ADC1_CR2_RESET_VALUE ((uint8_t) 0x00)

ADC1 Configuration Register 2 reset value.

Definition at line 4836 of file STM8AF_STM8S.h.

◆ _ADC1_CR3

#define _ADC1_CR3 _SFR(uint8_t, ADC1_AddressBase+0x23)

ADC1 Configuration Register 3.

Definition at line 4819 of file STM8AF_STM8S.h.

◆ _ADC1_CR3_RESET_VALUE

#define _ADC1_CR3_RESET_VALUE ((uint8_t) 0x00)

ADC1 Configuration Register 3 reset value.

Definition at line 4837 of file STM8AF_STM8S.h.

◆ _ADC1_CSR

#define _ADC1_CSR _SFR(uint8_t, ADC1_AddressBase+0x20)

ADC1 control/status register.

Definition at line 4816 of file STM8AF_STM8S.h.

◆ _ADC1_CSR_RESET_VALUE

#define _ADC1_CSR_RESET_VALUE ((uint8_t) 0x00)

ADC1 control/status register reset value.

Definition at line 4834 of file STM8AF_STM8S.h.

◆ _ADC1_DB0RH

#define _ADC1_DB0RH _SFR(uint8_t, ADC1_AddressBase+0x00)

ADC1 10-bit Data Buffer Register 0.

Definition at line 4795 of file STM8AF_STM8S.h.

◆ _ADC1_DB0RL

#define _ADC1_DB0RL _SFR(uint8_t, ADC1_AddressBase+0x01)

ADC1 10-bit Data Buffer Register 0.

Definition at line 4796 of file STM8AF_STM8S.h.

◆ _ADC1_DB1RH

#define _ADC1_DB1RH _SFR(uint8_t, ADC1_AddressBase+0x02)

ADC1 10-bit Data Buffer Register 1.

Definition at line 4797 of file STM8AF_STM8S.h.

◆ _ADC1_DB1RL

#define _ADC1_DB1RL _SFR(uint8_t, ADC1_AddressBase+0x03)

ADC1 10-bit Data Buffer Register 1.

Definition at line 4798 of file STM8AF_STM8S.h.

◆ _ADC1_DB2RH

#define _ADC1_DB2RH _SFR(uint8_t, ADC1_AddressBase+0x04)

ADC1 10-bit Data Buffer Register 2.

Definition at line 4799 of file STM8AF_STM8S.h.

◆ _ADC1_DB2RL

#define _ADC1_DB2RL _SFR(uint8_t, ADC1_AddressBase+0x05)

ADC1 10-bit Data Buffer Register 2.

Definition at line 4800 of file STM8AF_STM8S.h.

◆ _ADC1_DB3RH

#define _ADC1_DB3RH _SFR(uint8_t, ADC1_AddressBase+0x06)

ADC1 10-bit Data Buffer Register 3.

Definition at line 4801 of file STM8AF_STM8S.h.

◆ _ADC1_DB3RL

#define _ADC1_DB3RL _SFR(uint8_t, ADC1_AddressBase+0x07)

ADC1 10-bit Data Buffer Register 3.

Definition at line 4802 of file STM8AF_STM8S.h.

◆ _ADC1_DB4RH

#define _ADC1_DB4RH _SFR(uint8_t, ADC1_AddressBase+0x08)

ADC1 10-bit Data Buffer Register 4.

Definition at line 4803 of file STM8AF_STM8S.h.

◆ _ADC1_DB4RL

#define _ADC1_DB4RL _SFR(uint8_t, ADC1_AddressBase+0x09)

ADC1 10-bit Data Buffer Register 4.

Definition at line 4804 of file STM8AF_STM8S.h.

◆ _ADC1_DB5RH

#define _ADC1_DB5RH _SFR(uint8_t, ADC1_AddressBase+0x0A)

ADC1 10-bit Data Buffer Register 5.

Definition at line 4805 of file STM8AF_STM8S.h.

◆ _ADC1_DB5RL

#define _ADC1_DB5RL _SFR(uint8_t, ADC1_AddressBase+0x0B)

ADC1 10-bit Data Buffer Register 5.

Definition at line 4806 of file STM8AF_STM8S.h.

◆ _ADC1_DB6RH

#define _ADC1_DB6RH _SFR(uint8_t, ADC1_AddressBase+0x0C)

ADC1 10-bit Data Buffer Register 6.

Definition at line 4807 of file STM8AF_STM8S.h.

◆ _ADC1_DB6RL

#define _ADC1_DB6RL _SFR(uint8_t, ADC1_AddressBase+0x0D)

ADC1 10-bit Data Buffer Register 6.

Definition at line 4808 of file STM8AF_STM8S.h.

◆ _ADC1_DB7RH

#define _ADC1_DB7RH _SFR(uint8_t, ADC1_AddressBase+0x0E)

ADC1 10-bit Data Buffer Register 7.

Definition at line 4809 of file STM8AF_STM8S.h.

◆ _ADC1_DB7RL

#define _ADC1_DB7RL _SFR(uint8_t, ADC1_AddressBase+0x0F)

ADC1 10-bit Data Buffer Register 7.

Definition at line 4810 of file STM8AF_STM8S.h.

◆ _ADC1_DB8RH

#define _ADC1_DB8RH _SFR(uint8_t, ADC1_AddressBase+0x10)

ADC1 10-bit Data Buffer Register 8.

Definition at line 4811 of file STM8AF_STM8S.h.

◆ _ADC1_DB8RL

#define _ADC1_DB8RL _SFR(uint8_t, ADC1_AddressBase+0x11)

ADC1 10-bit Data Buffer Register 8.

Definition at line 4812 of file STM8AF_STM8S.h.

◆ _ADC1_DB9RH

#define _ADC1_DB9RH _SFR(uint8_t, ADC1_AddressBase+0x12)

ADC1 10-bit Data Buffer Register 9.

Definition at line 4813 of file STM8AF_STM8S.h.

◆ _ADC1_DB9RL

#define _ADC1_DB9RL _SFR(uint8_t, ADC1_AddressBase+0x13)

ADC1 10-bit Data Buffer Register 9.

Definition at line 4814 of file STM8AF_STM8S.h.

◆ _ADC1_DBUF

#define _ADC1_DBUF ((uint8_t) (0x01 << 7))

ADC1 Data buffer enable [0] (in _ADC1_CR3)

Definition at line 4882 of file STM8AF_STM8S.h.

◆ _ADC1_DRH

#define _ADC1_DRH _SFR(uint8_t, ADC1_AddressBase+0x24)

ADC1 (unbuffered) 10-bit measurement result.

Definition at line 4820 of file STM8AF_STM8S.h.

◆ _ADC1_DRL

#define _ADC1_DRL _SFR(uint8_t, ADC1_AddressBase+0x25)

ADC1 (unbuffered) 10-bit measurement result.

Definition at line 4821 of file STM8AF_STM8S.h.

◆ _ADC1_EOC

#define _ADC1_EOC ((uint8_t) (0x01 << 7))

ADC1 End of conversion [0] (in _ADC1_CSR)

Definition at line 4856 of file STM8AF_STM8S.h.

◆ _ADC1_EOCIE

#define _ADC1_EOCIE ((uint8_t) (0x01 << 5))

ADC1 Interrupt enable for EOC [0] (in _ADC1_CSR)

Definition at line 4854 of file STM8AF_STM8S.h.

◆ _ADC1_EXTSEL

#define _ADC1_EXTSEL ((uint8_t) (0x03 << 4)

ADC1 External event selection [1:0] (in _ADC1_CR2)

Definition at line 4873 of file STM8AF_STM8S.h.

◆ _ADC1_EXTSEL0

#define _ADC1_EXTSEL0 ((uint8_t) (0x01 << 4)

ADC1 External event selection [0] (in _ADC1_CR2)

Definition at line 4874 of file STM8AF_STM8S.h.

◆ _ADC1_EXTSEL1

#define _ADC1_EXTSEL1 ((uint8_t) (0x01 << 5)

ADC1 External event selection [1] (in _ADC1_CR2)

Definition at line 4875 of file STM8AF_STM8S.h.

◆ _ADC1_EXTTRIG

#define _ADC1_EXTTRIG ((uint8_t) (0x01 << 6))

ADC1 External trigger enable [0] (in _ADC1_CR2)

Definition at line 4876 of file STM8AF_STM8S.h.

◆ _ADC1_HTRH

#define _ADC1_HTRH _SFR(uint8_t, ADC1_AddressBase+0x28)

ADC1 watchdog high threshold register.

Definition at line 4824 of file STM8AF_STM8S.h.

◆ _ADC1_HTRH_RESET_VALUE

#define _ADC1_HTRH_RESET_VALUE ((uint8_t) 0xFF)

ADC1 watchdog high threshold register reset value.

Definition at line 4840 of file STM8AF_STM8S.h.

◆ _ADC1_HTRL

#define _ADC1_HTRL _SFR(uint8_t, ADC1_AddressBase+0x29)

ADC1 watchdog high threshold register.

Definition at line 4825 of file STM8AF_STM8S.h.

◆ _ADC1_HTRL_RESET_VALUE

#define _ADC1_HTRL_RESET_VALUE ((uint8_t) 0x03)

ADC1 watchdog high threshold register reset value.

Definition at line 4841 of file STM8AF_STM8S.h.

◆ _ADC1_LTRH

#define _ADC1_LTRH _SFR(uint8_t, ADC1_AddressBase+0x2A)

ADC1 watchdog low threshold register.

Definition at line 4826 of file STM8AF_STM8S.h.

◆ _ADC1_LTRH_RESET_VALUE

#define _ADC1_LTRH_RESET_VALUE ((uint8_t) 0x00)

ADC1 watchdog low threshold register reset value.

Definition at line 4842 of file STM8AF_STM8S.h.

◆ _ADC1_LTRL

#define _ADC1_LTRL _SFR(uint8_t, ADC1_AddressBase+0x2B)

ADC1 watchdog low threshold register.

Definition at line 4827 of file STM8AF_STM8S.h.

◆ _ADC1_LTRL_RESET_VALUE

#define _ADC1_LTRL_RESET_VALUE ((uint8_t) 0x00)

ADC1 watchdog low threshold register reset value.

Definition at line 4843 of file STM8AF_STM8S.h.

◆ _ADC1_OVR

#define _ADC1_OVR ((uint8_t) (0x01 << 6))

ADC1 Overrun flag [0] (in _ADC1_CR3)

Definition at line 4881 of file STM8AF_STM8S.h.

◆ _ADC1_SCAN

#define _ADC1_SCAN ((uint8_t) (0x01 << 1))

ADC1 Scan mode enable [0] (in _ADC1_CR2)

Definition at line 4870 of file STM8AF_STM8S.h.

◆ _ADC1_SPSEL

#define _ADC1_SPSEL ((uint8_t) (0x07 << 4)

ADC1 clock prescaler selection [2:0] (in _ADC1_CR1)

Definition at line 4862 of file STM8AF_STM8S.h.

◆ _ADC1_SPSEL0

#define _ADC1_SPSEL0 ((uint8_t) (0x01 << 4)

ADC1 clock prescaler selection [0] (in _ADC1_CR1)

Definition at line 4863 of file STM8AF_STM8S.h.

◆ _ADC1_SPSEL1

#define _ADC1_SPSEL1 ((uint8_t) (0x01 << 5)

ADC1 clock prescaler selection [1] (in _ADC1_CR1)

Definition at line 4864 of file STM8AF_STM8S.h.

◆ _ADC1_SPSEL2

#define _ADC1_SPSEL2 ((uint8_t) (0x01 << 6)

ADC1 clock prescaler selection [2] (in _ADC1_CR1)

Definition at line 4865 of file STM8AF_STM8S.h.

◆ _ADC1_TDRH

#define _ADC1_TDRH _SFR(uint8_t, ADC1_AddressBase+0x26)

ADC1 Schmitt trigger disable register.

Definition at line 4822 of file STM8AF_STM8S.h.

◆ _ADC1_TDRH_RESET_VALUE

#define _ADC1_TDRH_RESET_VALUE ((uint8_t) 0x00)

ADC1 Schmitt trigger disable register reset value.

Definition at line 4838 of file STM8AF_STM8S.h.

◆ _ADC1_TDRL

#define _ADC1_TDRL _SFR(uint8_t, ADC1_AddressBase+0x27)

ADC1 Schmitt trigger disable register.

Definition at line 4823 of file STM8AF_STM8S.h.

◆ _ADC1_TDRL_RESET_VALUE

#define _ADC1_TDRL_RESET_VALUE ((uint8_t) 0x00)

ADC1 Schmitt trigger disable register reset value.

Definition at line 4839 of file STM8AF_STM8S.h.

◆ _ADC2

#define _ADC2 _SFR(ADC2_t, ADC2_AddressBase)

ADC2 struct/bit access.

Definition at line 4957 of file STM8AF_STM8S.h.

◆ _ADC2_ADON

#define _ADC2_ADON ((uint8_t) (0x01 << 0))

ADC2 Conversion on/off [0] (in _ADC2_CR1)

Definition at line 4986 of file STM8AF_STM8S.h.

◆ _ADC2_ALIGN

#define _ADC2_ALIGN ((uint8_t) (0x01 << 3))

ADC2 Data alignment [0] (in _ADC2_CR2)

Definition at line 4997 of file STM8AF_STM8S.h.

◆ _ADC2_CH

#define _ADC2_CH ((uint8_t) (0x0F << 0))

ADC2 Channel selection bits [3:0] (in _ADC2_CSR)

Definition at line 4975 of file STM8AF_STM8S.h.

◆ _ADC2_CH0

#define _ADC2_CH0 ((uint8_t) (0x01 << 0))

ADC2 Channel selection bits [0] (in _ADC2_CSR)

Definition at line 4976 of file STM8AF_STM8S.h.

◆ _ADC2_CH1

#define _ADC2_CH1 ((uint8_t) (0x01 << 1))

ADC2 Channel selection bits [1] (in _ADC2_CSR)

Definition at line 4977 of file STM8AF_STM8S.h.

◆ _ADC2_CH2

#define _ADC2_CH2 ((uint8_t) (0x01 << 2))

ADC2 Channel selection bits [2] (in _ADC2_CSR)

Definition at line 4978 of file STM8AF_STM8S.h.

◆ _ADC2_CH3

#define _ADC2_CH3 ((uint8_t) (0x01 << 3))

ADC2 Channel selection bits [3] (in _ADC2_CSR)

Definition at line 4979 of file STM8AF_STM8S.h.

◆ _ADC2_CONT

#define _ADC2_CONT ((uint8_t) (0x01 << 1))

ADC2 Continuous conversion [0] (in _ADC2_CR1)

Definition at line 4987 of file STM8AF_STM8S.h.

◆ _ADC2_CR1

#define _ADC2_CR1 _SFR(uint8_t, ADC2_AddressBase+0x01)

ADC2 Configuration Register 1.

Definition at line 4959 of file STM8AF_STM8S.h.

◆ _ADC2_CR1_RESET_VALUE

#define _ADC2_CR1_RESET_VALUE ((uint8_t) 0x00)

ADC2 Configuration Register 1 reset value.

Definition at line 4969 of file STM8AF_STM8S.h.

◆ _ADC2_CR2

#define _ADC2_CR2 _SFR(uint8_t, ADC2_AddressBase+0x02)

ADC2 Configuration Register 2.

Definition at line 4960 of file STM8AF_STM8S.h.

◆ _ADC2_CR2_RESET_VALUE

#define _ADC2_CR2_RESET_VALUE ((uint8_t) 0x00)

ADC2 Configuration Register 2 reset value.

Definition at line 4970 of file STM8AF_STM8S.h.

◆ _ADC2_CSR

#define _ADC2_CSR _SFR(uint8_t, ADC2_AddressBase+0x00)

ADC2 control/status register.

Definition at line 4958 of file STM8AF_STM8S.h.

◆ _ADC2_CSR_RESET_VALUE

#define _ADC2_CSR_RESET_VALUE ((uint8_t) 0x00)

ADC2 control/status register reset value.

Definition at line 4968 of file STM8AF_STM8S.h.

◆ _ADC2_DRH

#define _ADC2_DRH _SFR(uint8_t, ADC2_AddressBase+0x04)

ADC2 (unbuffered) 10-bit measurement result.

Definition at line 4962 of file STM8AF_STM8S.h.

◆ _ADC2_DRL

#define _ADC2_DRL _SFR(uint8_t, ADC2_AddressBase+0x05)

ADC2 (unbuffered) 10-bit measurement result.

Definition at line 4963 of file STM8AF_STM8S.h.

◆ _ADC2_EOC

#define _ADC2_EOC ((uint8_t) (0x01 << 7))

ADC2 End of conversion [0] (in _ADC2_CSR)

Definition at line 4983 of file STM8AF_STM8S.h.

◆ _ADC2_EOCIE

#define _ADC2_EOCIE ((uint8_t) (0x01 << 5))

ADC2 Interrupt enable for EOC [0] (in _ADC2_CSR)

Definition at line 4981 of file STM8AF_STM8S.h.

◆ _ADC2_EXTSEL

#define _ADC2_EXTSEL ((uint8_t) (0x03 << 4)

ADC2 External event selection [1:0] (in _ADC2_CR2)

Definition at line 4998 of file STM8AF_STM8S.h.

◆ _ADC2_EXTSEL0

#define _ADC2_EXTSEL0 ((uint8_t) (0x01 << 4)

ADC2 External event selection [0] (in _ADC2_CR2)

Definition at line 4999 of file STM8AF_STM8S.h.

◆ _ADC2_EXTSEL1

#define _ADC2_EXTSEL1 ((uint8_t) (0x01 << 5)

ADC2 External event selection [1] (in _ADC2_CR2)

Definition at line 5000 of file STM8AF_STM8S.h.

◆ _ADC2_EXTTRIG

#define _ADC2_EXTTRIG ((uint8_t) (0x01 << 6))

ADC2 External trigger enable [0] (in _ADC2_CR2)

Definition at line 5001 of file STM8AF_STM8S.h.

◆ _ADC2_SPSEL

#define _ADC2_SPSEL ((uint8_t) (0x07 << 4)

ADC2 clock prescaler selection [2:0] (in _ADC2_CR1)

Definition at line 4989 of file STM8AF_STM8S.h.

◆ _ADC2_SPSEL0

#define _ADC2_SPSEL0 ((uint8_t) (0x01 << 4)

ADC2 clock prescaler selection [0] (in _ADC2_CR1)

Definition at line 4990 of file STM8AF_STM8S.h.

◆ _ADC2_SPSEL1

#define _ADC2_SPSEL1 ((uint8_t) (0x01 << 5)

ADC2 clock prescaler selection [1] (in _ADC2_CR1)

Definition at line 4991 of file STM8AF_STM8S.h.

◆ _ADC2_SPSEL2

#define _ADC2_SPSEL2 ((uint8_t) (0x01 << 6)

ADC2 clock prescaler selection [2] (in _ADC2_CR1)

Definition at line 4992 of file STM8AF_STM8S.h.

◆ _ADC2_TDRH

#define _ADC2_TDRH _SFR(uint8_t, ADC2_AddressBase+0x06)

ADC2 Schmitt trigger disable register.

Definition at line 4964 of file STM8AF_STM8S.h.

◆ _ADC2_TDRH_RESET_VALUE

#define _ADC2_TDRH_RESET_VALUE ((uint8_t) 0x00)

ADC2 Schmitt trigger disable register reset value.

Definition at line 4972 of file STM8AF_STM8S.h.

◆ _ADC2_TDRL

#define _ADC2_TDRL _SFR(uint8_t, ADC2_AddressBase+0x07)

ADC2 Schmitt trigger disable register.

Definition at line 4965 of file STM8AF_STM8S.h.

◆ _ADC2_TDRL_RESET_VALUE

#define _ADC2_TDRL_RESET_VALUE ((uint8_t) 0x00)

ADC2 Schmitt trigger disable register reset value.

Definition at line 4971 of file STM8AF_STM8S.h.

◆ _AWU

#define _AWU _SFR(AWU_t, AWU_AddressBase)

Auto Wake-Up struct/bit access.

Definition at line 1128 of file STM8AF_STM8S.h.

◆ _AWU_APR

#define _AWU_APR _SFR(uint8_t, AWU_AddressBase+0x01)

Auto Wake-Up Asynchronous prescaler register (AWU_APR)

Definition at line 1130 of file STM8AF_STM8S.h.

◆ _AWU_APR_RESET_VALUE

#define _AWU_APR_RESET_VALUE ((uint8_t) 0x3F)

Auto Wake-Up Asynchronous prescaler register reset value.

Definition at line 1135 of file STM8AF_STM8S.h.

◆ _AWU_APRE

#define _AWU_APRE ((uint8_t) (0x3F << 0))

Auto-wakeup asynchronous prescaler divider [5:0] (in _AWU_APR)

Definition at line 1146 of file STM8AF_STM8S.h.

◆ _AWU_APRE0

#define _AWU_APRE0 ((uint8_t) (0x01 << 0))

Auto-wakeup asynchronous prescaler divider [0] (in _AWU_APR)

Definition at line 1147 of file STM8AF_STM8S.h.

◆ _AWU_APRE1

#define _AWU_APRE1 ((uint8_t) (0x01 << 1))

Auto-wakeup asynchronous prescaler divider [1] (in _AWU_APR)

Definition at line 1148 of file STM8AF_STM8S.h.

◆ _AWU_APRE2

#define _AWU_APRE2 ((uint8_t) (0x01 << 2))

Auto-wakeup asynchronous prescaler divider [2] (in _AWU_APR)

Definition at line 1149 of file STM8AF_STM8S.h.

◆ _AWU_APRE3

#define _AWU_APRE3 ((uint8_t) (0x01 << 3))

Auto-wakeup asynchronous prescaler divider [3] (in _AWU_APR)

Definition at line 1150 of file STM8AF_STM8S.h.

◆ _AWU_APRE4

#define _AWU_APRE4 ((uint8_t) (0x01 << 4))

Auto-wakeup asynchronous prescaler divider [4] (in _AWU_APR)

Definition at line 1151 of file STM8AF_STM8S.h.

◆ _AWU_APRE5

#define _AWU_APRE5 ((uint8_t) (0x01 << 5))

Auto-wakeup asynchronous prescaler divider [5] (in _AWU_APR)

Definition at line 1152 of file STM8AF_STM8S.h.

◆ _AWU_AWUEN

#define _AWU_AWUEN ((uint8_t) (0x01 << 4))

Auto-wakeup enable [0] (in _AWU_CSR)

Definition at line 1141 of file STM8AF_STM8S.h.

◆ _AWU_AWUF

#define _AWU_AWUF ((uint8_t) (0x01 << 5))

Auto-wakeup status flag [0] (in _AWU_CSR)

Definition at line 1142 of file STM8AF_STM8S.h.

◆ _AWU_AWUTB

#define _AWU_AWUTB ((uint8_t) (0x0F << 0))

Auto-wakeup timebase selection [3:0] (in _AWU_APR)

Definition at line 1156 of file STM8AF_STM8S.h.

◆ _AWU_AWUTB0

#define _AWU_AWUTB0 ((uint8_t) (0x01 << 0))

Auto-wakeup timebase selection [0] (in _AWU_APR)

Definition at line 1157 of file STM8AF_STM8S.h.

◆ _AWU_AWUTB1

#define _AWU_AWUTB1 ((uint8_t) (0x01 << 1))

Auto-wakeup timebase selection [1] (in _AWU_APR)

Definition at line 1158 of file STM8AF_STM8S.h.

◆ _AWU_AWUTB2

#define _AWU_AWUTB2 ((uint8_t) (0x01 << 2))

Auto-wakeup timebase selection [2] (in _AWU_APR)

Definition at line 1159 of file STM8AF_STM8S.h.

◆ _AWU_AWUTB3

#define _AWU_AWUTB3 ((uint8_t) (0x01 << 3))

Auto-wakeup timebase selection [3] (in _AWU_APR)

Definition at line 1160 of file STM8AF_STM8S.h.

◆ _AWU_CSR

#define _AWU_CSR _SFR(uint8_t, AWU_AddressBase+0x00)

Auto Wake-Up Control/status register (AWU_CSR)

Definition at line 1129 of file STM8AF_STM8S.h.

◆ _AWU_CSR_RESET_VALUE

#define _AWU_CSR_RESET_VALUE ((uint8_t) 0x00)

Auto Wake-Up Control/status register reset value.

Definition at line 1134 of file STM8AF_STM8S.h.

◆ _AWU_MSR

#define _AWU_MSR ((uint8_t) (0x01 << 0))

Auto Wake-Up LSI measurement enable [0] (in _AWU_CSR)

Definition at line 1139 of file STM8AF_STM8S.h.

◆ _AWU_TBR

#define _AWU_TBR _SFR(uint8_t, AWU_AddressBase+0x02)

Auto Wake-Up Timebase selection register (AWU_TBR)

Definition at line 1131 of file STM8AF_STM8S.h.

◆ _AWU_TBR_RESET_VALUE

#define _AWU_TBR_RESET_VALUE ((uint8_t) 0x00)

Auto Wake-Up Timebase selection register reset value.

Definition at line 1136 of file STM8AF_STM8S.h.

◆ _BEEP

#define _BEEP _SFR(BEEP_t, BEEP_AddressBase)

Beeper struct/bit access.

Definition at line 1185 of file STM8AF_STM8S.h.

◆ _BEEP_BEEPDIV

#define _BEEP_BEEPDIV ((uint8_t) (0x1F << 0))

Beeper clock prescaler divider [4:0] (in _BEEP_CSR)

Definition at line 1192 of file STM8AF_STM8S.h.

◆ _BEEP_BEEPDIV0

#define _BEEP_BEEPDIV0 ((uint8_t) (0x01 << 0))

Beeper clock prescaler divider [0] (in _BEEP_CSR)

Definition at line 1193 of file STM8AF_STM8S.h.

◆ _BEEP_BEEPDIV1

#define _BEEP_BEEPDIV1 ((uint8_t) (0x01 << 1))

Beeper clock prescaler divider [1] (in _BEEP_CSR)

Definition at line 1194 of file STM8AF_STM8S.h.

◆ _BEEP_BEEPDIV2

#define _BEEP_BEEPDIV2 ((uint8_t) (0x01 << 2))

Beeper clock prescaler divider [2] (in _BEEP_CSR)

Definition at line 1195 of file STM8AF_STM8S.h.

◆ _BEEP_BEEPDIV3

#define _BEEP_BEEPDIV3 ((uint8_t) (0x01 << 3))

Beeper clock prescaler divider [3] (in _BEEP_CSR)

Definition at line 1196 of file STM8AF_STM8S.h.

◆ _BEEP_BEEPDIV4

#define _BEEP_BEEPDIV4 ((uint8_t) (0x01 << 4))

Beeper clock prescaler divider [4] (in _BEEP_CSR)

Definition at line 1197 of file STM8AF_STM8S.h.

◆ _BEEP_BEEPEN

#define _BEEP_BEEPEN ((uint8_t) (0x01 << 5))

Beeper enable [0] (in _BEEP_CSR)

Definition at line 1198 of file STM8AF_STM8S.h.

◆ _BEEP_BEEPSEL

#define _BEEP_BEEPSEL ((uint8_t) (0x03 << 6))

Beeper frequency selection [1:0] (in _BEEP_CSR)

Definition at line 1199 of file STM8AF_STM8S.h.

◆ _BEEP_BEEPSEL0

#define _BEEP_BEEPSEL0 ((uint8_t) (0x01 << 6))

Beeper frequency selection [0] (in _BEEP_CSR)

Definition at line 1200 of file STM8AF_STM8S.h.

◆ _BEEP_BEEPSEL1

#define _BEEP_BEEPSEL1 ((uint8_t) (0x01 << 7))

Beeper frequency selection [1] (in _BEEP_CSR)

Definition at line 1201 of file STM8AF_STM8S.h.

◆ _BEEP_CSR

#define _BEEP_CSR _SFR(uint8_t, BEEP_AddressBase+0x00)

Beeper control/status register (BEEP_CSR)

Definition at line 1186 of file STM8AF_STM8S.h.

◆ _BEEP_CSR_RESET_VALUE

#define _BEEP_CSR_RESET_VALUE ((uint8_t) 0x1F)

Beeper control/status register reset value.

Definition at line 1189 of file STM8AF_STM8S.h.

◆ _BITS

#define _BITS unsigned int

data type in bit structs (follow C90 standard)

Definition at line 177 of file STM8AF_STM8S.h.

◆ _CAN

#define _CAN _SFR(CAN_t, CAN_AddressBase)

CAN struct/bit access.

Definition at line 5946 of file STM8AF_STM8S.h.

◆ _CAN_ABOM

#define _CAN_ABOM ((uint8_t) (0x01 << 6))

CAN Channel Automatic Bus-Off Management [0] (in _CAN_MCR)

Definition at line 6095 of file STM8AF_STM8S.h.

◆ _CAN_ABRQ

#define _CAN_ABRQ ((uint8_t) (0x01 << 1))

CAN Abort request for mailbox [0] (in _CAN_MCSR, page 0,1,5)

Definition at line 6163 of file STM8AF_STM8S.h.

◆ _CAN_ALST

#define _CAN_ALST ((uint8_t) (0x01 << 4))

CAN Arbitration lost [0] (in _CAN_MCSR, page 0,1,5)

Definition at line 6166 of file STM8AF_STM8S.h.

◆ _CAN_AWUM

#define _CAN_AWUM ((uint8_t) (0x01 << 5))

CAN Channel Automatic Wakeup Mode [0] (in _CAN_MCR)

Definition at line 6094 of file STM8AF_STM8S.h.

◆ _CAN_BOFF

#define _CAN_BOFF ((uint8_t) (0x01 << 2))

CAN Bus off flag [0] (in _CAN_ESR, page 6)

Definition at line 6188 of file STM8AF_STM8S.h.

◆ _CAN_BOFIE

#define _CAN_BOFIE ((uint8_t) (0x01 << 2))

CAN Bus-Off interrupt enable [0] (in _CAN_EIER, page 6)

Definition at line 6199 of file STM8AF_STM8S.h.

◆ _CAN_BRP

#define _CAN_BRP ((uint8_t) (0x3F << 0))

CAN Baud rate prescaler [5:0] (in _CAN_BTR1, page 6)

Definition at line 6207 of file STM8AF_STM8S.h.

◆ _CAN_BRP0

#define _CAN_BRP0 ((uint8_t) (0x01 << 0))

CAN Baud rate prescaler [0] (in _CAN_BTR1, page 6)

Definition at line 6208 of file STM8AF_STM8S.h.

◆ _CAN_BRP1

#define _CAN_BRP1 ((uint8_t) (0x01 << 1))

CAN Baud rate prescaler [1] (in _CAN_BTR1, page 6)

Definition at line 6209 of file STM8AF_STM8S.h.

◆ _CAN_BRP2

#define _CAN_BRP2 ((uint8_t) (0x01 << 2))

CAN Baud rate prescaler [2] (in _CAN_BTR1, page 6)

Definition at line 6210 of file STM8AF_STM8S.h.

◆ _CAN_BRP3

#define _CAN_BRP3 ((uint8_t) (0x01 << 3))

CAN Baud rate prescaler [3] (in _CAN_BTR1, page 6)

Definition at line 6211 of file STM8AF_STM8S.h.

◆ _CAN_BRP4

#define _CAN_BRP4 ((uint8_t) (0x01 << 4))

CAN Baud rate prescaler [4] (in _CAN_BTR1, page 6)

Definition at line 6212 of file STM8AF_STM8S.h.

◆ _CAN_BRP5

#define _CAN_BRP5 ((uint8_t) (0x01 << 5))

CAN Baud rate prescaler [5] (in _CAN_BTR1, page 6)

Definition at line 6213 of file STM8AF_STM8S.h.

◆ _CAN_BS1

#define _CAN_BS1 ((uint8_t) (0x0F << 0))

CAN Bit segment 1 [3:0] (in _CAN_BTR2, page 6)

Definition at line 6219 of file STM8AF_STM8S.h.

◆ _CAN_BS10

#define _CAN_BS10 ((uint8_t) (0x01 << 0))

CAN Bit segment 1 [0] (in _CAN_BTR2, page 6)

Definition at line 6220 of file STM8AF_STM8S.h.

◆ _CAN_BS11

#define _CAN_BS11 ((uint8_t) (0x01 << 1))

CAN Bit segment 1 [1] (in _CAN_BTR2, page 6)

Definition at line 6221 of file STM8AF_STM8S.h.

◆ _CAN_BS12

#define _CAN_BS12 ((uint8_t) (0x01 << 2))

CAN Bit segment 1 [2] (in _CAN_BTR2, page 6)

Definition at line 6222 of file STM8AF_STM8S.h.

◆ _CAN_BS13

#define _CAN_BS13 ((uint8_t) (0x01 << 3))

CAN Bit segment 1 [3] (in _CAN_BTR2, page 6)

Definition at line 6223 of file STM8AF_STM8S.h.

◆ _CAN_BS2

#define _CAN_BS2 ((uint8_t) (0x07 << 4))

CAN Bit segment 2 [2:0] (in _CAN_BTR2, page 6)

Definition at line 6224 of file STM8AF_STM8S.h.

◆ _CAN_BS20

#define _CAN_BS20 ((uint8_t) (0x01 << 4))

CAN Bit segment 2 [0] (in _CAN_BTR2, page 6)

Definition at line 6225 of file STM8AF_STM8S.h.

◆ _CAN_BS21

#define _CAN_BS21 ((uint8_t) (0x01 << 5))

CAN Bit segment 2 [1] (in _CAN_BTR2, page 6)

Definition at line 6226 of file STM8AF_STM8S.h.

◆ _CAN_BS22

#define _CAN_BS22 ((uint8_t) (0x01 << 6))

CAN Bit segment 2 [2] (in _CAN_BTR2, page 6)

Definition at line 6227 of file STM8AF_STM8S.h.

◆ _CAN_BTR1

#define _CAN_BTR1 _SFR(uint8_t, CAN_AddressBase+0x08+0x04)

CAN bit timing register 1 (page 6)

Definition at line 6037 of file STM8AF_STM8S.h.

◆ _CAN_BTR1_RESET_VALUE

#define _CAN_BTR1_RESET_VALUE ((uint8_t) 0x40)

CAN bit timing register 1 (page 6) reset value.

Definition at line 6081 of file STM8AF_STM8S.h.

◆ _CAN_BTR2

#define _CAN_BTR2 _SFR(uint8_t, CAN_AddressBase+0x08+0x05)

CAN bit timing register 2 (page 6)

Definition at line 6038 of file STM8AF_STM8S.h.

◆ _CAN_BTR2_RESET_VALUE

#define _CAN_BTR2_RESET_VALUE ((uint8_t) 0x23)

CAN bit timing register 2 (page 6) reset value.

Definition at line 6082 of file STM8AF_STM8S.h.

◆ _CAN_CODE

#define _CAN_CODE ((uint8_t) (0x03 << 0))

CAN Mailbox Code [1:0] (in _CAN_TPR)

Definition at line 6118 of file STM8AF_STM8S.h.

◆ _CAN_CODE0

#define _CAN_CODE0 ((uint8_t) (0x01 << 0))

CAN Mailbox Code [0] (in _CAN_TPR)

Definition at line 6119 of file STM8AF_STM8S.h.

◆ _CAN_CODE1

#define _CAN_CODE1 ((uint8_t) (0x01 << 1))

CAN Mailbox Code [1] (in _CAN_TPR)

Definition at line 6120 of file STM8AF_STM8S.h.

◆ _CAN_DGR

#define _CAN_DGR _SFR(uint8_t, CAN_AddressBase+0x06)

CAN diagnosis register.

Definition at line 5953 of file STM8AF_STM8S.h.

◆ _CAN_DGR_RESET_VALUE

#define _CAN_DGR_RESET_VALUE ((uint8_t) 0x0C)

CAN diagnosis register reset value.

Definition at line 6072 of file STM8AF_STM8S.h.

◆ _CAN_DLC

#define _CAN_DLC ((uint8_t) (0x0F << 0))

CAN Data length code [3:0] (in _CAN_MDLCR, page 0,1,5,7)

Definition at line 6171 of file STM8AF_STM8S.h.

◆ _CAN_DLC0

#define _CAN_DLC0 ((uint8_t) (0x01 << 0))

CAN Data length code [0] (in _CAN_MDLCR, page 0,1,5,7)

Definition at line 6172 of file STM8AF_STM8S.h.

◆ _CAN_DLC1

#define _CAN_DLC1 ((uint8_t) (0x01 << 1))

CAN Data length code [1] (in _CAN_MDLCR, page 0,1,5,7)

Definition at line 6173 of file STM8AF_STM8S.h.

◆ _CAN_DLC2

#define _CAN_DLC2 ((uint8_t) (0x01 << 2))

CAN Data length code [2] (in _CAN_MDLCR, page 0,1,5,7)

Definition at line 6174 of file STM8AF_STM8S.h.

◆ _CAN_DLC3

#define _CAN_DLC3 ((uint8_t) (0x01 << 3))

CAN Data length code [3] (in _CAN_MDLCR, page 0,1,5,7)

Definition at line 6175 of file STM8AF_STM8S.h.

◆ _CAN_EIER

#define _CAN_EIER _SFR(uint8_t, CAN_AddressBase+0x08+0x01)

CAN error interrupt enable register (page 6)

Definition at line 6034 of file STM8AF_STM8S.h.

◆ _CAN_EIER_RESET_VALUE

#define _CAN_EIER_RESET_VALUE ((uint8_t) 0x00)

CAN error interrupt enable register (page 6) reset value.

Definition at line 6078 of file STM8AF_STM8S.h.

◆ _CAN_EPVF

#define _CAN_EPVF ((uint8_t) (0x01 << 1))

CAN Error passive flag [0] (in _CAN_ESR, page 6)

Definition at line 6187 of file STM8AF_STM8S.h.

◆ _CAN_EPVIE

#define _CAN_EPVIE ((uint8_t) (0x01 << 1))

CAN Error passive interrupt enable [0] (in _CAN_EIER, page 6)

Definition at line 6198 of file STM8AF_STM8S.h.

◆ _CAN_ERRI

#define _CAN_ERRI ((uint8_t) (0x01 << 2))

CAN Error Interrupt [0] (in _CAN_MSR)

Definition at line 6101 of file STM8AF_STM8S.h.

◆ _CAN_ERRIE

#define _CAN_ERRIE ((uint8_t) (0x01 << 6))

CAN Error interrupt enable [0] (in _CAN_EIER, page 6)

Definition at line 6203 of file STM8AF_STM8S.h.

◆ _CAN_ESR

#define _CAN_ESR _SFR(uint8_t, CAN_AddressBase+0x08+0x00)

CAN error status register (page 6)

Definition at line 6033 of file STM8AF_STM8S.h.

◆ _CAN_ESR_RESET_VALUE

#define _CAN_ESR_RESET_VALUE ((uint8_t) 0x00)

CAN error status register (page 6) reset value.

Definition at line 6077 of file STM8AF_STM8S.h.

◆ _CAN_EWGF

#define _CAN_EWGF ((uint8_t) (0x01 << 0))

CAN Error warning flag [0] (in _CAN_ESR, page 6)

Definition at line 6186 of file STM8AF_STM8S.h.

◆ _CAN_EWGIE

#define _CAN_EWGIE ((uint8_t) (0x01 << 0))

CAN Error warning interrupt enable [0] (in _CAN_EIER, page 6)

Definition at line 6197 of file STM8AF_STM8S.h.

◆ _CAN_F0R1

#define _CAN_F0R1 _SFR(uint8_t, CAN_AddressBase+0x08+0x00)

CAN acceptance filter 0/1 (page 2)

Definition at line 5977 of file STM8AF_STM8S.h.

◆ _CAN_F0R2

#define _CAN_F0R2 _SFR(uint8_t, CAN_AddressBase+0x08+0x01)

CAN acceptance filter 0/2 (page 2)

Definition at line 5978 of file STM8AF_STM8S.h.

◆ _CAN_F0R3

#define _CAN_F0R3 _SFR(uint8_t, CAN_AddressBase+0x08+0x02)

CAN acceptance filter 0/3 (page 2)

Definition at line 5979 of file STM8AF_STM8S.h.

◆ _CAN_F0R4

#define _CAN_F0R4 _SFR(uint8_t, CAN_AddressBase+0x08+0x03)

CAN acceptance filter 0/4 (page 2)

Definition at line 5980 of file STM8AF_STM8S.h.

◆ _CAN_F0R5

#define _CAN_F0R5 _SFR(uint8_t, CAN_AddressBase+0x08+0x04)

CAN acceptance filter 0/5 (page 2)

Definition at line 5981 of file STM8AF_STM8S.h.

◆ _CAN_F0R6

#define _CAN_F0R6 _SFR(uint8_t, CAN_AddressBase+0x08+0x05)

CAN acceptance filter 0/6 (page 2)

Definition at line 5982 of file STM8AF_STM8S.h.

◆ _CAN_F0R7

#define _CAN_F0R7 _SFR(uint8_t, CAN_AddressBase+0x08+0x06)

CAN acceptance filter 0/7 (page 2)

Definition at line 5983 of file STM8AF_STM8S.h.

◆ _CAN_F0R8

#define _CAN_F0R8 _SFR(uint8_t, CAN_AddressBase+0x08+0x07)

CAN acceptance filter 0/8 (page 2)

Definition at line 5984 of file STM8AF_STM8S.h.

◆ _CAN_F1R1

#define _CAN_F1R1 _SFR(uint8_t, CAN_AddressBase+0x08+0x08)

CAN acceptance filter 1/1 (page 2)

Definition at line 5985 of file STM8AF_STM8S.h.

◆ _CAN_F1R2

#define _CAN_F1R2 _SFR(uint8_t, CAN_AddressBase+0x08+0x09)

CAN acceptance filter 1/2 (page 2)

Definition at line 5986 of file STM8AF_STM8S.h.

◆ _CAN_F1R3

#define _CAN_F1R3 _SFR(uint8_t, CAN_AddressBase+0x08+0x0A)

CAN acceptance filter 1/3 (page 2)

Definition at line 5987 of file STM8AF_STM8S.h.

◆ _CAN_F1R4

#define _CAN_F1R4 _SFR(uint8_t, CAN_AddressBase+0x08+0x0B)

CAN acceptance filter 1/4 (page 2)

Definition at line 5988 of file STM8AF_STM8S.h.

◆ _CAN_F1R5

#define _CAN_F1R5 _SFR(uint8_t, CAN_AddressBase+0x08+0x0C)

CAN acceptance filter 1/5 (page 2)

Definition at line 5989 of file STM8AF_STM8S.h.

◆ _CAN_F1R6

#define _CAN_F1R6 _SFR(uint8_t, CAN_AddressBase+0x08+0x0D)

CAN acceptance filter 1/6 (page 2)

Definition at line 5990 of file STM8AF_STM8S.h.

◆ _CAN_F1R7

#define _CAN_F1R7 _SFR(uint8_t, CAN_AddressBase+0x08+0x0E)

CAN acceptance filter 1/7 (page 2)

Definition at line 5991 of file STM8AF_STM8S.h.

◆ _CAN_F1R8

#define _CAN_F1R8 _SFR(uint8_t, CAN_AddressBase+0x08+0x0F)

CAN acceptance filter 1/8 (page 2)

Definition at line 5992 of file STM8AF_STM8S.h.

◆ _CAN_F2R1

#define _CAN_F2R1 _SFR(uint8_t, CAN_AddressBase+0x08+0x00)

CAN acceptance filter 2/1 (page 3)

Definition at line 5995 of file STM8AF_STM8S.h.

◆ _CAN_F2R2

#define _CAN_F2R2 _SFR(uint8_t, CAN_AddressBase+0x08+0x01)

CAN acceptance filter 2/2 (page 3)

Definition at line 5996 of file STM8AF_STM8S.h.

◆ _CAN_F2R3

#define _CAN_F2R3 _SFR(uint8_t, CAN_AddressBase+0x08+0x02)

CAN acceptance filter 2/3 (page 3)

Definition at line 5997 of file STM8AF_STM8S.h.

◆ _CAN_F2R4

#define _CAN_F2R4 _SFR(uint8_t, CAN_AddressBase+0x08+0x03)

CAN acceptance filter 2/4 (page 3)

Definition at line 5998 of file STM8AF_STM8S.h.

◆ _CAN_F2R5

#define _CAN_F2R5 _SFR(uint8_t, CAN_AddressBase+0x08+0x04)

CAN acceptance filter 2/5 (page 3)

Definition at line 5999 of file STM8AF_STM8S.h.

◆ _CAN_F2R6

#define _CAN_F2R6 _SFR(uint8_t, CAN_AddressBase+0x08+0x05)

CAN acceptance filter 2/6 (page 3)

Definition at line 6000 of file STM8AF_STM8S.h.

◆ _CAN_F2R7

#define _CAN_F2R7 _SFR(uint8_t, CAN_AddressBase+0x08+0x06)

CAN acceptance filter 2/7 (page 3)

Definition at line 6001 of file STM8AF_STM8S.h.

◆ _CAN_F2R8

#define _CAN_F2R8 _SFR(uint8_t, CAN_AddressBase+0x08+0x07)

CAN acceptance filter 2/8 (page 3)

Definition at line 6002 of file STM8AF_STM8S.h.

◆ _CAN_F3R1

#define _CAN_F3R1 _SFR(uint8_t, CAN_AddressBase+0x08+0x08)

CAN acceptance filter 3/1 (page 3)

Definition at line 6003 of file STM8AF_STM8S.h.

◆ _CAN_F3R2

#define _CAN_F3R2 _SFR(uint8_t, CAN_AddressBase+0x08+0x09)

CAN acceptance filter 3/2 (page 3)

Definition at line 6004 of file STM8AF_STM8S.h.

◆ _CAN_F3R3

#define _CAN_F3R3 _SFR(uint8_t, CAN_AddressBase+0x08+0x0A)

CAN acceptance filter 3/3 (page 3)

Definition at line 6005 of file STM8AF_STM8S.h.

◆ _CAN_F3R4

#define _CAN_F3R4 _SFR(uint8_t, CAN_AddressBase+0x08+0x0B)

CAN acceptance filter 3/4 (page 3)

Definition at line 6006 of file STM8AF_STM8S.h.

◆ _CAN_F3R5

#define _CAN_F3R5 _SFR(uint8_t, CAN_AddressBase+0x08+0x0C)

CAN acceptance filter 3/5 (page 3)

Definition at line 6007 of file STM8AF_STM8S.h.

◆ _CAN_F3R6

#define _CAN_F3R6 _SFR(uint8_t, CAN_AddressBase+0x08+0x0D)

CAN acceptance filter 3/6 (page 3)

Definition at line 6008 of file STM8AF_STM8S.h.

◆ _CAN_F3R7

#define _CAN_F3R7 _SFR(uint8_t, CAN_AddressBase+0x08+0x0E)

CAN acceptance filter 3/7 (page 3)

Definition at line 6009 of file STM8AF_STM8S.h.

◆ _CAN_F3R8

#define _CAN_F3R8 _SFR(uint8_t, CAN_AddressBase+0x08+0x0F)

CAN acceptance filter 3/8 (page 3)

Definition at line 6010 of file STM8AF_STM8S.h.

◆ _CAN_F4R1

#define _CAN_F4R1 _SFR(uint8_t, CAN_AddressBase+0x08+0x00)

CAN acceptance filter 4/1 (page 4)

Definition at line 6013 of file STM8AF_STM8S.h.

◆ _CAN_F4R2

#define _CAN_F4R2 _SFR(uint8_t, CAN_AddressBase+0x08+0x01)

CAN acceptance filter 4/2 (page 4)

Definition at line 6014 of file STM8AF_STM8S.h.

◆ _CAN_F4R3

#define _CAN_F4R3 _SFR(uint8_t, CAN_AddressBase+0x08+0x02)

CAN acceptance filter 4/3 (page 4)

Definition at line 6015 of file STM8AF_STM8S.h.

◆ _CAN_F4R4

#define _CAN_F4R4 _SFR(uint8_t, CAN_AddressBase+0x08+0x03)

CAN acceptance filter 4/4 (page 4)

Definition at line 6016 of file STM8AF_STM8S.h.

◆ _CAN_F4R5

#define _CAN_F4R5 _SFR(uint8_t, CAN_AddressBase+0x08+0x04)

CAN acceptance filter 4/5 (page 4)

Definition at line 6017 of file STM8AF_STM8S.h.

◆ _CAN_F4R6

#define _CAN_F4R6 _SFR(uint8_t, CAN_AddressBase+0x08+0x05)

CAN acceptance filter 4/6 (page 4)

Definition at line 6018 of file STM8AF_STM8S.h.

◆ _CAN_F4R7

#define _CAN_F4R7 _SFR(uint8_t, CAN_AddressBase+0x08+0x06)

CAN acceptance filter 4/7 (page 4)

Definition at line 6019 of file STM8AF_STM8S.h.

◆ _CAN_F4R8

#define _CAN_F4R8 _SFR(uint8_t, CAN_AddressBase+0x08+0x07)

CAN acceptance filter 4/8 (page 4)

Definition at line 6020 of file STM8AF_STM8S.h.

◆ _CAN_F5R1

#define _CAN_F5R1 _SFR(uint8_t, CAN_AddressBase+0x08+0x08)

CAN acceptance filter 5/1 (page 4)

Definition at line 6021 of file STM8AF_STM8S.h.

◆ _CAN_F5R2

#define _CAN_F5R2 _SFR(uint8_t, CAN_AddressBase+0x08+0x09)

CAN acceptance filter 5/2 (page 4)

Definition at line 6022 of file STM8AF_STM8S.h.

◆ _CAN_F5R3

#define _CAN_F5R3 _SFR(uint8_t, CAN_AddressBase+0x08+0x0A)

CAN acceptance filter 5/3 (page 4)

Definition at line 6023 of file STM8AF_STM8S.h.

◆ _CAN_F5R4

#define _CAN_F5R4 _SFR(uint8_t, CAN_AddressBase+0x08+0x0B)

CAN acceptance filter 5/4 (page 4)

Definition at line 6024 of file STM8AF_STM8S.h.

◆ _CAN_F5R5

#define _CAN_F5R5 _SFR(uint8_t, CAN_AddressBase+0x08+0x0C)

CAN acceptance filter 5/5 (page 4)

Definition at line 6025 of file STM8AF_STM8S.h.

◆ _CAN_F5R6

#define _CAN_F5R6 _SFR(uint8_t, CAN_AddressBase+0x08+0x0D)

CAN acceptance filter 5/6 (page 4)

Definition at line 6026 of file STM8AF_STM8S.h.

◆ _CAN_F5R7

#define _CAN_F5R7 _SFR(uint8_t, CAN_AddressBase+0x08+0x0E)

CAN acceptance filter 5/7 (page 4)

Definition at line 6027 of file STM8AF_STM8S.h.

◆ _CAN_F5R8

#define _CAN_F5R8 _SFR(uint8_t, CAN_AddressBase+0x08+0x0F)

CAN acceptance filter 5/8 (page 4)

Definition at line 6028 of file STM8AF_STM8S.h.

◆ _CAN_FACT0

#define _CAN_FACT0 ((uint8_t) (0x01 << 0))

CAN Filter 0 active [0] (in _CAN_FCR1, page 6)

Definition at line 6248 of file STM8AF_STM8S.h.

◆ _CAN_FACT1

#define _CAN_FACT1 ((uint8_t) (0x01 << 4))

CAN Filter 1 active [0] (in _CAN_FCR1, page 6)

Definition at line 6253 of file STM8AF_STM8S.h.

◆ _CAN_FACT2

#define _CAN_FACT2 ((uint8_t) (0x01 << 0))

CAN Filter 2 active [0] (in _CAN_FCR2, page 6)

Definition at line 6260 of file STM8AF_STM8S.h.

◆ _CAN_FACT3

#define _CAN_FACT3 ((uint8_t) (0x01 << 4))

CAN Filter 3 active [0] (in _CAN_FCR2, page 6)

Definition at line 6265 of file STM8AF_STM8S.h.

◆ _CAN_FACT4

#define _CAN_FACT4 ((uint8_t) (0x01 << 0))

CAN Filter 4 active [0] (in _CAN_FCR3, page 6)

Definition at line 6272 of file STM8AF_STM8S.h.

◆ _CAN_FACT5

#define _CAN_FACT5 ((uint8_t) (0x01 << 4))

CAN Filter 5 active [0] (in _CAN_FCR2, page 6)

Definition at line 6277 of file STM8AF_STM8S.h.

◆ _CAN_FCR1

#define _CAN_FCR1 _SFR(uint8_t, CAN_AddressBase+0x08+0x0A)

CAN filter configuration register 1 (page 6)

Definition at line 6042 of file STM8AF_STM8S.h.

◆ _CAN_FCR2

#define _CAN_FCR2 _SFR(uint8_t, CAN_AddressBase+0x08+0x0B)

CAN filter configuration register 2 (page 6)

Definition at line 6043 of file STM8AF_STM8S.h.

◆ _CAN_FCR3

#define _CAN_FCR3 _SFR(uint8_t, CAN_AddressBase+0x08+0x0C)

CAN filter configuration register 3 (page 6)

Definition at line 6044 of file STM8AF_STM8S.h.

◆ _CAN_FCR_RESET_VALUE

#define _CAN_FCR_RESET_VALUE ((uint8_t) 0x00)

CAN filter configuration register reset value.

Definition at line 6085 of file STM8AF_STM8S.h.

◆ _CAN_FFIE

#define _CAN_FFIE ((uint8_t) (0x01 << 2))

CAN FIFO Full Interrupt Enable [0] (in _CAN_IER)

Definition at line 6141 of file STM8AF_STM8S.h.

◆ _CAN_FMH0

#define _CAN_FMH0 ((uint8_t) (0x01 << 1))

CAN Filter 0 mode high [0] (in _CAN_FMR1, page 6)

Definition at line 6232 of file STM8AF_STM8S.h.

◆ _CAN_FMH1

#define _CAN_FMH1 ((uint8_t) (0x01 << 3))

CAN Filter 1 mode high [0] (in _CAN_FMR1, page 6)

Definition at line 6234 of file STM8AF_STM8S.h.

◆ _CAN_FMH2

#define _CAN_FMH2 ((uint8_t) (0x01 << 5))

CAN Filter 2 mode high [0] (in _CAN_FMR1, page 6)

Definition at line 6236 of file STM8AF_STM8S.h.

◆ _CAN_FMH3

#define _CAN_FMH3 ((uint8_t) (0x01 << 7))

CAN Filter 3 mode high [0] (in _CAN_FMR1, page 6)

Definition at line 6238 of file STM8AF_STM8S.h.

◆ _CAN_FMH4

#define _CAN_FMH4 ((uint8_t) (0x01 << 1))

CAN Filter 4 mode high [0] (in _CAN_FMR2, page 6)

Definition at line 6242 of file STM8AF_STM8S.h.

◆ _CAN_FMH5

#define _CAN_FMH5 ((uint8_t) (0x01 << 3))

CAN Filter 5 mode high [0] (in _CAN_FMR2, page 6)

Definition at line 6244 of file STM8AF_STM8S.h.

◆ _CAN_FML0

#define _CAN_FML0 ((uint8_t) (0x01 << 0))

CAN Filter 0 mode low [0] (in _CAN_FMR1, page 6)

Definition at line 6231 of file STM8AF_STM8S.h.

◆ _CAN_FML1

#define _CAN_FML1 ((uint8_t) (0x01 << 2))

CAN Filter 1 mode low [0] (in _CAN_FMR1, page 6)

Definition at line 6233 of file STM8AF_STM8S.h.

◆ _CAN_FML2

#define _CAN_FML2 ((uint8_t) (0x01 << 4))

CAN Filter 2 mode low [0] (in _CAN_FMR1, page 6)

Definition at line 6235 of file STM8AF_STM8S.h.

◆ _CAN_FML3

#define _CAN_FML3 ((uint8_t) (0x01 << 6))

CAN Filter 3 mode low [0] (in _CAN_FMR1, page 6)

Definition at line 6237 of file STM8AF_STM8S.h.

◆ _CAN_FML4

#define _CAN_FML4 ((uint8_t) (0x01 << 0))

CAN Filter 4 mode low [0] (in _CAN_FMR2, page 6)

Definition at line 6241 of file STM8AF_STM8S.h.

◆ _CAN_FML5

#define _CAN_FML5 ((uint8_t) (0x01 << 2))

CAN Filter 5 mode low [0] (in _CAN_FMR2, page 6)

Definition at line 6243 of file STM8AF_STM8S.h.

◆ _CAN_FMP

#define _CAN_FMP ((uint8_t) (0x03 << 0))

CAN FIFO Message Pending [1:0] (in _CAN_RFR)

Definition at line 6129 of file STM8AF_STM8S.h.

◆ _CAN_FMP0

#define _CAN_FMP0 ((uint8_t) (0x01 << 0))

CAN FIFO Message Pending [0] (in _CAN_RFR)

Definition at line 6130 of file STM8AF_STM8S.h.

◆ _CAN_FMP1

#define _CAN_FMP1 ((uint8_t) (0x01 << 1))

CAN FIFO Message Pending [1] (in _CAN_RFR)

Definition at line 6131 of file STM8AF_STM8S.h.

◆ _CAN_FMPIE

#define _CAN_FMPIE ((uint8_t) (0x01 << 1))

CAN FIFO Message Pending Interrupt Enable [0] (in _CAN_IER)

Definition at line 6140 of file STM8AF_STM8S.h.

◆ _CAN_FMR1

#define _CAN_FMR1 _SFR(uint8_t, CAN_AddressBase+0x08+0x08)

CAN filter mode register 1 (page 6)

Definition at line 6040 of file STM8AF_STM8S.h.

◆ _CAN_FMR1_RESET_VALUE

#define _CAN_FMR1_RESET_VALUE ((uint8_t) 0x00)

CAN filter mode register 1 (page 6) reset value.

Definition at line 6083 of file STM8AF_STM8S.h.

◆ _CAN_FMR2

#define _CAN_FMR2 _SFR(uint8_t, CAN_AddressBase+0x08+0x09)

CAN filter mode register 2 (page 6)

Definition at line 6041 of file STM8AF_STM8S.h.

◆ _CAN_FMR2_RESET_VALUE

#define _CAN_FMR2_RESET_VALUE ((uint8_t) 0x00)

CAN filter mode register 2 (page 6) reset value.

Definition at line 6084 of file STM8AF_STM8S.h.

◆ _CAN_FOVIE

#define _CAN_FOVIE ((uint8_t) (0x01 << 3))

CAN FIFO Overrun Interrupt Enable [0] (in _CAN_IER)

Definition at line 6142 of file STM8AF_STM8S.h.

◆ _CAN_FOVR

#define _CAN_FOVR ((uint8_t) (0x01 << 4))

CAN FIFO Overrun [0] (in _CAN_RFR)

Definition at line 6134 of file STM8AF_STM8S.h.

◆ _CAN_FSC0

#define _CAN_FSC0 ((uint8_t) (0x03 << 1))

CAN Filter 0 scale configuration [1:0] (in _CAN_FCR1, page 6)

Definition at line 6249 of file STM8AF_STM8S.h.

◆ _CAN_FSC00

#define _CAN_FSC00 ((uint8_t) (0x01 << 1))

CAN Filter 0 scale configuration [0] (in _CAN_FCR1, page 6)

Definition at line 6250 of file STM8AF_STM8S.h.

◆ _CAN_FSC01

#define _CAN_FSC01 ((uint8_t) (0x01 << 2))

CAN Filter 0 scale configuration [1] (in _CAN_FCR1, page 6)

Definition at line 6251 of file STM8AF_STM8S.h.

◆ _CAN_FSC1

#define _CAN_FSC1 ((uint8_t) (0x03 << 5))

CAN Filter 1 scale configuration [1:0] (in _CAN_FCR1, page 6)

Definition at line 6254 of file STM8AF_STM8S.h.

◆ _CAN_FSC10

#define _CAN_FSC10 ((uint8_t) (0x01 << 5))

CAN Filter 1 scale configuration [0] (in _CAN_FCR1, page 6)

Definition at line 6255 of file STM8AF_STM8S.h.

◆ _CAN_FSC11

#define _CAN_FSC11 ((uint8_t) (0x01 << 6))

CAN Filter 1 scale configuration [1] (in _CAN_FCR1, page 6)

Definition at line 6256 of file STM8AF_STM8S.h.

◆ _CAN_FSC2

#define _CAN_FSC2 ((uint8_t) (0x03 << 1))

CAN Filter 2 scale configuration [1:0] (in _CAN_FCR2, page 6)

Definition at line 6261 of file STM8AF_STM8S.h.

◆ _CAN_FSC20

#define _CAN_FSC20 ((uint8_t) (0x01 << 1))

CAN Filter 2 scale configuration [0] (in _CAN_FCR2, page 6)

Definition at line 6262 of file STM8AF_STM8S.h.

◆ _CAN_FSC21

#define _CAN_FSC21 ((uint8_t) (0x01 << 2))

CAN Filter 2 scale configuration [1] (in _CAN_FCR2, page 6)

Definition at line 6263 of file STM8AF_STM8S.h.

◆ _CAN_FSC3

#define _CAN_FSC3 ((uint8_t) (0x03 << 5))

CAN Filter 3 scale configuration [1:0] (in _CAN_FCR2, page 6)

Definition at line 6266 of file STM8AF_STM8S.h.

◆ _CAN_FSC30

#define _CAN_FSC30 ((uint8_t) (0x01 << 5))

CAN Filter 3 scale configuration [0] (in _CAN_FCR2, page 6)

Definition at line 6267 of file STM8AF_STM8S.h.

◆ _CAN_FSC31

#define _CAN_FSC31 ((uint8_t) (0x01 << 6))

CAN Filter 3 scale configuration [1] (in _CAN_FCR2, page 6)

Definition at line 6268 of file STM8AF_STM8S.h.

◆ _CAN_FSC4

#define _CAN_FSC4 ((uint8_t) (0x03 << 1))

CAN Filter 4 scale configuration [1:0] (in _CAN_FCR3, page 6)

Definition at line 6273 of file STM8AF_STM8S.h.

◆ _CAN_FSC40

#define _CAN_FSC40 ((uint8_t) (0x01 << 1))

CAN Filter 4 scale configuration [0] (in _CAN_FCR3, page 6)

Definition at line 6274 of file STM8AF_STM8S.h.

◆ _CAN_FSC41

#define _CAN_FSC41 ((uint8_t) (0x01 << 2))

CAN Filter 4 scale configuration [1] (in _CAN_FCR3, page 6)

Definition at line 6275 of file STM8AF_STM8S.h.

◆ _CAN_FSC5

#define _CAN_FSC5 ((uint8_t) (0x03 << 5))

CAN Filter 5 scale configuration [1:0] (in _CAN_FCR3, page 6)

Definition at line 6278 of file STM8AF_STM8S.h.

◆ _CAN_FSC50

#define _CAN_FSC50 ((uint8_t) (0x01 << 5))

CAN Filter 5 scale configuration [0] (in _CAN_FCR3, page 6)

Definition at line 6279 of file STM8AF_STM8S.h.

◆ _CAN_FSC51

#define _CAN_FSC51 ((uint8_t) (0x01 << 6))

CAN Filter 5 scale configuration [1] (in _CAN_FCR3, page 6)

Definition at line 6280 of file STM8AF_STM8S.h.

◆ _CAN_FULL

#define _CAN_FULL ((uint8_t) (0x01 << 3))

CAN FIFO Full [0] (in _CAN_RFR)

Definition at line 6133 of file STM8AF_STM8S.h.

◆ _CAN_IDE

#define _CAN_IDE ((uint8_t) (0x01 << 6))

CAN Extended identifier [0] (in _CAN_MIDR1, page 0,1,5)

Definition at line 6182 of file STM8AF_STM8S.h.

◆ _CAN_IER

#define _CAN_IER _SFR(uint8_t, CAN_AddressBase+0x05)

CAN interrupt enable register.

Definition at line 5952 of file STM8AF_STM8S.h.

◆ _CAN_IER_RESET_VALUE

#define _CAN_IER_RESET_VALUE ((uint8_t) 0x00)

CAN interrupt enable register reset value.

Definition at line 6071 of file STM8AF_STM8S.h.

◆ _CAN_INAK

#define _CAN_INAK ((uint8_t) (0x01 << 0))

CAN Initialization Acknowledge [0] (in _CAN_MSR)

Definition at line 6099 of file STM8AF_STM8S.h.

◆ _CAN_INRQ

#define _CAN_INRQ ((uint8_t) (0x01 << 0))

CAN Channel Initialization Request [0] (in _CAN_MCR)

Definition at line 6089 of file STM8AF_STM8S.h.

◆ _CAN_LBKM

#define _CAN_LBKM ((uint8_t) (0x01 << 0))

CAN Loop back mode [0] (in _CAN_DGR)

Definition at line 6147 of file STM8AF_STM8S.h.

◆ _CAN_LEC

#define _CAN_LEC ((uint8_t) (0x07 << 4))

CAN Last error code [2:0] (in _CAN_ESR, page 6)

Definition at line 6190 of file STM8AF_STM8S.h.

◆ _CAN_LEC0

#define _CAN_LEC0 ((uint8_t) (0x01 << 4))

CAN Last error code [0] (in _CAN_ESR, page 6)

Definition at line 6191 of file STM8AF_STM8S.h.

◆ _CAN_LEC1

#define _CAN_LEC1 ((uint8_t) (0x01 << 5))

CAN Last error code [1] (in _CAN_ESR, page 6)

Definition at line 6192 of file STM8AF_STM8S.h.

◆ _CAN_LEC2

#define _CAN_LEC2 ((uint8_t) (0x01 << 6))

CAN Last error code [3] (in _CAN_ESR, page 6)

Definition at line 6193 of file STM8AF_STM8S.h.

◆ _CAN_LECIE

#define _CAN_LECIE ((uint8_t) (0x01 << 4))

CAN Last error code interrupt enable [0] (in _CAN_EIER, page 6)

Definition at line 6201 of file STM8AF_STM8S.h.

◆ _CAN_LOW0

#define _CAN_LOW0 ((uint8_t) (0x01 << 5))

CAN Lowest Priority Flag for Mailbox 0 [0] (in _CAN_TPR)

Definition at line 6124 of file STM8AF_STM8S.h.

◆ _CAN_LOW1

#define _CAN_LOW1 ((uint8_t) (0x01 << 6))

CAN Lowest Priority Flag for Mailbox 1 [0] (in _CAN_TPR)

Definition at line 6125 of file STM8AF_STM8S.h.

◆ _CAN_LOW2

#define _CAN_LOW2 ((uint8_t) (0x01 << 7))

CAN Lowest Priority Flag for Mailbox 2 [0] (in _CAN_TPR)

Definition at line 6126 of file STM8AF_STM8S.h.

◆ _CAN_MCR

#define _CAN_MCR _SFR(uint8_t, CAN_AddressBase+0x00)

CAN master control register.

Definition at line 5947 of file STM8AF_STM8S.h.

◆ _CAN_MCR_RESET_VALUE

#define _CAN_MCR_RESET_VALUE ((uint8_t) 0x02)

CAN master control register reset value.

Definition at line 6066 of file STM8AF_STM8S.h.

◆ _CAN_MCSR

#define _CAN_MCSR _SFR(uint8_t, CAN_AddressBase+0x08+0x00)

CAN message control/status register (page 0,1,5)

Definition at line 5957 of file STM8AF_STM8S.h.

◆ _CAN_MCSR_RESET_VALUE

#define _CAN_MCSR_RESET_VALUE ((uint8_t) 0x00)

CAN message control/status register (page 0,1,5) reset value.

Definition at line 6075 of file STM8AF_STM8S.h.

◆ _CAN_MDAR1

#define _CAN_MDAR1 _SFR(uint8_t, CAN_AddressBase+0x08+0x06)

CAN mailbox data register 1 (page 0,1,5,7) */.

Definition at line 5963 of file STM8AF_STM8S.h.

◆ _CAN_MDAR2

#define _CAN_MDAR2 _SFR(uint8_t, CAN_AddressBase+0x08+0x07)

CAN mailbox data register 2 (page 0,1,5,7) */.

Definition at line 5964 of file STM8AF_STM8S.h.

◆ _CAN_MDAR3

#define _CAN_MDAR3 _SFR(uint8_t, CAN_AddressBase+0x08+0x08)

CAN mailbox data register 3 (page 0,1,5,7) */.

Definition at line 5965 of file STM8AF_STM8S.h.

◆ _CAN_MDAR4

#define _CAN_MDAR4 _SFR(uint8_t, CAN_AddressBase+0x08+0x09)

CAN mailbox data register 4 (page 0,1,5,7) */.

Definition at line 5966 of file STM8AF_STM8S.h.

◆ _CAN_MDAR5

#define _CAN_MDAR5 _SFR(uint8_t, CAN_AddressBase+0x08+0x0A)

CAN mailbox data register 5 (page 0,1,5,7) */.

Definition at line 5967 of file STM8AF_STM8S.h.

◆ _CAN_MDAR6

#define _CAN_MDAR6 _SFR(uint8_t, CAN_AddressBase+0x08+0x0B)

CAN mailbox data register 6 (page 0,1,5,7) */.

Definition at line 5968 of file STM8AF_STM8S.h.

◆ _CAN_MDAR7

#define _CAN_MDAR7 _SFR(uint8_t, CAN_AddressBase+0x08+0x0C)

CAN mailbox data register 7 (page 0,1,5,7) */.

Definition at line 5969 of file STM8AF_STM8S.h.

◆ _CAN_MDAR8

#define _CAN_MDAR8 _SFR(uint8_t, CAN_AddressBase+0x08+0x0D)

CAN mailbox data register 8 (page 0,1,5,7) */.

Definition at line 5970 of file STM8AF_STM8S.h.

◆ _CAN_MDLCR

#define _CAN_MDLCR _SFR(uint8_t, CAN_AddressBase+0x08+0x01)

CAN mailbox data length control register (page 0,1,5,7)

Definition at line 5958 of file STM8AF_STM8S.h.

◆ _CAN_MDLCR_RESET_VALUE

#define _CAN_MDLCR_RESET_VALUE ((uint8_t) 0x00)

CAN mailbox data length control register (page 0,1,5,7) reset value.

Definition at line 6076 of file STM8AF_STM8S.h.

◆ _CAN_MFMIR

#define _CAN_MFMIR _SFR(uint8_t, CAN_AddressBase+0x08+0x00)

CAN mailbox filter match index register (page 7)

Definition at line 6048 of file STM8AF_STM8S.h.

◆ _CAN_MFMIR_RESET_VALUE

#define _CAN_MFMIR_RESET_VALUE ((uint8_t) 0x00)

CAN mailbox filter match index register reset value.

Definition at line 6086 of file STM8AF_STM8S.h.

◆ _CAN_MIDR1

#define _CAN_MIDR1 _SFR(uint8_t, CAN_AddressBase+0x08+0x02)

CAN mailbox identifier register 1 (page 0,1,5,7)

Definition at line 5959 of file STM8AF_STM8S.h.

◆ _CAN_MIDR2

#define _CAN_MIDR2 _SFR(uint8_t, CAN_AddressBase+0x08+0x03)

CAN mailbox identifier register 2 (page 0,1,5,7)

Definition at line 5960 of file STM8AF_STM8S.h.

◆ _CAN_MIDR3

#define _CAN_MIDR3 _SFR(uint8_t, CAN_AddressBase+0x08+0x04)

CAN mailbox identifier register 3 (page 0,1,5,7)

Definition at line 5961 of file STM8AF_STM8S.h.

◆ _CAN_MIDR4

#define _CAN_MIDR4 _SFR(uint8_t, CAN_AddressBase+0x08+0x05)

CAN mailbox identifier register 4 (page 0,1,5,7)

Definition at line 5962 of file STM8AF_STM8S.h.

◆ _CAN_MSR

#define _CAN_MSR _SFR(uint8_t, CAN_AddressBase+0x01)

CAN master status register.

Definition at line 5948 of file STM8AF_STM8S.h.

◆ _CAN_MSR_RESET_VALUE

#define _CAN_MSR_RESET_VALUE ((uint8_t) 0x02)

CAN master status register reset value.

Definition at line 6067 of file STM8AF_STM8S.h.

◆ _CAN_MTSRH

#define _CAN_MTSRH _SFR(uint8_t, CAN_AddressBase+0x08+0x0F)

CAN mailbox time stamp register high byte (page 0,1,5,7) */.

Definition at line 5972 of file STM8AF_STM8S.h.

◆ _CAN_MTSRL

#define _CAN_MTSRL _SFR(uint8_t, CAN_AddressBase+0x08+0x0E)

CAN mailbox time stamp register low byte (page 0,1,5,7) */.

Definition at line 5971 of file STM8AF_STM8S.h.

◆ _CAN_NART

#define _CAN_NART ((uint8_t) (0x01 << 4))

CAN Channel No Automatic Retransmission [0] (in _CAN_MCR)

Definition at line 6093 of file STM8AF_STM8S.h.

◆ _CAN_PS

#define _CAN_PS ((uint8_t) (0x07 << 0))

CAN Page select [2:0] (in _CAN_PSR)

Definition at line 6155 of file STM8AF_STM8S.h.

◆ _CAN_PS0

#define _CAN_PS0 ((uint8_t) (0x01 << 0))

CAN Page select [0] (in _CAN_PSR)

Definition at line 6156 of file STM8AF_STM8S.h.

◆ _CAN_PS1

#define _CAN_PS1 ((uint8_t) (0x01 << 1))

CAN Page select [1] (in _CAN_PSR)

Definition at line 6157 of file STM8AF_STM8S.h.

◆ _CAN_PS2

#define _CAN_PS2 ((uint8_t) (0x01 << 2))

CAN Page select [2] (in _CAN_PSR)

Definition at line 6158 of file STM8AF_STM8S.h.

◆ _CAN_PSR

#define _CAN_PSR _SFR(uint8_t, CAN_AddressBase+0x07)

CAN page selection for below paged registers.

Definition at line 5954 of file STM8AF_STM8S.h.

◆ _CAN_PSR_RESET_VALUE

#define _CAN_PSR_RESET_VALUE ((uint8_t) 0x00)

CAN page selection reset value.

Definition at line 6073 of file STM8AF_STM8S.h.

◆ _CAN_RECR

#define _CAN_RECR _SFR(uint8_t, CAN_AddressBase+0x08+0x03)

CAN receive error counter register (page 6)

Definition at line 6036 of file STM8AF_STM8S.h.

◆ _CAN_RECR_RESET_VALUE

#define _CAN_RECR_RESET_VALUE ((uint8_t) 0x00)

CAN receive error counter register (page 6) reset value.

Definition at line 6080 of file STM8AF_STM8S.h.

◆ _CAN_RFLM

#define _CAN_RFLM ((uint8_t) (0x01 << 3))

CAN Channel Receive FIFO Locked Mode [0] (in _CAN_MCR)

Definition at line 6092 of file STM8AF_STM8S.h.

◆ _CAN_RFOM

#define _CAN_RFOM ((uint8_t) (0x01 << 5))

CAN Release FIFO Output Mailbox [0] (in _CAN_RFR)

Definition at line 6135 of file STM8AF_STM8S.h.

◆ _CAN_RFR

#define _CAN_RFR _SFR(uint8_t, CAN_AddressBase+0x04)

CAN receive FIFO register.

Definition at line 5951 of file STM8AF_STM8S.h.

◆ _CAN_RFR_RESET_VALUE

#define _CAN_RFR_RESET_VALUE ((uint8_t) 0x00)

CAN receive FIFO register reset value.

Definition at line 6070 of file STM8AF_STM8S.h.

◆ _CAN_RQCP

#define _CAN_RQCP ((uint8_t) (0x01 << 2))

CAN Request completed [0] (in _CAN_MCSR, page 0,1,5)

Definition at line 6164 of file STM8AF_STM8S.h.

◆ _CAN_RQCP0

#define _CAN_RQCP0 ((uint8_t) (0x01 << 0))

CAN Request Completed for Mailbox 0 [0] (in _CAN_TSR)

Definition at line 6108 of file STM8AF_STM8S.h.

◆ _CAN_RQCP1

#define _CAN_RQCP1 ((uint8_t) (0x01 << 1))

CAN Request Completed for Mailbox 1 [0] (in _CAN_TSR)

Definition at line 6109 of file STM8AF_STM8S.h.

◆ _CAN_RQCP2

#define _CAN_RQCP2 ((uint8_t) (0x01 << 2))

CAN Request Completed for Mailbox 2 [0] (in _CAN_TSR)

Definition at line 6110 of file STM8AF_STM8S.h.

◆ _CAN_RTR

#define _CAN_RTR ((uint8_t) (0x01 << 5))

CAN Remote transmission request [0] (in _CAN_MIDR1, page 0,1,5)

Definition at line 6181 of file STM8AF_STM8S.h.

◆ _CAN_RX

#define _CAN_RX ((uint8_t) (0x01 << 5))

CAN Receive [0] (in _CAN_MSR)

Definition at line 6104 of file STM8AF_STM8S.h.

◆ _CAN_RXS

#define _CAN_RXS ((uint8_t) (0x01 << 3))

CAN Rx Signal (=pin status) [0] (in _CAN_DGR)

Definition at line 6150 of file STM8AF_STM8S.h.

◆ _CAN_SAMP

#define _CAN_SAMP ((uint8_t) (0x01 << 2))

CAN Last sample point [0] (in _CAN_DGR)

Definition at line 6149 of file STM8AF_STM8S.h.

◆ _CAN_SILM

#define _CAN_SILM ((uint8_t) (0x01 << 1))

CAN Silent mode [0] (in _CAN_DGR)

Definition at line 6148 of file STM8AF_STM8S.h.

◆ _CAN_SJW

#define _CAN_SJW ((uint8_t) (0x03 << 6))

CAN Resynchronization jump width [1:0] (in _CAN_EIER, page 6)

Definition at line 6214 of file STM8AF_STM8S.h.

◆ _CAN_SJW0

#define _CAN_SJW0 ((uint8_t) (0x01 << 6))

CAN Resynchronization jump width [0] (in _CAN_EIER, page 6)

Definition at line 6215 of file STM8AF_STM8S.h.

◆ _CAN_SJW1

#define _CAN_SJW1 ((uint8_t) (0x01 << 7))

CAN Resynchronization jump width [1] (in _CAN_EIER, page 6)

Definition at line 6216 of file STM8AF_STM8S.h.

◆ _CAN_SLAK

#define _CAN_SLAK ((uint8_t) (0x01 << 1))

CAN Sleep Acknowledge [0] (in _CAN_MSR)

Definition at line 6100 of file STM8AF_STM8S.h.

◆ _CAN_SLEEP

#define _CAN_SLEEP ((uint8_t) (0x01 << 1))

CAN Channel Sleep Mode Request [0] (in _CAN_MCR)

Definition at line 6090 of file STM8AF_STM8S.h.

◆ _CAN_TECR

#define _CAN_TECR _SFR(uint8_t, CAN_AddressBase+0x08+0x02)

CAN transmit error counter register (page 6)

Definition at line 6035 of file STM8AF_STM8S.h.

◆ _CAN_TECR_RESET_VALUE

#define _CAN_TECR_RESET_VALUE ((uint8_t) 0x00)

CAN transmit error counter register (page 6) reset value.

Definition at line 6079 of file STM8AF_STM8S.h.

◆ _CAN_TERR

#define _CAN_TERR ((uint8_t) (0x01 << 5))

CAN Transmission error [0] (in _CAN_MCSR, page 0,1,5)

Definition at line 6167 of file STM8AF_STM8S.h.

◆ _CAN_TGT

#define _CAN_TGT ((uint8_t) (0x01 << 7))

CAN Transmit global time [0] (in _CAN_MDLCR, page 0,1,5,7)

Definition at line 6177 of file STM8AF_STM8S.h.

◆ _CAN_TME0

#define _CAN_TME0 ((uint8_t) (0x01 << 2))

CAN Transmit Mailbox 0 Empty [0] (in _CAN_TPR)

Definition at line 6121 of file STM8AF_STM8S.h.

◆ _CAN_TME1

#define _CAN_TME1 ((uint8_t) (0x01 << 3))

CAN Transmit Mailbox 1 Empty [0] (in _CAN_TPR)

Definition at line 6122 of file STM8AF_STM8S.h.

◆ _CAN_TME2

#define _CAN_TME2 ((uint8_t) (0x01 << 4))

CAN Transmit Mailbox 2 Empty [0] (in _CAN_TPR)

Definition at line 6123 of file STM8AF_STM8S.h.

◆ _CAN_TMEIE

#define _CAN_TMEIE ((uint8_t) (0x01 << 0))

CAN Transmit Mailbox Empty Interrupt Enable [0] (in _CAN_IER)

Definition at line 6139 of file STM8AF_STM8S.h.

◆ _CAN_TPR

#define _CAN_TPR _SFR(uint8_t, CAN_AddressBase+0x03)

CAN transmit priority register.

Definition at line 5950 of file STM8AF_STM8S.h.

◆ _CAN_TPR_RESET_VALUE

#define _CAN_TPR_RESET_VALUE ((uint8_t) 0x0C)

CAN transmit priority register reset value.

Definition at line 6069 of file STM8AF_STM8S.h.

◆ _CAN_TSR

#define _CAN_TSR _SFR(uint8_t, CAN_AddressBase+0x02)

CAN transmit status register.

Definition at line 5949 of file STM8AF_STM8S.h.

◆ _CAN_TSR_RESET_VALUE

#define _CAN_TSR_RESET_VALUE ((uint8_t) 0x00)

CAN transmit status register reset value.

Definition at line 6068 of file STM8AF_STM8S.h.

◆ _CAN_TTCM

#define _CAN_TTCM ((uint8_t) (0x01 << 7))

CAN Channel Time Triggered Communication Mode [0] (in _CAN_MCR)

Definition at line 6096 of file STM8AF_STM8S.h.

◆ _CAN_TX

#define _CAN_TX ((uint8_t) (0x01 << 4))

CAN Transmit [0] (in _CAN_MSR)

Definition at line 6103 of file STM8AF_STM8S.h.

◆ _CAN_TXFP

#define _CAN_TXFP ((uint8_t) (0x01 << 2))

CAN Channel Transmit FIFO Priority [0] (in _CAN_MCR)

Definition at line 6091 of file STM8AF_STM8S.h.

◆ _CAN_TXM2E

#define _CAN_TXM2E ((uint8_t) (0x01 << 4))

CAN TX Mailbox 2 enable [0] (in _CAN_DGR)

Definition at line 6151 of file STM8AF_STM8S.h.

◆ _CAN_TXOK

#define _CAN_TXOK ((uint8_t) (0x01 << 3))

CAN Transmission OK [0] (in _CAN_MCSR, page 0,1,5)

Definition at line 6165 of file STM8AF_STM8S.h.

◆ _CAN_TXOK0

#define _CAN_TXOK0 ((uint8_t) (0x01 << 4))

CAN Transmission ok for Mailbox 0 [0] (in _CAN_TSR)

Definition at line 6112 of file STM8AF_STM8S.h.

◆ _CAN_TXOK1

#define _CAN_TXOK1 ((uint8_t) (0x01 << 5))

CAN Transmission ok for Mailbox 1 [0] (in _CAN_TSR)

Definition at line 6113 of file STM8AF_STM8S.h.

◆ _CAN_TXOK2

#define _CAN_TXOK2 ((uint8_t) (0x01 << 6))

CAN Transmission ok for Mailbox 2 [0] (in _CAN_TSR)

Definition at line 6114 of file STM8AF_STM8S.h.

◆ _CAN_TXRQ

#define _CAN_TXRQ ((uint8_t) (0x01 << 0))

CAN Transmission mailbox request [0] (in _CAN_MCSR, page 0,1,5)

Definition at line 6162 of file STM8AF_STM8S.h.

◆ _CAN_WKUI

#define _CAN_WKUI ((uint8_t) (0x01 << 3))

CAN Wakeup Interrupt [0] (in _CAN_MSR)

Definition at line 6102 of file STM8AF_STM8S.h.

◆ _CAN_WKUIE

#define _CAN_WKUIE ((uint8_t) (0x01 << 7))

CAN Wakeup Interrupt Enable [0] (in _CAN_IER)

Definition at line 6144 of file STM8AF_STM8S.h.

◆ _CFG

#define _CFG _SFR(CFG_t, CFG_AddressBase)

CFG struct/bit access.

Definition at line 6305 of file STM8AF_STM8S.h.

◆ _CFG_AL

#define _CFG_AL ((uint8_t) (0x01 << 1))

Activation level [0].

Definition at line 6313 of file STM8AF_STM8S.h.

◆ _CFG_GCR

#define _CFG_GCR _SFR(uint8_t, CFG_AddressBase+0x00)

Global configuration register (CFG_GCR)

Definition at line 6306 of file STM8AF_STM8S.h.

◆ _CFG_GCR_RESET_VALUE

#define _CFG_GCR_RESET_VALUE ((uint8_t)0x00)

Definition at line 6309 of file STM8AF_STM8S.h.

◆ _CFG_SWD

#define _CFG_SWD ((uint8_t) (0x01 << 0))

SWIM disable [0].

Definition at line 6312 of file STM8AF_STM8S.h.

◆ _CLK

#define _CLK _SFR(CLK_t, CLK_AddressBase)

Clock module struct/bit access.

Definition at line 865 of file STM8AF_STM8S.h.

◆ _CLK_ADC

#define _CLK_ADC ((uint8_t) (0x01 << 3))

clock enable ADC [0] (in _CLK_PCKENR2)

Definition at line 962 of file STM8AF_STM8S.h.

◆ _CLK_AUX

#define _CLK_AUX ((uint8_t) (0x01 << 1))

Auxiliary oscillator connected to master clock [0] (in _CLK_CSSR)

Definition at line 943 of file STM8AF_STM8S.h.

◆ _CLK_AWU

#define _CLK_AWU ((uint8_t) (0x01 << 2))

clock enable AWU [0] (in _CLK_PCKENR2)

Definition at line 961 of file STM8AF_STM8S.h.

◆ _CLK_CAN

#define _CLK_CAN ((uint8_t) (0x01 << 7))

clock enable CAN [0] (in _CLK_PCKENR2)

Definition at line 964 of file STM8AF_STM8S.h.

◆ _CLK_CCOBSY

#define _CLK_CCOBSY ((uint8_t) (0x01 << 6))

Configurable clock output busy [0] (in _CLK_CCOR)

Definition at line 956 of file STM8AF_STM8S.h.

◆ _CLK_CCOEN

#define _CLK_CCOEN ((uint8_t) (0x01 << 0))

Configurable clock output enable [0] (in _CLK_CCOR)

Definition at line 949 of file STM8AF_STM8S.h.

◆ _CLK_CCOR

#define _CLK_CCOR _SFR(uint8_t, CLK_AddressBase+0x09)

Configurable clock output register.

Definition at line 875 of file STM8AF_STM8S.h.

◆ _CLK_CCOR_RESET_VALUE

#define _CLK_CCOR_RESET_VALUE ((uint8_t) 0x00)

Configurable clock output register reset value.

Definition at line 891 of file STM8AF_STM8S.h.

◆ _CLK_CCORDY

#define _CLK_CCORDY ((uint8_t) (0x01 << 5))

Configurable clock output ready [0] (in _CLK_CCOR)

Definition at line 955 of file STM8AF_STM8S.h.

◆ _CLK_CCOSEL

#define _CLK_CCOSEL ((uint8_t) (0x0F << 1))

Configurable clock output selection [3:0] (in _CLK_CCOR)

Definition at line 950 of file STM8AF_STM8S.h.

◆ _CLK_CCOSEL0

#define _CLK_CCOSEL0 ((uint8_t) (0x01 << 1))

Configurable clock output selection [0] (in _CLK_CCOR)

Definition at line 951 of file STM8AF_STM8S.h.

◆ _CLK_CCOSEL1

#define _CLK_CCOSEL1 ((uint8_t) (0x01 << 2))

Configurable clock output selection [1] (in _CLK_CCOR)

Definition at line 952 of file STM8AF_STM8S.h.

◆ _CLK_CCOSEL2

#define _CLK_CCOSEL2 ((uint8_t) (0x01 << 3))

Configurable clock output selection [2] (in _CLK_CCOR)

Definition at line 953 of file STM8AF_STM8S.h.

◆ _CLK_CCOSEL3

#define _CLK_CCOSEL3 ((uint8_t) (0x01 << 4))

Configurable clock output selection [3] (in _CLK_CCOR)

Definition at line 954 of file STM8AF_STM8S.h.

◆ _CLK_CKDIVR

#define _CLK_CKDIVR _SFR(uint8_t, CLK_AddressBase+0x06)

Clock divider register.

Definition at line 872 of file STM8AF_STM8S.h.

◆ _CLK_CKDIVR_RESET_VALUE

#define _CLK_CKDIVR_RESET_VALUE ((uint8_t) 0x18)

Clock divider register reset value.

Definition at line 887 of file STM8AF_STM8S.h.

◆ _CLK_CMSR

#define _CLK_CMSR _SFR(uint8_t, CLK_AddressBase+0x03)

Clock master status register.

Definition at line 869 of file STM8AF_STM8S.h.

◆ _CLK_CMSR_RESET_VALUE

#define _CLK_CMSR_RESET_VALUE ((uint8_t) 0xE1)

Clock master status reset value.

Definition at line 884 of file STM8AF_STM8S.h.

◆ _CLK_CPUDIV

#define _CLK_CPUDIV ((uint8_t) (0x07 << 0))

CPU clock prescaler [2:0] (in _CLK_CKDIVR)

Definition at line 922 of file STM8AF_STM8S.h.

◆ _CLK_CPUDIV0

#define _CLK_CPUDIV0 ((uint8_t) (0x01 << 0))

CPU clock prescaler [0] (in _CLK_CKDIVR)

Definition at line 923 of file STM8AF_STM8S.h.

◆ _CLK_CPUDIV1

#define _CLK_CPUDIV1 ((uint8_t) (0x01 << 1))

CPU clock prescaler [1] (in _CLK_CKDIVR)

Definition at line 924 of file STM8AF_STM8S.h.

◆ _CLK_CPUDIV2

#define _CLK_CPUDIV2 ((uint8_t) (0x01 << 2))

CPU clock prescaler [2] (in _CLK_CKDIVR)

Definition at line 925 of file STM8AF_STM8S.h.

◆ _CLK_CSSD

#define _CLK_CSSD ((uint8_t) (0x01 << 3))

Clock security system detection [0] (in _CLK_CSSR)

Definition at line 945 of file STM8AF_STM8S.h.

◆ _CLK_CSSDIE

#define _CLK_CSSDIE ((uint8_t) (0x01 << 2))

Clock security system detection interrupt enable [0] (in _CLK_CSSR)

Definition at line 944 of file STM8AF_STM8S.h.

◆ _CLK_CSSEN

#define _CLK_CSSEN ((uint8_t) (0x01 << 0))

Clock security system enable [0] (in _CLK_CSSR)

Definition at line 942 of file STM8AF_STM8S.h.

◆ _CLK_CSSR

#define _CLK_CSSR _SFR(uint8_t, CLK_AddressBase+0x08)

Clock security system register.

Definition at line 874 of file STM8AF_STM8S.h.

◆ _CLK_CSSR_RESET_VALUE

#define _CLK_CSSR_RESET_VALUE ((uint8_t) 0x00)

Clock security system register reset value.

Definition at line 890 of file STM8AF_STM8S.h.

◆ _CLK_ECKR

#define _CLK_ECKR _SFR(uint8_t, CLK_AddressBase+0x01)

External clock register.

Definition at line 867 of file STM8AF_STM8S.h.

◆ _CLK_ECKR_HSERDY

#define _CLK_ECKR_HSERDY ((uint8_t) (0x01 << 1))

High speed external crystal oscillator ready [0] (in _CLK_ECKR)

Definition at line 906 of file STM8AF_STM8S.h.

◆ _CLK_ECKR_RESET_VALUE

#define _CLK_ECKR_RESET_VALUE ((uint8_t) 0x00)

External clock register reset value.

Definition at line 883 of file STM8AF_STM8S.h.

◆ _CLK_FHWU

#define _CLK_FHWU ((uint8_t) (0x01 << 2))

Fast wakeup from Halt/Active-halt modes [0] (in _CLK_ICKR)

Definition at line 898 of file STM8AF_STM8S.h.

◆ _CLK_HSEEN

#define _CLK_HSEEN ((uint8_t) (0x01 << 0))

High speed external crystal oscillator enable [0] (in _CLK_ECKR)

Definition at line 905 of file STM8AF_STM8S.h.

◆ _CLK_HSIDIV

#define _CLK_HSIDIV ((uint8_t) (0x03 << 3))

High speed internal clock prescaler [1:0] (in _CLK_CKDIVR)

Definition at line 926 of file STM8AF_STM8S.h.

◆ _CLK_HSIDIV0

#define _CLK_HSIDIV0 ((uint8_t) (0x01 << 3))

High speed internal clock prescaler [0] (in _CLK_CKDIVR)

Definition at line 927 of file STM8AF_STM8S.h.

◆ _CLK_HSIDIV1

#define _CLK_HSIDIV1 ((uint8_t) (0x01 << 4))

High speed internal clock prescaler [1] (in _CLK_CKDIVR)

Definition at line 928 of file STM8AF_STM8S.h.

◆ _CLK_HSIEN

#define _CLK_HSIEN ((uint8_t) (0x01 << 0))

High speed internal RC oscillator enable [0] (in _CLK_ICKR)

Definition at line 896 of file STM8AF_STM8S.h.

◆ _CLK_HSIRDY

#define _CLK_HSIRDY ((uint8_t) (0x01 << 1))

High speed internal oscillator ready [0] (in _CLK_ICKR)

Definition at line 897 of file STM8AF_STM8S.h.

◆ _CLK_HSITRIM

#define _CLK_HSITRIM ((uint8_t) (0x0F << 0))

HSI trimming value (some devices only support 3 bits, see DS!) [3:0] (in _CLK_HSITRIMR)

Definition at line 967 of file STM8AF_STM8S.h.

◆ _CLK_HSITRIM0

#define _CLK_HSITRIM0 ((uint8_t) (0x01 << 0))

HSI trimming value [0] (in _CLK_HSITRIMR)

Definition at line 968 of file STM8AF_STM8S.h.

◆ _CLK_HSITRIM1

#define _CLK_HSITRIM1 ((uint8_t) (0x01 << 1))

HSI trimming value [1] (in _CLK_HSITRIMR)

Definition at line 969 of file STM8AF_STM8S.h.

◆ _CLK_HSITRIM2

#define _CLK_HSITRIM2 ((uint8_t) (0x01 << 2))

HSI trimming value [2] (in _CLK_HSITRIMR)

Definition at line 970 of file STM8AF_STM8S.h.

◆ _CLK_HSITRIM3

#define _CLK_HSITRIM3 ((uint8_t) (0x01 << 3))

HSI trimming value [3] (in _CLK_HSITRIMR)

Definition at line 971 of file STM8AF_STM8S.h.

◆ _CLK_HSITRIMR

#define _CLK_HSITRIMR _SFR(uint8_t, CLK_AddressBase+0x0C)

HSI clock calibration trimming register.

Definition at line 878 of file STM8AF_STM8S.h.

◆ _CLK_HSITRIMR_RESET_VALUE

#define _CLK_HSITRIMR_RESET_VALUE ((uint8_t) 0x00)

HSI clock calibration trimming register reset value.

Definition at line 892 of file STM8AF_STM8S.h.

◆ _CLK_I2C

#define _CLK_I2C ((uint8_t) (0x01 << 0))

clock enable I2C [0] (in _CLK_PCKENR1)

Definition at line 932 of file STM8AF_STM8S.h.

◆ _CLK_ICKR

#define _CLK_ICKR _SFR(uint8_t, CLK_AddressBase+0x00)

Internal clock register.

Definition at line 866 of file STM8AF_STM8S.h.

◆ _CLK_ICKR_RESET_VALUE

#define _CLK_ICKR_RESET_VALUE ((uint8_t) 0x01)

Internal clock register reset value.

Definition at line 882 of file STM8AF_STM8S.h.

◆ _CLK_LSIEN

#define _CLK_LSIEN ((uint8_t) (0x01 << 3))

Low speed internal RC oscillator enable [0] (in _CLK_ICKR)

Definition at line 899 of file STM8AF_STM8S.h.

◆ _CLK_LSIRDY

#define _CLK_LSIRDY ((uint8_t) (0x01 << 4))

Low speed internal oscillator ready [0] (in _CLK_ICKR)

Definition at line 900 of file STM8AF_STM8S.h.

◆ _CLK_PCKENR1

#define _CLK_PCKENR1 _SFR(uint8_t, CLK_AddressBase+0x07)

Peripheral clock gating register 1.

Definition at line 873 of file STM8AF_STM8S.h.

◆ _CLK_PCKENR1_RESET_VALUE

#define _CLK_PCKENR1_RESET_VALUE ((uint8_t) 0xFF)

Peripheral clock gating register 1 reset value.

Definition at line 888 of file STM8AF_STM8S.h.

◆ _CLK_PCKENR2

#define _CLK_PCKENR2 _SFR(uint8_t, CLK_AddressBase+0x0A)

Peripheral clock gating register 2.

Definition at line 876 of file STM8AF_STM8S.h.

◆ _CLK_PCKENR2_RESET_VALUE

#define _CLK_PCKENR2_RESET_VALUE ((uint8_t) 0xFF)

Peripheral clock gating register 2 reset value.

Definition at line 889 of file STM8AF_STM8S.h.

◆ _CLK_REGAH

#define _CLK_REGAH ((uint8_t) (0x01 << 5))

Regulator power off in Active-halt mode [0] (in _CLK_ICKR)

Definition at line 901 of file STM8AF_STM8S.h.

◆ _CLK_SPI

#define _CLK_SPI ((uint8_t) (0x01 << 1))

clock enable SPI [0] (in _CLK_PCKENR1)

Definition at line 933 of file STM8AF_STM8S.h.

◆ _CLK_SWBSY

#define _CLK_SWBSY ((uint8_t) (0x01 << 0))

Switch busy flag [0] (in _CLK_SWCR)

Definition at line 915 of file STM8AF_STM8S.h.

◆ _CLK_SWCR

#define _CLK_SWCR _SFR(uint8_t, CLK_AddressBase+0x05)

Clock switch control register.

Definition at line 871 of file STM8AF_STM8S.h.

◆ _CLK_SWCR_RESET_VALUE

#define _CLK_SWCR_RESET_VALUE ((uint8_t) 0x00)

Clock switch control reset value.

Definition at line 886 of file STM8AF_STM8S.h.

◆ _CLK_SWEN

#define _CLK_SWEN ((uint8_t) (0x01 << 1))

Switch start/stop enable [0] (in _CLK_SWCR)

Definition at line 916 of file STM8AF_STM8S.h.

◆ _CLK_SWI_HSE

#define _CLK_SWI_HSE ((uint8_t) 0xB4)

write to CLK_SWR for HSE clock (in _CLK_SWR)

Definition at line 912 of file STM8AF_STM8S.h.

◆ _CLK_SWI_HSI

#define _CLK_SWI_HSI ((uint8_t) 0xE1)

write to CLK_SWR for HSI clock (in _CLK_SWR)

Definition at line 910 of file STM8AF_STM8S.h.

◆ _CLK_SWI_LSI

#define _CLK_SWI_LSI ((uint8_t) 0xD2)

write to CLK_SWR for LSI clock (in _CLK_SWR)

Definition at line 911 of file STM8AF_STM8S.h.

◆ _CLK_SWIEN

#define _CLK_SWIEN ((uint8_t) (0x01 << 2))

Clock switch interrupt enable [0] (in _CLK_SWCR)

Definition at line 917 of file STM8AF_STM8S.h.

◆ _CLK_SWIF

#define _CLK_SWIF ((uint8_t) (0x01 << 3))

Clock switch interrupt flag [0] (in _CLK_SWCR)

Definition at line 918 of file STM8AF_STM8S.h.

◆ _CLK_SWIMCCR

#define _CLK_SWIMCCR _SFR(uint8_t, CLK_AddressBase+0x0D)

SWIM clock control register.

Definition at line 879 of file STM8AF_STM8S.h.

◆ _CLK_SWIMCCR_RESET_VALUE

#define _CLK_SWIMCCR_RESET_VALUE ((uint8_t) 0x00)

SWIM clock control register reset value.

Definition at line 893 of file STM8AF_STM8S.h.

◆ _CLK_SWIMCLK

#define _CLK_SWIMCLK ((uint8_t) (0x01 << 0))

SWIM clock divider [0] (in _CLK_SWIMCCR)

Definition at line 975 of file STM8AF_STM8S.h.

◆ _CLK_SWR

#define _CLK_SWR _SFR(uint8_t, CLK_AddressBase+0x04)

Clock master switch register.

Definition at line 870 of file STM8AF_STM8S.h.

◆ _CLK_SWR_RESET_VALUE

#define _CLK_SWR_RESET_VALUE ((uint8_t) 0xE1)

Clock master switch reset value.

Definition at line 885 of file STM8AF_STM8S.h.

◆ _CLK_TIM1

#define _CLK_TIM1 ((uint8_t) (0x01 << 7))

clock enable TIM1 [0] (in _CLK_PCKENR1)

Definition at line 939 of file STM8AF_STM8S.h.

◆ _CLK_TIM2_TIM5

#define _CLK_TIM2_TIM5 ((uint8_t) (0x01 << 5))

clock enable TIM2/TIM5 [0] (in _CLK_PCKENR1)

Definition at line 937 of file STM8AF_STM8S.h.

◆ _CLK_TIM3

#define _CLK_TIM3 ((uint8_t) (0x01 << 6))

clock enable TIM3 [0] (in _CLK_PCKENR1)

Definition at line 938 of file STM8AF_STM8S.h.

◆ _CLK_TIM4_TIM6

#define _CLK_TIM4_TIM6 ((uint8_t) (0x01 << 4))

clock enable TIM4/TIM6 [0] (in _CLK_PCKENR1)

Definition at line 936 of file STM8AF_STM8S.h.

◆ _CLK_UART1

#define _CLK_UART1 ((uint8_t) (0x01 << 2))

clock enable UART1 [0] (in _CLK_PCKENR1)

Definition at line 934 of file STM8AF_STM8S.h.

◆ _CLK_UART2

#define _CLK_UART2 ((uint8_t) (0x01 << 3))

clock enable UART2 [0] (in _CLK_PCKENR1)

Definition at line 935 of file STM8AF_STM8S.h.

◆ _EXTI

#define _EXTI _SFR(EXTI_t, EXTI_AddressBase)

External interrupt struct/bit access.

Definition at line 671 of file STM8AF_STM8S.h.

◆ _EXTI_CR1

#define _EXTI_CR1 _SFR(uint8_t, EXTI_AddressBase+0x00)

External interrupt control register 1 (EXTI_CR1)

Definition at line 672 of file STM8AF_STM8S.h.

◆ _EXTI_CR1_RESET_VALUE

#define _EXTI_CR1_RESET_VALUE ((uint8_t) 0x00)

External interrupt control register 1 reset value.

Definition at line 676 of file STM8AF_STM8S.h.

◆ _EXTI_CR2

#define _EXTI_CR2 _SFR(uint8_t, EXTI_AddressBase+0x01)

External interrupt control register 2 (EXTI_CR2)

Definition at line 673 of file STM8AF_STM8S.h.

◆ _EXTI_CR2_RESET_VALUE

#define _EXTI_CR2_RESET_VALUE ((uint8_t) 0x00)

External interrupt control register 2 reset value.

Definition at line 677 of file STM8AF_STM8S.h.

◆ _EXTI_PAIS

#define _EXTI_PAIS ((uint8_t) (0x03 << 0))

External interrupt sensitivity for Port A [1:0] (in _EXTI_CR1)

Definition at line 680 of file STM8AF_STM8S.h.

◆ _EXTI_PAIS0

#define _EXTI_PAIS0 ((uint8_t) (0x01 << 0))

External interrupt sensitivity for Port A [0] (in _EXTI_CR1)

Definition at line 681 of file STM8AF_STM8S.h.

◆ _EXTI_PAIS1

#define _EXTI_PAIS1 ((uint8_t) (0x01 << 1))

External interrupt sensitivity for Port A [1] (in _EXTI_CR1)

Definition at line 682 of file STM8AF_STM8S.h.

◆ _EXTI_PBIS

#define _EXTI_PBIS ((uint8_t) (0x03 << 2))

External interrupt sensitivity for Port B [1:0] (in _EXTI_CR1)

Definition at line 683 of file STM8AF_STM8S.h.

◆ _EXTI_PBIS0

#define _EXTI_PBIS0 ((uint8_t) (0x01 << 2))

External interrupt sensitivity for Port B [0] (in _EXTI_CR1)

Definition at line 684 of file STM8AF_STM8S.h.

◆ _EXTI_PBIS1

#define _EXTI_PBIS1 ((uint8_t) (0x01 << 3))

External interrupt sensitivity for Port B [1] (in _EXTI_CR1)

Definition at line 685 of file STM8AF_STM8S.h.

◆ _EXTI_PCIS

#define _EXTI_PCIS ((uint8_t) (0x03 << 4))

External interrupt sensitivity for Port C [1:0] (in _EXTI_CR1)

Definition at line 686 of file STM8AF_STM8S.h.

◆ _EXTI_PCIS0

#define _EXTI_PCIS0 ((uint8_t) (0x01 << 4))

External interrupt sensitivity for Port C [0] (in _EXTI_CR1)

Definition at line 687 of file STM8AF_STM8S.h.

◆ _EXTI_PCIS1

#define _EXTI_PCIS1 ((uint8_t) (0x01 << 5))

External interrupt sensitivity for Port C [1] (in _EXTI_CR1)

Definition at line 688 of file STM8AF_STM8S.h.

◆ _EXTI_PDIS

#define _EXTI_PDIS ((uint8_t) (0x03 << 6))

External interrupt sensitivity for Port D [1:0] (in _EXTI_CR1)

Definition at line 689 of file STM8AF_STM8S.h.

◆ _EXTI_PDIS0

#define _EXTI_PDIS0 ((uint8_t) (0x01 << 6))

External interrupt sensitivity for Port D [0] (in _EXTI_CR1)

Definition at line 690 of file STM8AF_STM8S.h.

◆ _EXTI_PDIS1

#define _EXTI_PDIS1 ((uint8_t) (0x01 << 7))

External interrupt sensitivity for Port D [1] (in _EXTI_CR1)

Definition at line 691 of file STM8AF_STM8S.h.

◆ _EXTI_PEIS

#define _EXTI_PEIS ((uint8_t) (0x03 << 0))

Port E external interrupt sensitivity bits [1:0] (in _EXTI_CR2)

Definition at line 694 of file STM8AF_STM8S.h.

◆ _EXTI_PEIS0

#define _EXTI_PEIS0 ((uint8_t) (0x01 << 0))

Port E external interrupt sensitivity bits [0] (in _EXTI_CR2)

Definition at line 695 of file STM8AF_STM8S.h.

◆ _EXTI_PEIS1

#define _EXTI_PEIS1 ((uint8_t) (0x01 << 1))

Port E external interrupt sensitivity bits [1] (in _EXTI_CR2)

Definition at line 696 of file STM8AF_STM8S.h.

◆ _EXTI_TLIS

#define _EXTI_TLIS ((uint8_t) (0x01 << 2))

Top level interrupt sensitivity [0] (in _EXTI_CR2)

Definition at line 697 of file STM8AF_STM8S.h.

◆ _FLASH

#define _FLASH _SFR(FLASH_t, FLASH_AddressBase)

Flash struct/bit access.

Definition at line 586 of file STM8AF_STM8S.h.

◆ _FLASH_AHALT

#define _FLASH_AHALT ((uint8_t) (0x01 << 2))

Power-down in Active-halt mode [0] (in _FLASH_CR1)

Definition at line 609 of file STM8AF_STM8S.h.

◆ _FLASH_CR1

#define _FLASH_CR1 _SFR(uint8_t, FLASH_AddressBase+0x00)

Flash control register 1 (FLASH_CR1)

Definition at line 587 of file STM8AF_STM8S.h.

◆ _FLASH_CR1_RESET_VALUE

#define _FLASH_CR1_RESET_VALUE ((uint8_t) 0x00)

Flash control register 1 reset value.

Definition at line 599 of file STM8AF_STM8S.h.

◆ _FLASH_CR2

#define _FLASH_CR2 _SFR(uint8_t, FLASH_AddressBase+0x01)

Flash control register 2 (FLASH_CR2)

Definition at line 588 of file STM8AF_STM8S.h.

◆ _FLASH_CR2_RESET_VALUE

#define _FLASH_CR2_RESET_VALUE ((uint8_t) 0x00)

Flash control register 2 reset value.

Definition at line 600 of file STM8AF_STM8S.h.

◆ _FLASH_DUKR

#define _FLASH_DUKR _SFR(uint8_t, FLASH_AddressBase+0x0A)

Data EEPROM unprotection key register (FLASH_DUKR)

Definition at line 596 of file STM8AF_STM8S.h.

◆ _FLASH_DUKR_RESET_VALUE

#define _FLASH_DUKR_RESET_VALUE ((uint8_t) 0x00)

Data EEPROM unprotection key reset value.

Definition at line 604 of file STM8AF_STM8S.h.

◆ _FLASH_DUL

#define _FLASH_DUL ((uint8_t) (0x01 << 3))

Data EEPROM area unlocked flag [0] (in _FLASH_IAPSR)

Definition at line 635 of file STM8AF_STM8S.h.

◆ _FLASH_EOP

#define _FLASH_EOP ((uint8_t) (0x01 << 2))

End of programming (write or erase operation) flag [0] (in _FLASH_IAPSR)

Definition at line 634 of file STM8AF_STM8S.h.

◆ _FLASH_ERASE

#define _FLASH_ERASE ((uint8_t) (0x01 << 5))

Block erasing [0] (in _FLASH_CR2 and _FLASH_NCR2)

Definition at line 617 of file STM8AF_STM8S.h.

◆ _FLASH_FIX

#define _FLASH_FIX ((uint8_t) (0x01 << 0))

Fixed Byte programming time [0] (in _FLASH_CR1)

Definition at line 607 of file STM8AF_STM8S.h.

◆ _FLASH_FPR

#define _FLASH_FPR _SFR(uint8_t, FLASH_AddressBase+0x03)

Flash protection register (FLASH_FPR)

Definition at line 590 of file STM8AF_STM8S.h.

◆ _FLASH_FPRG

#define _FLASH_FPRG ((uint8_t) (0x01 << 4))

Fast block programming [0] (in _FLASH_CR2 and _FLASH_NCR2)

Definition at line 616 of file STM8AF_STM8S.h.

◆ _FLASH_HALT

#define _FLASH_HALT ((uint8_t) (0x01 << 3))

Power-down in Halt mode [0] (in _FLASH_CR1)

Definition at line 610 of file STM8AF_STM8S.h.

◆ _FLASH_HVOFF

#define _FLASH_HVOFF ((uint8_t) (0x01 << 5))

End of high voltage flag [0] (in _FLASH_IAPSR)

Definition at line 637 of file STM8AF_STM8S.h.

◆ _FLASH_IAPSR

#define _FLASH_IAPSR _SFR(uint8_t, FLASH_AddressBase+0x05)

Flash status register (FLASH_IAPSR)

Definition at line 592 of file STM8AF_STM8S.h.

◆ _FLASH_IAPSR_RESET_VALUE

#define _FLASH_IAPSR_RESET_VALUE ((uint8_t) 0x40)

Flash status register reset value.

Definition at line 602 of file STM8AF_STM8S.h.

◆ _FLASH_IE

#define _FLASH_IE ((uint8_t) (0x01 << 1))

Flash Interrupt enable [0] (in _FLASH_CR1)

Definition at line 608 of file STM8AF_STM8S.h.

◆ _FLASH_NCR2

#define _FLASH_NCR2 _SFR(uint8_t, FLASH_AddressBase+0x02)

complementary Flash control register 2 (FLASH_NCR2)

Definition at line 589 of file STM8AF_STM8S.h.

◆ _FLASH_NCR2_RESET_VALUE

#define _FLASH_NCR2_RESET_VALUE ((uint8_t) 0xFF)

complementary Flash control register 2 reset value

Definition at line 601 of file STM8AF_STM8S.h.

◆ _FLASH_NFPR

#define _FLASH_NFPR _SFR(uint8_t, FLASH_AddressBase+0x04)

complementary Flash protection register (FLASH_NFPR)

Definition at line 591 of file STM8AF_STM8S.h.

◆ _FLASH_OPT

#define _FLASH_OPT ((uint8_t) (0x01 << 7))

Write option bytes [0] (in _FLASH_CR2 and _FLASH_NCR2)

Definition at line 619 of file STM8AF_STM8S.h.

◆ _FLASH_PRG

#define _FLASH_PRG ((uint8_t) (0x01 << 0))

Standard block programming [0] (in _FLASH_CR2 and _FLASH_NCR2)

Definition at line 614 of file STM8AF_STM8S.h.

◆ _FLASH_PUKR

#define _FLASH_PUKR _SFR(uint8_t, FLASH_AddressBase+0x08)

Flash program memory unprotecting key register (FLASH_PUKR)

Definition at line 594 of file STM8AF_STM8S.h.

◆ _FLASH_PUKR_RESET_VALUE

#define _FLASH_PUKR_RESET_VALUE ((uint8_t) 0x00)

Flash program memory unprotecting key reset value.

Definition at line 603 of file STM8AF_STM8S.h.

◆ _FLASH_PUL

#define _FLASH_PUL ((uint8_t) (0x01 << 1))

Flash Program memory unlocked flag [0] (in _FLASH_IAPSR)

Definition at line 633 of file STM8AF_STM8S.h.

◆ _FLASH_WPB

#define _FLASH_WPB ((uint8_t) (0x3F << 0))

User boot code area protection bits [5:0] (in _FLASH_FPR and _FLASH_NFPR)

Definition at line 622 of file STM8AF_STM8S.h.

◆ _FLASH_WPB0

#define _FLASH_WPB0 ((uint8_t) (0x01 << 0))

User boot code area protection bit [0] (in _FLASH_FPR and _FLASH_NFPR)

Definition at line 623 of file STM8AF_STM8S.h.

◆ _FLASH_WPB1

#define _FLASH_WPB1 ((uint8_t) (0x01 << 1))

User boot code area protection bit [1] (in _FLASH_FPR and _FLASH_NFPR)

Definition at line 624 of file STM8AF_STM8S.h.

◆ _FLASH_WPB2

#define _FLASH_WPB2 ((uint8_t) (0x01 << 2))

User boot code area protection bit [2] (in _FLASH_FPR and _FLASH_NFPR)

Definition at line 625 of file STM8AF_STM8S.h.

◆ _FLASH_WPB3

#define _FLASH_WPB3 ((uint8_t) (0x01 << 3))

User boot code area protection bit [3] (in _FLASH_FPR and _FLASH_NFPR)

Definition at line 626 of file STM8AF_STM8S.h.

◆ _FLASH_WPB4

#define _FLASH_WPB4 ((uint8_t) (0x01 << 4))

User boot code area protection bit [4] (in _FLASH_FPR and _FLASH_NFPR)

Definition at line 627 of file STM8AF_STM8S.h.

◆ _FLASH_WPB5

#define _FLASH_WPB5 ((uint8_t) (0x01 << 5))

User boot code area protection bit [5] (in _FLASH_FPR and _FLASH_NFPR)

Definition at line 628 of file STM8AF_STM8S.h.

◆ _FLASH_WPRG

#define _FLASH_WPRG ((uint8_t) (0x01 << 6))

Word programming [0] (in _FLASH_CR2 and _FLASH_NCR2)

Definition at line 618 of file STM8AF_STM8S.h.

◆ _FLASH_WR_PG_DIS

#define _FLASH_WR_PG_DIS ((uint8_t) (0x01 << 0))

Write attempted to protected page flag [0] (in _FLASH_IAPSR)

Definition at line 632 of file STM8AF_STM8S.h.

◆ _GPIO_CR1_RESET_VALUE

#define _GPIO_CR1_RESET_VALUE ((uint8_t) 0x00)

port control register 1 reset value

Definition at line 481 of file STM8AF_STM8S.h.

◆ _GPIO_CR2_RESET_VALUE

#define _GPIO_CR2_RESET_VALUE ((uint8_t) 0x00)

port control register 2 reset value

Definition at line 482 of file STM8AF_STM8S.h.

◆ _GPIO_DDR_RESET_VALUE

#define _GPIO_DDR_RESET_VALUE ((uint8_t) 0x00)

port direction register reset value

Definition at line 480 of file STM8AF_STM8S.h.

◆ _GPIO_ODR_RESET_VALUE

#define _GPIO_ODR_RESET_VALUE ((uint8_t) 0x00)

port output register reset value

Definition at line 479 of file STM8AF_STM8S.h.

◆ _GPIO_PIN0

#define _GPIO_PIN0 ((uint8_t) (0x01 << 0))

port bit mask for pin 0 (in _GPIOI_ODR, _GPIOI_IDR, _GPIOI_DDR, _GPIOI_CR1, _GPIOI_CR2)

Definition at line 485 of file STM8AF_STM8S.h.

◆ _GPIO_PIN1

#define _GPIO_PIN1 ((uint8_t) (0x01 << 1))

port bit mask for pin 1 (in _GPIOI_ODR, _GPIOI_IDR, _GPIOI_DDR, _GPIOI_CR1, _GPIOI_CR2)

Definition at line 486 of file STM8AF_STM8S.h.

◆ _GPIO_PIN2

#define _GPIO_PIN2 ((uint8_t) (0x01 << 2))

port bit mask for pin 2 (in _GPIOI_ODR, _GPIOI_IDR, _GPIOI_DDR, _GPIOI_CR1, _GPIOI_CR2)

Definition at line 487 of file STM8AF_STM8S.h.

◆ _GPIO_PIN3

#define _GPIO_PIN3 ((uint8_t) (0x01 << 3))

port bit mask for pin 3 (in _GPIOI_ODR, _GPIOI_IDR, _GPIOI_DDR, _GPIOI_CR1, _GPIOI_CR2)

Definition at line 488 of file STM8AF_STM8S.h.

◆ _GPIO_PIN4

#define _GPIO_PIN4 ((uint8_t) (0x01 << 4))

port bit mask for pin 4 (in _GPIOI_ODR, _GPIOI_IDR, _GPIOI_DDR, _GPIOI_CR1, _GPIOI_CR2)

Definition at line 489 of file STM8AF_STM8S.h.

◆ _GPIO_PIN5

#define _GPIO_PIN5 ((uint8_t) (0x01 << 5))

port bit mask for pin 5 (in _GPIOI_ODR, _GPIOI_IDR, _GPIOI_DDR, _GPIOI_CR1, _GPIOI_CR2)

Definition at line 490 of file STM8AF_STM8S.h.

◆ _GPIO_PIN6

#define _GPIO_PIN6 ((uint8_t) (0x01 << 6))

port bit mask for pin 6 (in _GPIOI_ODR, _GPIOI_IDR, _GPIOI_DDR, _GPIOI_CR1, _GPIOI_CR2)

Definition at line 491 of file STM8AF_STM8S.h.

◆ _GPIO_PIN7

#define _GPIO_PIN7 ((uint8_t) (0x01 << 7))

port bit mask for pin 7 (in _GPIOI_ODR, _GPIOI_IDR, _GPIOI_DDR, _GPIOI_CR1, _GPIOI_CR2)

Definition at line 492 of file STM8AF_STM8S.h.

◆ _GPIOA

#define _GPIOA _SFR(PORT_t, PORTA_AddressBase)

port A struct/bit access

Definition at line 390 of file STM8AF_STM8S.h.

◆ _GPIOA_CR1

#define _GPIOA_CR1 _SFR(uint8_t, PORTA_AddressBase+0x03)

port A control register 1

Definition at line 394 of file STM8AF_STM8S.h.

◆ _GPIOA_CR2

#define _GPIOA_CR2 _SFR(uint8_t, PORTA_AddressBase+0x04)

port A control register 2

Definition at line 395 of file STM8AF_STM8S.h.

◆ _GPIOA_DDR

#define _GPIOA_DDR _SFR(uint8_t, PORTA_AddressBase+0x02)

port A direction register

Definition at line 393 of file STM8AF_STM8S.h.

◆ _GPIOA_IDR

#define _GPIOA_IDR _SFR(uint8_t, PORTA_AddressBase+0x01)

port A input register

Definition at line 392 of file STM8AF_STM8S.h.

◆ _GPIOA_ODR

#define _GPIOA_ODR _SFR(uint8_t, PORTA_AddressBase+0x00)

port A output register

Definition at line 391 of file STM8AF_STM8S.h.

◆ _GPIOB

#define _GPIOB _SFR(PORT_t, PORTB_AddressBase)

port B struct/bit access

Definition at line 400 of file STM8AF_STM8S.h.

◆ _GPIOB_CR1

#define _GPIOB_CR1 _SFR(uint8_t, PORTB_AddressBase+0x03)

port B control register 1

Definition at line 404 of file STM8AF_STM8S.h.

◆ _GPIOB_CR2

#define _GPIOB_CR2 _SFR(uint8_t, PORTB_AddressBase+0x04)

port B control register 2

Definition at line 405 of file STM8AF_STM8S.h.

◆ _GPIOB_DDR

#define _GPIOB_DDR _SFR(uint8_t, PORTB_AddressBase+0x02)

port B direction register

Definition at line 403 of file STM8AF_STM8S.h.

◆ _GPIOB_IDR

#define _GPIOB_IDR _SFR(uint8_t, PORTB_AddressBase+0x01)

port B input register

Definition at line 402 of file STM8AF_STM8S.h.

◆ _GPIOB_ODR

#define _GPIOB_ODR _SFR(uint8_t, PORTB_AddressBase+0x00)

port B output register

Definition at line 401 of file STM8AF_STM8S.h.

◆ _GPIOC

#define _GPIOC _SFR(PORT_t, PORTC_AddressBase)

port C struct/bit access

Definition at line 410 of file STM8AF_STM8S.h.

◆ _GPIOC_CR1

#define _GPIOC_CR1 _SFR(uint8_t, PORTC_AddressBase+0x03)

port C control register 1

Definition at line 414 of file STM8AF_STM8S.h.

◆ _GPIOC_CR2

#define _GPIOC_CR2 _SFR(uint8_t, PORTC_AddressBase+0x04)

port C control register 2

Definition at line 415 of file STM8AF_STM8S.h.

◆ _GPIOC_DDR

#define _GPIOC_DDR _SFR(uint8_t, PORTC_AddressBase+0x02)

port C direction register

Definition at line 413 of file STM8AF_STM8S.h.

◆ _GPIOC_IDR

#define _GPIOC_IDR _SFR(uint8_t, PORTC_AddressBase+0x01)

port C input register

Definition at line 412 of file STM8AF_STM8S.h.

◆ _GPIOC_ODR

#define _GPIOC_ODR _SFR(uint8_t, PORTC_AddressBase+0x00)

port C output register

Definition at line 411 of file STM8AF_STM8S.h.

◆ _GPIOD

#define _GPIOD _SFR(PORT_t, PORTD_AddressBase)

port D struct/bit access

Definition at line 420 of file STM8AF_STM8S.h.

◆ _GPIOD_CR1

#define _GPIOD_CR1 _SFR(uint8_t, PORTD_AddressBase+0x03)

port D control register 1

Definition at line 424 of file STM8AF_STM8S.h.

◆ _GPIOD_CR2

#define _GPIOD_CR2 _SFR(uint8_t, PORTD_AddressBase+0x04)

port D control register 2

Definition at line 425 of file STM8AF_STM8S.h.

◆ _GPIOD_DDR

#define _GPIOD_DDR _SFR(uint8_t, PORTD_AddressBase+0x02)

port D direction register

Definition at line 423 of file STM8AF_STM8S.h.

◆ _GPIOD_IDR

#define _GPIOD_IDR _SFR(uint8_t, PORTD_AddressBase+0x01)

port D input register

Definition at line 422 of file STM8AF_STM8S.h.

◆ _GPIOD_ODR

#define _GPIOD_ODR _SFR(uint8_t, PORTD_AddressBase+0x00)

port D output register

Definition at line 421 of file STM8AF_STM8S.h.

◆ _GPIOE

#define _GPIOE _SFR(PORT_t, PORTE_AddressBase)

port E struct/bit access

Definition at line 430 of file STM8AF_STM8S.h.

◆ _GPIOE_CR1

#define _GPIOE_CR1 _SFR(uint8_t, PORTE_AddressBase+0x03)

port E control register 1

Definition at line 434 of file STM8AF_STM8S.h.

◆ _GPIOE_CR2

#define _GPIOE_CR2 _SFR(uint8_t, PORTE_AddressBase+0x04)

port E control register 2

Definition at line 435 of file STM8AF_STM8S.h.

◆ _GPIOE_DDR

#define _GPIOE_DDR _SFR(uint8_t, PORTE_AddressBase+0x02)

port E direction register

Definition at line 433 of file STM8AF_STM8S.h.

◆ _GPIOE_IDR

#define _GPIOE_IDR _SFR(uint8_t, PORTE_AddressBase+0x01)

port E input register

Definition at line 432 of file STM8AF_STM8S.h.

◆ _GPIOE_ODR

#define _GPIOE_ODR _SFR(uint8_t, PORTE_AddressBase+0x00)

port E output register

Definition at line 431 of file STM8AF_STM8S.h.

◆ _GPIOF

#define _GPIOF _SFR(PORT_t, PORTF_AddressBase)

port F struct/bit access

Definition at line 440 of file STM8AF_STM8S.h.

◆ _GPIOF_CR1

#define _GPIOF_CR1 _SFR(uint8_t, PORTF_AddressBase+0x03)

port F control register 1

Definition at line 444 of file STM8AF_STM8S.h.

◆ _GPIOF_CR2

#define _GPIOF_CR2 _SFR(uint8_t, PORTF_AddressBase+0x04)

port F control register 2

Definition at line 445 of file STM8AF_STM8S.h.

◆ _GPIOF_DDR

#define _GPIOF_DDR _SFR(uint8_t, PORTF_AddressBase+0x02)

port F direction register

Definition at line 443 of file STM8AF_STM8S.h.

◆ _GPIOF_IDR

#define _GPIOF_IDR _SFR(uint8_t, PORTF_AddressBase+0x01)

port F input register

Definition at line 442 of file STM8AF_STM8S.h.

◆ _GPIOF_ODR

#define _GPIOF_ODR _SFR(uint8_t, PORTF_AddressBase+0x00)

port F output register

Definition at line 441 of file STM8AF_STM8S.h.

◆ _GPIOG

#define _GPIOG _SFR(PORT_t, PORTG_AddressBase)

port G struct/bit access

Definition at line 450 of file STM8AF_STM8S.h.

◆ _GPIOG_CR1

#define _GPIOG_CR1 _SFR(uint8_t, PORTG_AddressBase+0x03)

port G control register 1

Definition at line 454 of file STM8AF_STM8S.h.

◆ _GPIOG_CR2

#define _GPIOG_CR2 _SFR(uint8_t, PORTG_AddressBase+0x04)

port G control register 2

Definition at line 455 of file STM8AF_STM8S.h.

◆ _GPIOG_DDR

#define _GPIOG_DDR _SFR(uint8_t, PORTG_AddressBase+0x02)

port G direction register

Definition at line 453 of file STM8AF_STM8S.h.

◆ _GPIOG_IDR

#define _GPIOG_IDR _SFR(uint8_t, PORTG_AddressBase+0x01)

port G input register

Definition at line 452 of file STM8AF_STM8S.h.

◆ _GPIOG_ODR

#define _GPIOG_ODR _SFR(uint8_t, PORTG_AddressBase+0x00)

port G output register

Definition at line 451 of file STM8AF_STM8S.h.

◆ _GPIOH

#define _GPIOH _SFR(PORT_t, PORTH_AddressBase)

port H struct/bit access

Definition at line 460 of file STM8AF_STM8S.h.

◆ _GPIOH_CR1

#define _GPIOH_CR1 _SFR(uint8_t, PORTH_AddressBase+0x03)

port H control register 1

Definition at line 464 of file STM8AF_STM8S.h.

◆ _GPIOH_CR2

#define _GPIOH_CR2 _SFR(uint8_t, PORTH_AddressBase+0x04)

port H control register 2

Definition at line 465 of file STM8AF_STM8S.h.

◆ _GPIOH_DDR

#define _GPIOH_DDR _SFR(uint8_t, PORTH_AddressBase+0x02)

port H direction register

Definition at line 463 of file STM8AF_STM8S.h.

◆ _GPIOH_IDR

#define _GPIOH_IDR _SFR(uint8_t, PORTH_AddressBase+0x01)

port H input register

Definition at line 462 of file STM8AF_STM8S.h.

◆ _GPIOH_ODR

#define _GPIOH_ODR _SFR(uint8_t, PORTH_AddressBase+0x00)

port H output register

Definition at line 461 of file STM8AF_STM8S.h.

◆ _GPIOI

#define _GPIOI _SFR(PORT_t, PORTI_AddressBase)

port I struct/bit access

Definition at line 470 of file STM8AF_STM8S.h.

◆ _GPIOI_CR1

#define _GPIOI_CR1 _SFR(uint8_t, PORTI_AddressBase+0x03)

port I control register 1

Definition at line 474 of file STM8AF_STM8S.h.

◆ _GPIOI_CR2

#define _GPIOI_CR2 _SFR(uint8_t, PORTI_AddressBase+0x04)

port I control register 2

Definition at line 475 of file STM8AF_STM8S.h.

◆ _GPIOI_DDR

#define _GPIOI_DDR _SFR(uint8_t, PORTI_AddressBase+0x02)

port I direction register

Definition at line 473 of file STM8AF_STM8S.h.

◆ _GPIOI_IDR

#define _GPIOI_IDR _SFR(uint8_t, PORTI_AddressBase+0x01)

port I input register

Definition at line 472 of file STM8AF_STM8S.h.

◆ _GPIOI_ODR

#define _GPIOI_ODR _SFR(uint8_t, PORTI_AddressBase+0x00)

port I output register

Definition at line 471 of file STM8AF_STM8S.h.

◆ _I2C

#define _I2C _SFR(I2C_t, I2C_AddressBase)

register for SPI control

I2C struct/bit access

Definition at line 1485 of file STM8AF_STM8S.h.

◆ _I2C_ACK

#define _I2C_ACK ((uint8_t) (0x01 << 2))

I2C Acknowledge enable [0] (in _I2C_CR2)

Definition at line 1526 of file STM8AF_STM8S.h.

◆ _I2C_ADD0

#define _I2C_ADD0 ((uint8_t) (0x01 << 0))

I2C Interface address [0] (in 10-bit address mode) (in _I2C_OARL)

Definition at line 1542 of file STM8AF_STM8S.h.

◆ _I2C_ADD1

#define _I2C_ADD1 ((uint8_t) (0x01 << 1))

I2C Interface address [1] (in _I2C_OARL)

Definition at line 1543 of file STM8AF_STM8S.h.

◆ _I2C_ADD10

#define _I2C_ADD10 ((uint8_t) (0x01 << 3))

I2C 10-bit header sent (Master mode) [0] (in _I2C_SR1)

Definition at line 1564 of file STM8AF_STM8S.h.

◆ _I2C_ADD2

#define _I2C_ADD2 ((uint8_t) (0x01 << 2))

I2C Interface address [2] (in _I2C_OARL)

Definition at line 1544 of file STM8AF_STM8S.h.

◆ _I2C_ADD3

#define _I2C_ADD3 ((uint8_t) (0x01 << 3))

I2C Interface address [3] (in _I2C_OARL)

Definition at line 1545 of file STM8AF_STM8S.h.

◆ _I2C_ADD4

#define _I2C_ADD4 ((uint8_t) (0x01 << 4))

I2C Interface address [4] (in _I2C_OARL)

Definition at line 1546 of file STM8AF_STM8S.h.

◆ _I2C_ADD5

#define _I2C_ADD5 ((uint8_t) (0x01 << 5))

I2C Interface address [5] (in _I2C_OARL)

Definition at line 1547 of file STM8AF_STM8S.h.

◆ _I2C_ADD6

#define _I2C_ADD6 ((uint8_t) (0x01 << 6))

I2C Interface address [6] (in _I2C_OARL)

Definition at line 1548 of file STM8AF_STM8S.h.

◆ _I2C_ADD7

#define _I2C_ADD7 ((uint8_t) (0x01 << 7))

I2C Interface address [7] (in _I2C_OARL)

Definition at line 1549 of file STM8AF_STM8S.h.

◆ _I2C_ADD8

#define _I2C_ADD8 ((uint8_t) (0x01 << 1))

I2C Interface address [8] (in _I2C_OARH)

Definition at line 1554 of file STM8AF_STM8S.h.

◆ _I2C_ADD9

#define _I2C_ADD9 ((uint8_t) (0x01 << 2))

I2C Interface address [9] (in _I2C_OARH)

Definition at line 1555 of file STM8AF_STM8S.h.

◆ _I2C_ADD_8_9

#define _I2C_ADD_8_9 ((uint8_t) (0x03 << 1))

I2C Interface address [9:8] (in 10-bit address mode) (in _I2C_OARH)

Definition at line 1553 of file STM8AF_STM8S.h.

◆ _I2C_ADDCONF

#define _I2C_ADDCONF ((uint8_t) (0x01 << 6))

I2C Address mode configuration [0] (in _I2C_OARH)

Definition at line 1557 of file STM8AF_STM8S.h.

◆ _I2C_ADDMODE

#define _I2C_ADDMODE ((uint8_t) (0x01 << 7))

I2C 7-/10-bit addressing mode (Slave mode) [0] (in _I2C_OARH)

Definition at line 1558 of file STM8AF_STM8S.h.

◆ _I2C_ADDR

#define _I2C_ADDR ((uint8_t) (0x01 << 1))

I2C Address sent (Master mode) / matched (Slave mode) [0] (in _I2C_SR1)

Definition at line 1562 of file STM8AF_STM8S.h.

◆ _I2C_AF

#define _I2C_AF ((uint8_t) (0x01 << 2))

I2C Acknowledge failure [0] (in _I2C_SR2)

Definition at line 1573 of file STM8AF_STM8S.h.

◆ _I2C_ARLO

#define _I2C_ARLO ((uint8_t) (0x01 << 1))

I2C Arbitration lost (Master mode) [0] (in _I2C_SR2)

Definition at line 1572 of file STM8AF_STM8S.h.

◆ _I2C_BERR

#define _I2C_BERR ((uint8_t) (0x01 << 0))

I2C Bus error [0] (in _I2C_SR2)

Definition at line 1571 of file STM8AF_STM8S.h.

◆ _I2C_BTF

#define _I2C_BTF ((uint8_t) (0x01 << 2))

I2C Byte transfer finished [0] (in _I2C_SR1)

Definition at line 1563 of file STM8AF_STM8S.h.

◆ _I2C_BUSY

#define _I2C_BUSY ((uint8_t) (0x01 << 1))

I2C Bus busy [0] (in _I2C_SR3)

Definition at line 1581 of file STM8AF_STM8S.h.

◆ _I2C_CCR

#define _I2C_CCR ((uint8_t) (0x0F << 0))

I2C Clock control register (Master mode) [3:0] (in _I2C_CCRH)

Definition at line 1594 of file STM8AF_STM8S.h.

◆ _I2C_CCR0

#define _I2C_CCR0 ((uint8_t) (0x01 << 0))

I2C Clock control register (Master mode) [0] (in _I2C_CCRH)

Definition at line 1595 of file STM8AF_STM8S.h.

◆ _I2C_CCR1

#define _I2C_CCR1 ((uint8_t) (0x01 << 1))

I2C Clock control register (Master mode) [1] (in _I2C_CCRH)

Definition at line 1596 of file STM8AF_STM8S.h.

◆ _I2C_CCR2

#define _I2C_CCR2 ((uint8_t) (0x01 << 2))

I2C Clock control register (Master mode) [2] (in _I2C_CCRH)

Definition at line 1597 of file STM8AF_STM8S.h.

◆ _I2C_CCR3

#define _I2C_CCR3 ((uint8_t) (0x01 << 3))

I2C Clock control register (Master mode) [3] (in _I2C_CCRH)

Definition at line 1598 of file STM8AF_STM8S.h.

◆ _I2C_CCRH

#define _I2C_CCRH _SFR(uint8_t, I2C_AddressBase+0x0C)

I2C Clock control register high byte.

Definition at line 1498 of file STM8AF_STM8S.h.

◆ _I2C_CCRH_RESET_VALUE

#define _I2C_CCRH_RESET_VALUE ((uint8_t) 0x00)

I2C Clock control register high byte reset value.

Definition at line 1514 of file STM8AF_STM8S.h.

◆ _I2C_CCRL

#define _I2C_CCRL _SFR(uint8_t, I2C_AddressBase+0x0B)

I2C Clock control register low byte.

Definition at line 1497 of file STM8AF_STM8S.h.

◆ _I2C_CCRL_RESET_VALUE

#define _I2C_CCRL_RESET_VALUE ((uint8_t) 0x00)

I2C Clock control register low byte reset value.

Definition at line 1513 of file STM8AF_STM8S.h.

◆ _I2C_CR1

#define _I2C_CR1 _SFR(uint8_t, I2C_AddressBase+0x00)

I2C Control register 1.

Definition at line 1486 of file STM8AF_STM8S.h.

◆ _I2C_CR1_RESET_VALUE

#define _I2C_CR1_RESET_VALUE ((uint8_t) 0x00)

I2C Control register 1 reset value.

Definition at line 1503 of file STM8AF_STM8S.h.

◆ _I2C_CR2

#define _I2C_CR2 _SFR(uint8_t, I2C_AddressBase+0x01)

I2C Control register 2.

Definition at line 1487 of file STM8AF_STM8S.h.

◆ _I2C_CR2_RESET_VALUE

#define _I2C_CR2_RESET_VALUE ((uint8_t) 0x00)

I2C Control register 2 reset value.

Definition at line 1504 of file STM8AF_STM8S.h.

◆ _I2C_DR

#define _I2C_DR _SFR(uint8_t, I2C_AddressBase+0x06)

I2C data register.

Definition at line 1492 of file STM8AF_STM8S.h.

◆ _I2C_DR_RESET_VALUE

#define _I2C_DR_RESET_VALUE ((uint8_t) 0x00)

I2C data register reset value.

Definition at line 1508 of file STM8AF_STM8S.h.

◆ _I2C_DUTY

#define _I2C_DUTY ((uint8_t) (0x01 << 6))

I2C Fast mode duty cycle [0] (in _I2C_CCRH)

Definition at line 1600 of file STM8AF_STM8S.h.

◆ _I2C_ENGC

#define _I2C_ENGC ((uint8_t) (0x01 << 6))

I2C General call enable [0] (in _I2C_CR1)

Definition at line 1520 of file STM8AF_STM8S.h.

◆ _I2C_FREQ

#define _I2C_FREQ ((uint8_t) (0x3F << 0))

I2C Peripheral clock frequency [5:0] (in _I2C_FREQR)

Definition at line 1532 of file STM8AF_STM8S.h.

◆ _I2C_FREQ0

#define _I2C_FREQ0 ((uint8_t) (0x01 << 0))

I2C Peripheral clock frequency [0] (in _I2C_FREQR)

Definition at line 1533 of file STM8AF_STM8S.h.

◆ _I2C_FREQ1

#define _I2C_FREQ1 ((uint8_t) (0x01 << 1))

I2C Peripheral clock frequency [1] (in _I2C_FREQR)

Definition at line 1534 of file STM8AF_STM8S.h.

◆ _I2C_FREQ2

#define _I2C_FREQ2 ((uint8_t) (0x01 << 2))

I2C Peripheral clock frequency [2] (in _I2C_FREQR)

Definition at line 1535 of file STM8AF_STM8S.h.

◆ _I2C_FREQ3

#define _I2C_FREQ3 ((uint8_t) (0x01 << 3))

I2C Peripheral clock frequency [3] (in _I2C_FREQR)

Definition at line 1536 of file STM8AF_STM8S.h.

◆ _I2C_FREQ4

#define _I2C_FREQ4 ((uint8_t) (0x01 << 4))

I2C Peripheral clock frequency [4] (in _I2C_FREQR)

Definition at line 1537 of file STM8AF_STM8S.h.

◆ _I2C_FREQ5

#define _I2C_FREQ5 ((uint8_t) (0x01 << 5))

I2C Peripheral clock frequency [5] (in _I2C_FREQR)

Definition at line 1538 of file STM8AF_STM8S.h.

◆ _I2C_FREQR

#define _I2C_FREQR _SFR(uint8_t, I2C_AddressBase+0x02)

I2C Frequency register.

Definition at line 1488 of file STM8AF_STM8S.h.

◆ _I2C_FREQR_RESET_VALUE

#define _I2C_FREQR_RESET_VALUE ((uint8_t) 0x00)

I2C Frequency register reset value.

Definition at line 1505 of file STM8AF_STM8S.h.

◆ _I2C_FS

#define _I2C_FS ((uint8_t) (0x01 << 7))

I2C Master mode selection [0] (in _I2C_CCRH)

Definition at line 1601 of file STM8AF_STM8S.h.

◆ _I2C_GENCALL

#define _I2C_GENCALL ((uint8_t) (0x01 << 4))

I2C General call header (Slavemode) [0] (in _I2C_SR3)

Definition at line 1584 of file STM8AF_STM8S.h.

◆ _I2C_ITBUFEN

#define _I2C_ITBUFEN ((uint8_t) (0x01 << 2))

I2C Buffer interrupt enable [0] (in _I2C_ITR)

Definition at line 1590 of file STM8AF_STM8S.h.

◆ _I2C_ITERREN

#define _I2C_ITERREN ((uint8_t) (0x01 << 0))

I2C Error interrupt enable [0] (in _I2C_ITR)

Definition at line 1588 of file STM8AF_STM8S.h.

◆ _I2C_ITEVTEN

#define _I2C_ITEVTEN ((uint8_t) (0x01 << 1))

I2C Event interrupt enable [0] (in _I2C_ITR)

Definition at line 1589 of file STM8AF_STM8S.h.

◆ _I2C_ITR

#define _I2C_ITR _SFR(uint8_t, I2C_AddressBase+0x0A)

I2C Interrupt register.

Definition at line 1496 of file STM8AF_STM8S.h.

◆ _I2C_ITR_RESET_VALUE

#define _I2C_ITR_RESET_VALUE ((uint8_t) 0x00)

I2C Interrupt register reset value.

Definition at line 1512 of file STM8AF_STM8S.h.

◆ _I2C_MSL

#define _I2C_MSL ((uint8_t) (0x01 << 0))

I2C Master/Slave [0] (in _I2C_SR3)

Definition at line 1580 of file STM8AF_STM8S.h.

◆ _I2C_NOSTRETCH

#define _I2C_NOSTRETCH ((uint8_t) (0x01 << 7))

I2C Clock stretching disable (Slave mode) [0] (in _I2C_CR1)

Definition at line 1521 of file STM8AF_STM8S.h.

◆ _I2C_OARH

#define _I2C_OARH _SFR(uint8_t, I2C_AddressBase+0x04)

I2C own address register high byte.

Definition at line 1490 of file STM8AF_STM8S.h.

◆ _I2C_OARH_RESET_VALUE

#define _I2C_OARH_RESET_VALUE ((uint8_t) 0x00)

I2C own address register high byte reset value.

Definition at line 1507 of file STM8AF_STM8S.h.

◆ _I2C_OARL

#define _I2C_OARL _SFR(uint8_t, I2C_AddressBase+0x03)

I2C own address register low byte.

Definition at line 1489 of file STM8AF_STM8S.h.

◆ _I2C_OARL_RESET_VALUE

#define _I2C_OARL_RESET_VALUE ((uint8_t) 0x00)

I2C own address register low byte reset value.

Definition at line 1506 of file STM8AF_STM8S.h.

◆ _I2C_OVR

#define _I2C_OVR ((uint8_t) (0x01 << 3))

I2C Overrun/underrun [0] (in _I2C_SR2)

Definition at line 1574 of file STM8AF_STM8S.h.

◆ _I2C_PE

#define _I2C_PE ((uint8_t) (0x01 << 0))

I2C Peripheral enable [0] (in _I2C_CR1)

Definition at line 1518 of file STM8AF_STM8S.h.

◆ _I2C_POS

#define _I2C_POS ((uint8_t) (0x01 << 3))

I2C Acknowledge position (for data reception) [0] (in _I2C_CR2)

Definition at line 1527 of file STM8AF_STM8S.h.

◆ _I2C_RXNE

#define _I2C_RXNE ((uint8_t) (0x01 << 6))

I2C Data register not empty (receivers) [0] (in _I2C_SR1)

Definition at line 1567 of file STM8AF_STM8S.h.

◆ _I2C_SB

#define _I2C_SB ((uint8_t) (0x01 << 0))

I2C Start bit (Master mode) [0] (in _I2C_SR1)

Definition at line 1561 of file STM8AF_STM8S.h.

◆ _I2C_SR1

#define _I2C_SR1 _SFR(uint8_t, I2C_AddressBase+0x07)

I2C Status register 1.

Definition at line 1493 of file STM8AF_STM8S.h.

◆ _I2C_SR1_RESET_VALUE

#define _I2C_SR1_RESET_VALUE ((uint8_t) 0x00)

I2C Status register 1 reset value.

Definition at line 1509 of file STM8AF_STM8S.h.

◆ _I2C_SR2

#define _I2C_SR2 _SFR(uint8_t, I2C_AddressBase+0x08)

I2C Status register 2.

Definition at line 1494 of file STM8AF_STM8S.h.

◆ _I2C_SR2_RESET_VALUE

#define _I2C_SR2_RESET_VALUE ((uint8_t) 0x00)

I2C Status register 2 reset value.

Definition at line 1510 of file STM8AF_STM8S.h.

◆ _I2C_SR3

#define _I2C_SR3 _SFR(uint8_t, I2C_AddressBase+0x09)

I2C Status register 3.

Definition at line 1495 of file STM8AF_STM8S.h.

◆ _I2C_SR3_RESET_VALUE

#define _I2C_SR3_RESET_VALUE ((uint8_t) 0x00)

I2C Status register 3 reset value.

Definition at line 1511 of file STM8AF_STM8S.h.

◆ _I2C_START

#define _I2C_START ((uint8_t) (0x01 << 0))

I2C Start generation [0] (in _I2C_CR2)

Definition at line 1524 of file STM8AF_STM8S.h.

◆ _I2C_STOP

#define _I2C_STOP ((uint8_t) (0x01 << 1))

I2C Stop generation [0] (in _I2C_CR2)

Definition at line 1525 of file STM8AF_STM8S.h.

◆ _I2C_STOPF

#define _I2C_STOPF ((uint8_t) (0x01 << 4))

I2C Stop detection (Slave mode) [0] (in _I2C_SR1)

Definition at line 1565 of file STM8AF_STM8S.h.

◆ _I2C_SWRST

#define _I2C_SWRST ((uint8_t) (0x01 << 7))

I2C Software reset [0] (in _I2C_CR2)

Definition at line 1529 of file STM8AF_STM8S.h.

◆ _I2C_TRA

#define _I2C_TRA ((uint8_t) (0x01 << 2))

I2C Transmitter/Receiver [0] (in _I2C_SR3)

Definition at line 1582 of file STM8AF_STM8S.h.

◆ _I2C_TRISE

#define _I2C_TRISE ((uint8_t) (0x3F << 0))

I2C Maximum rise time (Master mode) [5:0] (in _I2C_TRISER)

Definition at line 1604 of file STM8AF_STM8S.h.

◆ _I2C_TRISE0

#define _I2C_TRISE0 ((uint8_t) (0x01 << 0))

I2C Maximum rise time (Master mode) [0] (in _I2C_TRISER)

Definition at line 1605 of file STM8AF_STM8S.h.

◆ _I2C_TRISE1

#define _I2C_TRISE1 ((uint8_t) (0x01 << 1))

I2C Maximum rise time (Master mode) [1] (in _I2C_TRISER)

Definition at line 1606 of file STM8AF_STM8S.h.

◆ _I2C_TRISE2

#define _I2C_TRISE2 ((uint8_t) (0x01 << 2))

I2C Maximum rise time (Master mode) [2] (in _I2C_TRISER)

Definition at line 1607 of file STM8AF_STM8S.h.

◆ _I2C_TRISE3

#define _I2C_TRISE3 ((uint8_t) (0x01 << 3))

I2C Maximum rise time (Master mode) [3] (in _I2C_TRISER)

Definition at line 1608 of file STM8AF_STM8S.h.

◆ _I2C_TRISE4

#define _I2C_TRISE4 ((uint8_t) (0x01 << 4))

I2C Maximum rise time (Master mode) [4] (in _I2C_TRISER)

Definition at line 1609 of file STM8AF_STM8S.h.

◆ _I2C_TRISE5

#define _I2C_TRISE5 ((uint8_t) (0x01 << 5))

I2C Maximum rise time (Master mode) [5] (in _I2C_TRISER)

Definition at line 1610 of file STM8AF_STM8S.h.

◆ _I2C_TRISER

#define _I2C_TRISER _SFR(uint8_t, I2C_AddressBase+0x0D)

I2C rise time register.

Definition at line 1499 of file STM8AF_STM8S.h.

◆ _I2C_TRISER_RESET_VALUE

#define _I2C_TRISER_RESET_VALUE ((uint8_t) 0x02)

I2C rise time register reset value.

Definition at line 1515 of file STM8AF_STM8S.h.

◆ _I2C_TXE

#define _I2C_TXE ((uint8_t) (0x01 << 7))

I2C Data register empty (transmitters) [0] (in _I2C_SR1)

Definition at line 1568 of file STM8AF_STM8S.h.

◆ _I2C_WUFH

#define _I2C_WUFH ((uint8_t) (0x01 << 5))

I2C Wakeup from Halt [0] (in _I2C_SR2)

Definition at line 1576 of file STM8AF_STM8S.h.

◆ _ITC

#define _ITC _SFR(ITC_t, ITC_AddressBase)

ITC struct/bit access.

Definition at line 6401 of file STM8AF_STM8S.h.

◆ _ITC_SPR1

#define _ITC_SPR1 _SFR(uint8_t, ITC_AddressBase+0x00)

Interrupt priority register 1/8.

Definition at line 6402 of file STM8AF_STM8S.h.

◆ _ITC_SPR1_RESET_VALUE

#define _ITC_SPR1_RESET_VALUE ((uint8_t) 0xFF)

Interrupt priority register 1/8 reset value.

Definition at line 6412 of file STM8AF_STM8S.h.

◆ _ITC_SPR2

#define _ITC_SPR2 _SFR(uint8_t, ITC_AddressBase+0x01)

Interrupt priority register 2/8.

Definition at line 6403 of file STM8AF_STM8S.h.

◆ _ITC_SPR2_RESET_VALUE

#define _ITC_SPR2_RESET_VALUE ((uint8_t) 0xFF)

Interrupt priority register 2/8 reset value.

Definition at line 6413 of file STM8AF_STM8S.h.

◆ _ITC_SPR3

#define _ITC_SPR3 _SFR(uint8_t, ITC_AddressBase+0x02)

Interrupt priority register 3/8.

Definition at line 6404 of file STM8AF_STM8S.h.

◆ _ITC_SPR3_RESET_VALUE

#define _ITC_SPR3_RESET_VALUE ((uint8_t) 0xFF)

Interrupt priority register 3/8 reset value.

Definition at line 6414 of file STM8AF_STM8S.h.

◆ _ITC_SPR4

#define _ITC_SPR4 _SFR(uint8_t, ITC_AddressBase+0x03)

Interrupt priority register 4/8.

Definition at line 6405 of file STM8AF_STM8S.h.

◆ _ITC_SPR4_RESET_VALUE

#define _ITC_SPR4_RESET_VALUE ((uint8_t) 0xFF)

Interrupt priority register 4/8 reset value.

Definition at line 6415 of file STM8AF_STM8S.h.

◆ _ITC_SPR5

#define _ITC_SPR5 _SFR(uint8_t, ITC_AddressBase+0x04)

Interrupt priority register 5/8.

Definition at line 6406 of file STM8AF_STM8S.h.

◆ _ITC_SPR5_RESET_VALUE

#define _ITC_SPR5_RESET_VALUE ((uint8_t) 0xFF)

Interrupt priority register 5/8 reset value.

Definition at line 6416 of file STM8AF_STM8S.h.

◆ _ITC_SPR6

#define _ITC_SPR6 _SFR(uint8_t, ITC_AddressBase+0x05)

Interrupt priority register 6/8.

Definition at line 6407 of file STM8AF_STM8S.h.

◆ _ITC_SPR6_RESET_VALUE

#define _ITC_SPR6_RESET_VALUE ((uint8_t) 0xFF)

Interrupt priority register 6/8 reset value.

Definition at line 6417 of file STM8AF_STM8S.h.

◆ _ITC_SPR7

#define _ITC_SPR7 _SFR(uint8_t, ITC_AddressBase+0x06)

Interrupt priority register 7/8.

Definition at line 6408 of file STM8AF_STM8S.h.

◆ _ITC_SPR7_RESET_VALUE

#define _ITC_SPR7_RESET_VALUE ((uint8_t) 0xFF)

Interrupt priority register 7/8 reset value.

Definition at line 6418 of file STM8AF_STM8S.h.

◆ _ITC_SPR8

#define _ITC_SPR8 _SFR(uint8_t, ITC_AddressBase+0x07)

Interrupt priority register 8/8.

Definition at line 6409 of file STM8AF_STM8S.h.

◆ _ITC_SPR8_RESET_VALUE

#define _ITC_SPR8_RESET_VALUE ((uint8_t) 0x0F)

Interrupt priority register 8/8 reset value.

Definition at line 6419 of file STM8AF_STM8S.h.

◆ _ITC_VECT10SPR

#define _ITC_VECT10SPR ((uint8_t) (0x03 << 4))

ITC interrupt priority vector 10 [1:0] (in _ITC_SPR3)

Definition at line 6454 of file STM8AF_STM8S.h.

◆ _ITC_VECT10SPR0

#define _ITC_VECT10SPR0 ((uint8_t) (0x01 << 4))

ITC interrupt priority vector 10 [0] (in _ITC_SPR3)

Definition at line 6455 of file STM8AF_STM8S.h.

◆ _ITC_VECT10SPR1

#define _ITC_VECT10SPR1 ((uint8_t) (0x01 << 5))

ITC interrupt priority vector 10 [1] (in _ITC_SPR3)

Definition at line 6456 of file STM8AF_STM8S.h.

◆ _ITC_VECT11SPR

#define _ITC_VECT11SPR ((uint8_t) (0x03 << 6))

ITC interrupt priority vector 11 [1:0] (in _ITC_SPR3)

Definition at line 6457 of file STM8AF_STM8S.h.

◆ _ITC_VECT11SPR0

#define _ITC_VECT11SPR0 ((uint8_t) (0x01 << 6))

ITC interrupt priority vector 11 [0] (in _ITC_SPR3)

Definition at line 6458 of file STM8AF_STM8S.h.

◆ _ITC_VECT11SPR1

#define _ITC_VECT11SPR1 ((uint8_t) (0x01 << 7))

ITC interrupt priority vector 11 [1] (in _ITC_SPR3)

Definition at line 6459 of file STM8AF_STM8S.h.

◆ _ITC_VECT12SPR

#define _ITC_VECT12SPR ((uint8_t) (0x03 << 0))

ITC interrupt priority vector 12 [1:0] (in _ITC_SPR4)

Definition at line 6462 of file STM8AF_STM8S.h.

◆ _ITC_VECT12SPR0

#define _ITC_VECT12SPR0 ((uint8_t) (0x01 << 0))

ITC interrupt priority vector 12 [0] (in _ITC_SPR4)

Definition at line 6463 of file STM8AF_STM8S.h.

◆ _ITC_VECT12SPR1

#define _ITC_VECT12SPR1 ((uint8_t) (0x01 << 1))

ITC interrupt priority vector 12 [1] (in _ITC_SPR4)

Definition at line 6464 of file STM8AF_STM8S.h.

◆ _ITC_VECT13SPR

#define _ITC_VECT13SPR ((uint8_t) (0x03 << 2))

ITC interrupt priority vector 13 [1:0] (in _ITC_SPR4)

Definition at line 6465 of file STM8AF_STM8S.h.

◆ _ITC_VECT13SPR0

#define _ITC_VECT13SPR0 ((uint8_t) (0x01 << 2))

ITC interrupt priority vector 13 [0] (in _ITC_SPR4)

Definition at line 6466 of file STM8AF_STM8S.h.

◆ _ITC_VECT13SPR1

#define _ITC_VECT13SPR1 ((uint8_t) (0x01 << 3))

ITC interrupt priority vector 13 [1] (in _ITC_SPR4)

Definition at line 6467 of file STM8AF_STM8S.h.

◆ _ITC_VECT14SPR

#define _ITC_VECT14SPR ((uint8_t) (0x03 << 4))

ITC interrupt priority vector 14 [1:0] (in _ITC_SPR4)

Definition at line 6468 of file STM8AF_STM8S.h.

◆ _ITC_VECT14SPR0

#define _ITC_VECT14SPR0 ((uint8_t) (0x01 << 4))

ITC interrupt priority vector 14 [0] (in _ITC_SPR4)

Definition at line 6469 of file STM8AF_STM8S.h.

◆ _ITC_VECT14SPR1

#define _ITC_VECT14SPR1 ((uint8_t) (0x01 << 5))

ITC interrupt priority vector 14 [1] (in _ITC_SPR4)

Definition at line 6470 of file STM8AF_STM8S.h.

◆ _ITC_VECT15SPR

#define _ITC_VECT15SPR ((uint8_t) (0x03 << 6))

ITC interrupt priority vector 15 [1:0] (in _ITC_SPR4)

Definition at line 6471 of file STM8AF_STM8S.h.

◆ _ITC_VECT15SPR0

#define _ITC_VECT15SPR0 ((uint8_t) (0x01 << 6))

ITC interrupt priority vector 15 [0] (in _ITC_SPR4)

Definition at line 6472 of file STM8AF_STM8S.h.

◆ _ITC_VECT15SPR1

#define _ITC_VECT15SPR1 ((uint8_t) (0x01 << 7))

ITC interrupt priority vector 15 [1] (in _ITC_SPR4)

Definition at line 6473 of file STM8AF_STM8S.h.

◆ _ITC_VECT16SPR

#define _ITC_VECT16SPR ((uint8_t) (0x03 << 0))

ITC interrupt priority vector 16 [1:0] (in _ITC_SPR5)

Definition at line 6476 of file STM8AF_STM8S.h.

◆ _ITC_VECT16SPR0

#define _ITC_VECT16SPR0 ((uint8_t) (0x01 << 0))

ITC interrupt priority vector 16 [0] (in _ITC_SPR5)

Definition at line 6477 of file STM8AF_STM8S.h.

◆ _ITC_VECT16SPR1

#define _ITC_VECT16SPR1 ((uint8_t) (0x01 << 1))

ITC interrupt priority vector 16 [1] (in _ITC_SPR5)

Definition at line 6478 of file STM8AF_STM8S.h.

◆ _ITC_VECT17SPR

#define _ITC_VECT17SPR ((uint8_t) (0x03 << 2))

ITC interrupt priority vector 17 [1:0] (in _ITC_SPR5)

Definition at line 6479 of file STM8AF_STM8S.h.

◆ _ITC_VECT17SPR0

#define _ITC_VECT17SPR0 ((uint8_t) (0x01 << 2))

ITC interrupt priority vector 17 [0] (in _ITC_SPR5)

Definition at line 6480 of file STM8AF_STM8S.h.

◆ _ITC_VECT17SPR1

#define _ITC_VECT17SPR1 ((uint8_t) (0x01 << 3))

ITC interrupt priority vector 17 [1] (in _ITC_SPR5)

Definition at line 6481 of file STM8AF_STM8S.h.

◆ _ITC_VECT18SPR

#define _ITC_VECT18SPR ((uint8_t) (0x03 << 4))

ITC interrupt priority vector 18 [1:0] (in _ITC_SPR5)

Definition at line 6482 of file STM8AF_STM8S.h.

◆ _ITC_VECT18SPR0

#define _ITC_VECT18SPR0 ((uint8_t) (0x01 << 4))

ITC interrupt priority vector 18 [0] (in _ITC_SPR5)

Definition at line 6483 of file STM8AF_STM8S.h.

◆ _ITC_VECT18SPR1

#define _ITC_VECT18SPR1 ((uint8_t) (0x01 << 5))

ITC interrupt priority vector 18 [1] (in _ITC_SPR5)

Definition at line 6484 of file STM8AF_STM8S.h.

◆ _ITC_VECT19SPR

#define _ITC_VECT19SPR ((uint8_t) (0x03 << 6))

ITC interrupt priority vector 19 [1:0] (in _ITC_SPR5)

Definition at line 6485 of file STM8AF_STM8S.h.

◆ _ITC_VECT19SPR0

#define _ITC_VECT19SPR0 ((uint8_t) (0x01 << 6))

ITC interrupt priority vector 19 [0] (in _ITC_SPR5)

Definition at line 6486 of file STM8AF_STM8S.h.

◆ _ITC_VECT19SPR1

#define _ITC_VECT19SPR1 ((uint8_t) (0x01 << 7))

ITC interrupt priority vector 19 [1] (in _ITC_SPR5)

Definition at line 6487 of file STM8AF_STM8S.h.

◆ _ITC_VECT1SPR

#define _ITC_VECT1SPR ((uint8_t) (0x03 << 2))

ITC interrupt priority vector 1 [1:0] (in _ITC_SPR1)

Definition at line 6423 of file STM8AF_STM8S.h.

◆ _ITC_VECT1SPR0

#define _ITC_VECT1SPR0 ((uint8_t) (0x01 << 2))

ITC interrupt priority vector 1 [0] (in _ITC_SPR1)

Definition at line 6424 of file STM8AF_STM8S.h.

◆ _ITC_VECT1SPR1

#define _ITC_VECT1SPR1 ((uint8_t) (0x01 << 3))

ITC interrupt priority vector 1 [1] (in _ITC_SPR1)

Definition at line 6425 of file STM8AF_STM8S.h.

◆ _ITC_VECT20SPR

#define _ITC_VECT20SPR ((uint8_t) (0x03 << 0))

ITC interrupt priority vector 20 [1:0] (in _ITC_SPR6)

Definition at line 6490 of file STM8AF_STM8S.h.

◆ _ITC_VECT20SPR0

#define _ITC_VECT20SPR0 ((uint8_t) (0x01 << 0))

ITC interrupt priority vector 20 [0] (in _ITC_SPR6)

Definition at line 6491 of file STM8AF_STM8S.h.

◆ _ITC_VECT20SPR1

#define _ITC_VECT20SPR1 ((uint8_t) (0x01 << 1))

ITC interrupt priority vector 20 [1] (in _ITC_SPR6)

Definition at line 6492 of file STM8AF_STM8S.h.

◆ _ITC_VECT21SPR

#define _ITC_VECT21SPR ((uint8_t) (0x03 << 2))

ITC interrupt priority vector 21 [1:0] (in _ITC_SPR6)

Definition at line 6493 of file STM8AF_STM8S.h.

◆ _ITC_VECT21SPR0

#define _ITC_VECT21SPR0 ((uint8_t) (0x01 << 2))

ITC interrupt priority vector 21 [0] (in _ITC_SPR6)

Definition at line 6494 of file STM8AF_STM8S.h.

◆ _ITC_VECT21SPR1

#define _ITC_VECT21SPR1 ((uint8_t) (0x01 << 3))

ITC interrupt priority vector 21 [1] (in _ITC_SPR6)

Definition at line 6495 of file STM8AF_STM8S.h.

◆ _ITC_VECT22SPR

#define _ITC_VECT22SPR ((uint8_t) (0x03 << 4))

ITC interrupt priority vector 22 [1:0] (in _ITC_SPR6)

Definition at line 6496 of file STM8AF_STM8S.h.

◆ _ITC_VECT22SPR0

#define _ITC_VECT22SPR0 ((uint8_t) (0x01 << 4))

ITC interrupt priority vector 22 [0] (in _ITC_SPR6)

Definition at line 6497 of file STM8AF_STM8S.h.

◆ _ITC_VECT22SPR1

#define _ITC_VECT22SPR1 ((uint8_t) (0x01 << 5))

ITC interrupt priority vector 22 [1] (in _ITC_SPR6)

Definition at line 6498 of file STM8AF_STM8S.h.

◆ _ITC_VECT23SPR

#define _ITC_VECT23SPR ((uint8_t) (0x03 << 6))

ITC interrupt priority vector 23 [1:0] (in _ITC_SPR6)

Definition at line 6499 of file STM8AF_STM8S.h.

◆ _ITC_VECT23SPR0

#define _ITC_VECT23SPR0 ((uint8_t) (0x01 << 6))

ITC interrupt priority vector 23 [0] (in _ITC_SPR6)

Definition at line 6500 of file STM8AF_STM8S.h.

◆ _ITC_VECT23SPR1

#define _ITC_VECT23SPR1 ((uint8_t) (0x01 << 7))

ITC interrupt priority vector 23 [1] (in _ITC_SPR6)

Definition at line 6501 of file STM8AF_STM8S.h.

◆ _ITC_VECT24SPR

#define _ITC_VECT24SPR ((uint8_t) (0x03 << 0))

ITC interrupt priority vector 24 [1:0] (in _ITC_SPR7)

Definition at line 6504 of file STM8AF_STM8S.h.

◆ _ITC_VECT24SPR0

#define _ITC_VECT24SPR0 ((uint8_t) (0x01 << 0))

ITC interrupt priority vector 24 [0] (in _ITC_SPR7)

Definition at line 6505 of file STM8AF_STM8S.h.

◆ _ITC_VECT24SPR1

#define _ITC_VECT24SPR1 ((uint8_t) (0x01 << 1))

ITC interrupt priority vector 24 [1] (in _ITC_SPR7)

Definition at line 6506 of file STM8AF_STM8S.h.

◆ _ITC_VECT25SPR

#define _ITC_VECT25SPR ((uint8_t) (0x03 << 2))

ITC interrupt priority vector 25 [1:0] (in _ITC_SPR7)

Definition at line 6507 of file STM8AF_STM8S.h.

◆ _ITC_VECT25SPR0

#define _ITC_VECT25SPR0 ((uint8_t) (0x01 << 2))

ITC interrupt priority vector 25 [0] (in _ITC_SPR7)

Definition at line 6508 of file STM8AF_STM8S.h.

◆ _ITC_VECT25SPR1

#define _ITC_VECT25SPR1 ((uint8_t) (0x01 << 3))

ITC interrupt priority vector 25 [1] (in _ITC_SPR7)

Definition at line 6509 of file STM8AF_STM8S.h.

◆ _ITC_VECT26SPR

#define _ITC_VECT26SPR ((uint8_t) (0x03 << 4))

ITC interrupt priority vector 26 [1:0] (in _ITC_SPR7)

Definition at line 6510 of file STM8AF_STM8S.h.

◆ _ITC_VECT26SPR0

#define _ITC_VECT26SPR0 ((uint8_t) (0x01 << 4))

ITC interrupt priority vector 26 [0] (in _ITC_SPR7)

Definition at line 6511 of file STM8AF_STM8S.h.

◆ _ITC_VECT26SPR1

#define _ITC_VECT26SPR1 ((uint8_t) (0x01 << 5))

ITC interrupt priority vector 26 [1] (in _ITC_SPR7)

Definition at line 6512 of file STM8AF_STM8S.h.

◆ _ITC_VECT27SPR

#define _ITC_VECT27SPR ((uint8_t) (0x03 << 6))

ITC interrupt priority vector 27 [1:0] (in _ITC_SPR7)

Definition at line 6513 of file STM8AF_STM8S.h.

◆ _ITC_VECT27SPR0

#define _ITC_VECT27SPR0 ((uint8_t) (0x01 << 6))

ITC interrupt priority vector 27 [0] (in _ITC_SPR7)

Definition at line 6514 of file STM8AF_STM8S.h.

◆ _ITC_VECT27SPR1

#define _ITC_VECT27SPR1 ((uint8_t) (0x01 << 7))

ITC interrupt priority vector 27 [1] (in _ITC_SPR7)

Definition at line 6515 of file STM8AF_STM8S.h.

◆ _ITC_VECT28SPR

#define _ITC_VECT28SPR ((uint8_t) (0x03 << 0))

ITC interrupt priority vector 28 [1:0] (in _ITC_SPR8)

Definition at line 6518 of file STM8AF_STM8S.h.

◆ _ITC_VECT28SPR0

#define _ITC_VECT28SPR0 ((uint8_t) (0x01 << 0))

ITC interrupt priority vector 28 [0] (in _ITC_SPR8)

Definition at line 6519 of file STM8AF_STM8S.h.

◆ _ITC_VECT28SPR1

#define _ITC_VECT28SPR1 ((uint8_t) (0x01 << 1))

ITC interrupt priority vector 28 [1] (in _ITC_SPR8)

Definition at line 6520 of file STM8AF_STM8S.h.

◆ _ITC_VECT29SPR

#define _ITC_VECT29SPR ((uint8_t) (0x03 << 2))

ITC interrupt priority vector 29 [1:0] (in _ITC_SPR8)

Definition at line 6521 of file STM8AF_STM8S.h.

◆ _ITC_VECT29SPR0

#define _ITC_VECT29SPR0 ((uint8_t) (0x01 << 2))

ITC interrupt priority vector 29 [0] (in _ITC_SPR8)

Definition at line 6522 of file STM8AF_STM8S.h.

◆ _ITC_VECT29SPR1

#define _ITC_VECT29SPR1 ((uint8_t) (0x01 << 3))

ITC interrupt priority vector 29 [1] (in _ITC_SPR8)

Definition at line 6523 of file STM8AF_STM8S.h.

◆ _ITC_VECT2SPR

#define _ITC_VECT2SPR ((uint8_t) (0x03 << 4))

ITC interrupt priority vector 2 [1:0] (in _ITC_SPR1)

Definition at line 6426 of file STM8AF_STM8S.h.

◆ _ITC_VECT2SPR0

#define _ITC_VECT2SPR0 ((uint8_t) (0x01 << 4))

ITC interrupt priority vector 2 [0] (in _ITC_SPR1)

Definition at line 6427 of file STM8AF_STM8S.h.

◆ _ITC_VECT2SPR1

#define _ITC_VECT2SPR1 ((uint8_t) (0x01 << 5))

ITC interrupt priority vector 2 [1] (in _ITC_SPR1)

Definition at line 6428 of file STM8AF_STM8S.h.

◆ _ITC_VECT3SPR

#define _ITC_VECT3SPR ((uint8_t) (0x03 << 6))

ITC interrupt priority vector 3 [1:0] (in _ITC_SPR1)

Definition at line 6429 of file STM8AF_STM8S.h.

◆ _ITC_VECT3SPR0

#define _ITC_VECT3SPR0 ((uint8_t) (0x01 << 6))

ITC interrupt priority vector 3 [0] (in _ITC_SPR1)

Definition at line 6430 of file STM8AF_STM8S.h.

◆ _ITC_VECT3SPR1

#define _ITC_VECT3SPR1 ((uint8_t) (0x01 << 7))

ITC interrupt priority vector 3 [1] (in _ITC_SPR1)

Definition at line 6431 of file STM8AF_STM8S.h.

◆ _ITC_VECT4SPR

#define _ITC_VECT4SPR ((uint8_t) (0x03 << 0))

ITC interrupt priority vector 4 [1:0] (in _ITC_SPR2)

Definition at line 6434 of file STM8AF_STM8S.h.

◆ _ITC_VECT4SPR0

#define _ITC_VECT4SPR0 ((uint8_t) (0x01 << 0))

ITC interrupt priority vector 4 [0] (in _ITC_SPR2)

Definition at line 6435 of file STM8AF_STM8S.h.

◆ _ITC_VECT4SPR1

#define _ITC_VECT4SPR1 ((uint8_t) (0x01 << 1))

ITC interrupt priority vector 4 [1] (in _ITC_SPR2)

Definition at line 6436 of file STM8AF_STM8S.h.

◆ _ITC_VECT5SPR

#define _ITC_VECT5SPR ((uint8_t) (0x03 << 2))

ITC interrupt priority vector 5 [1:0] (in _ITC_SPR2)

Definition at line 6437 of file STM8AF_STM8S.h.

◆ _ITC_VECT5SPR0

#define _ITC_VECT5SPR0 ((uint8_t) (0x01 << 2))

ITC interrupt priority vector 5 [0] (in _ITC_SPR2)

Definition at line 6438 of file STM8AF_STM8S.h.

◆ _ITC_VECT5SPR1

#define _ITC_VECT5SPR1 ((uint8_t) (0x01 << 3))

ITC interrupt priority vector 5 [1] (in _ITC_SPR2)

Definition at line 6439 of file STM8AF_STM8S.h.

◆ _ITC_VECT6SPR

#define _ITC_VECT6SPR ((uint8_t) (0x03 << 4))

ITC interrupt priority vector 6 [1:0] (in _ITC_SPR2)

Definition at line 6440 of file STM8AF_STM8S.h.

◆ _ITC_VECT6SPR0

#define _ITC_VECT6SPR0 ((uint8_t) (0x01 << 4))

ITC interrupt priority vector 6 [0] (in _ITC_SPR2)

Definition at line 6441 of file STM8AF_STM8S.h.

◆ _ITC_VECT6SPR1

#define _ITC_VECT6SPR1 ((uint8_t) (0x01 << 5))

ITC interrupt priority vector 6 [1] (in _ITC_SPR2)

Definition at line 6442 of file STM8AF_STM8S.h.

◆ _ITC_VECT7SPR

#define _ITC_VECT7SPR ((uint8_t) (0x03 << 6))

ITC interrupt priority vector 7 [1:0] (in _ITC_SPR2)

Definition at line 6443 of file STM8AF_STM8S.h.

◆ _ITC_VECT7SPR0

#define _ITC_VECT7SPR0 ((uint8_t) (0x01 << 6))

ITC interrupt priority vector 7 [0] (in _ITC_SPR2)

Definition at line 6444 of file STM8AF_STM8S.h.

◆ _ITC_VECT7SPR1

#define _ITC_VECT7SPR1 ((uint8_t) (0x01 << 7))

ITC interrupt priority vector 7 [1] (in _ITC_SPR2)

Definition at line 6445 of file STM8AF_STM8S.h.

◆ _ITC_VECT8SPR

#define _ITC_VECT8SPR ((uint8_t) (0x03 << 0))

ITC interrupt priority vector 8 [1:0] (in _ITC_SPR3)

Definition at line 6448 of file STM8AF_STM8S.h.

◆ _ITC_VECT8SPR0

#define _ITC_VECT8SPR0 ((uint8_t) (0x01 << 0))

ITC interrupt priority vector 8 [0] (in _ITC_SPR3)

Definition at line 6449 of file STM8AF_STM8S.h.

◆ _ITC_VECT8SPR1

#define _ITC_VECT8SPR1 ((uint8_t) (0x01 << 1))

ITC interrupt priority vector 8 [1] (in _ITC_SPR3)

Definition at line 6450 of file STM8AF_STM8S.h.

◆ _ITC_VECT9SPR

#define _ITC_VECT9SPR ((uint8_t) (0x03 << 2))

ITC interrupt priority vector 9 [1:0] (in _ITC_SPR3)

Definition at line 6451 of file STM8AF_STM8S.h.

◆ _ITC_VECT9SPR0

#define _ITC_VECT9SPR0 ((uint8_t) (0x01 << 2))

ITC interrupt priority vector 9 [0] (in _ITC_SPR3)

Definition at line 6452 of file STM8AF_STM8S.h.

◆ _ITC_VECT9SPR1

#define _ITC_VECT9SPR1 ((uint8_t) (0x01 << 3))

ITC interrupt priority vector 9 [1] (in _ITC_SPR3)

Definition at line 6453 of file STM8AF_STM8S.h.

◆ _IWDG

#define _IWDG _SFR(IWDG_t, IWDG_AddressBase)

Independent Timeout Watchdog struct/bit access.

Definition at line 1069 of file STM8AF_STM8S.h.

◆ _IWDG_KEY_ACCESS

#define _IWDG_KEY_ACCESS ((uint8_t) 0x55)

Independent Timeout Watchdog unlock write to IWDG_PR and IWDG_RLR (in _IWDG_KR)

Definition at line 1081 of file STM8AF_STM8S.h.

◆ _IWDG_KEY_ENABLE

#define _IWDG_KEY_ENABLE ((uint8_t) 0xCC)

Independent Timeout Watchdog enable (in _IWDG_KR)

Definition at line 1079 of file STM8AF_STM8S.h.

◆ _IWDG_KEY_REFRESH

#define _IWDG_KEY_REFRESH ((uint8_t) 0xAA)

Independent Timeout Watchdog refresh (in _IWDG_KR)

Definition at line 1080 of file STM8AF_STM8S.h.

◆ _IWDG_KR

#define _IWDG_KR _SFR(uint8_t, IWDG_AddressBase+0x00)

Independent Timeout Watchdog Key register (IWDG_KR)

Definition at line 1070 of file STM8AF_STM8S.h.

◆ _IWDG_PR

#define _IWDG_PR _SFR(uint8_t, IWDG_AddressBase+0x01)

Independent Timeout Watchdog Prescaler register (IWDG_PR)

Definition at line 1071 of file STM8AF_STM8S.h.

◆ _IWDG_PR_RESET_VALUE

#define _IWDG_PR_RESET_VALUE ((uint8_t) 0x00)

Independent Timeout Watchdog Prescaler register reset value.

Definition at line 1075 of file STM8AF_STM8S.h.

◆ _IWDG_PRE

#define _IWDG_PRE ((uint8_t) (0x07 << 0))

Independent Timeout Watchdog Prescaler divider [2:0] (in _IWDG_PR)

Definition at line 1084 of file STM8AF_STM8S.h.

◆ _IWDG_PRE0

#define _IWDG_PRE0 ((uint8_t) (0x01 << 0))

Independent Timeout Watchdog Prescaler divider [0] (in _IWDG_PR)

Definition at line 1085 of file STM8AF_STM8S.h.

◆ _IWDG_PRE1

#define _IWDG_PRE1 ((uint8_t) (0x01 << 1))

Independent Timeout Watchdog Prescaler divider [1] (in _IWDG_PR)

Definition at line 1086 of file STM8AF_STM8S.h.

◆ _IWDG_PRE2

#define _IWDG_PRE2 ((uint8_t) (0x01 << 2))

Independent Timeout Watchdog Prescaler divider [2] (in _IWDG_PR)

Definition at line 1087 of file STM8AF_STM8S.h.

◆ _IWDG_RLR

#define _IWDG_RLR _SFR(uint8_t, IWDG_AddressBase+0x02)

Independent Timeout Watchdog Reload register (IWDG_RLR)

Definition at line 1072 of file STM8AF_STM8S.h.

◆ _IWDG_RLR_RESET_VALUE

#define _IWDG_RLR_RESET_VALUE ((uint8_t) 0xFF)

Independent Timeout Watchdog Reload register reset value.

Definition at line 1076 of file STM8AF_STM8S.h.

◆ _RST

#define _RST _SFR(RST_t, RST_AddressBase)

Reset module struct/bit access.

Definition at line 725 of file STM8AF_STM8S.h.

◆ _RST_EMCF

#define _RST_EMCF ((uint8_t) (0x01 << 4))

EMC reset flag [0] (in _RST_SR)

Definition at line 733 of file STM8AF_STM8S.h.

◆ _RST_ILLOPF

#define _RST_ILLOPF ((uint8_t) (0x01 << 2))

Illegal opcode reset flag [0] (in _RST_SR)

Definition at line 731 of file STM8AF_STM8S.h.

◆ _RST_IWDGF

#define _RST_IWDGF ((uint8_t) (0x01 << 1))

Independent Watchdog reset flag [0] (in _RST_SR)

Definition at line 730 of file STM8AF_STM8S.h.

◆ _RST_SR

#define _RST_SR _SFR(uint8_t, RST_AddressBase+0x00)

Reset module status register (RST_SR)

Definition at line 726 of file STM8AF_STM8S.h.

◆ _RST_SWIMF

#define _RST_SWIMF ((uint8_t) (0x01 << 3))

SWIM reset flag [0] (in _RST_SR)

Definition at line 732 of file STM8AF_STM8S.h.

◆ _RST_WWDGF

#define _RST_WWDGF ((uint8_t) (0x01 << 0))

Window Watchdog reset flag [0] (in _RST_SR)

Definition at line 729 of file STM8AF_STM8S.h.

◆ _SFR

#define _SFR	(	type,
		addr
	)	(((volatile type) (addr)))

peripheral register

Definition at line 187 of file STM8AF_STM8S.h.

◆ _SPI

#define _SPI _SFR(SPI_t, SPI_AddressBase)

register for SPI control

SPI struct/bit access

Definition at line 1288 of file STM8AF_STM8S.h.

◆ _SPI_BDM

#define _SPI_BDM ((uint8_t) (0x01 << 7))

SPI Bidirectional data mode enable [0] (in _SPI_CR2)

Definition at line 1327 of file STM8AF_STM8S.h.

◆ _SPI_BDOE

#define _SPI_BDOE ((uint8_t) (0x01 << 6))

SPI Input/Output enable in bidirectional mode [0] (in _SPI_CR2)

Definition at line 1326 of file STM8AF_STM8S.h.

◆ _SPI_BR

#define _SPI_BR ((uint8_t) (0x07 << 3))

SPI Baudrate control [2:0] (in _SPI_CR1)

Definition at line 1312 of file STM8AF_STM8S.h.

◆ _SPI_BR0

#define _SPI_BR0 ((uint8_t) (0x01 << 3))

SPI Baudrate control [0] (in _SPI_CR1)

Definition at line 1313 of file STM8AF_STM8S.h.

◆ _SPI_BR1

#define _SPI_BR1 ((uint8_t) (0x01 << 4))

SPI Baudrate control [1] (in _SPI_CR1)

Definition at line 1314 of file STM8AF_STM8S.h.

◆ _SPI_BR2

#define _SPI_BR2 ((uint8_t) (0x01 << 5))

SPI Baudrate control [2] (in _SPI_CR1)

Definition at line 1315 of file STM8AF_STM8S.h.

◆ _SPI_BSY

#define _SPI_BSY ((uint8_t) (0x01 << 7))

SPI Busy flag [0] (in _SPI_SR)

Definition at line 1344 of file STM8AF_STM8S.h.

◆ _SPI_CPHA

#define _SPI_CPHA ((uint8_t) (0x01 << 0))

SPI Clock phase [0] (in _SPI_CR1)

Definition at line 1309 of file STM8AF_STM8S.h.

◆ _SPI_CPOL

#define _SPI_CPOL ((uint8_t) (0x01 << 1))

SPI Clock polarity [0] (in _SPI_CR1)

Definition at line 1310 of file STM8AF_STM8S.h.

◆ _SPI_CR1

#define _SPI_CR1 _SFR(uint8_t, SPI_AddressBase+0x00)

SPI control register 1.

Definition at line 1289 of file STM8AF_STM8S.h.

◆ _SPI_CR1_RESET_VALUE

#define _SPI_CR1_RESET_VALUE ((uint8_t) 0x00)

SPI Control Register 1 reset value.

Definition at line 1299 of file STM8AF_STM8S.h.

◆ _SPI_CR2

#define _SPI_CR2 _SFR(uint8_t, SPI_AddressBase+0x01)

SPI control register 2.

Definition at line 1290 of file STM8AF_STM8S.h.

◆ _SPI_CR2_RESET_VALUE

#define _SPI_CR2_RESET_VALUE ((uint8_t) 0x00)

SPI Control Register 2 reset value.

Definition at line 1300 of file STM8AF_STM8S.h.

◆ _SPI_CRCEN

#define _SPI_CRCEN ((uint8_t) (0x01 << 5))

SPI Hardware CRC calculation enable [0] (in _SPI_CR2)

Definition at line 1325 of file STM8AF_STM8S.h.

◆ _SPI_CRCERR

#define _SPI_CRCERR ((uint8_t) (0x01 << 4))

SPI CRC error flag [0] (in _SPI_SR)

Definition at line 1341 of file STM8AF_STM8S.h.

◆ _SPI_CRCNEXT

#define _SPI_CRCNEXT ((uint8_t) (0x01 << 4))

SPI Transmit CRC next [0] (in _SPI_CR2)

Definition at line 1324 of file STM8AF_STM8S.h.

◆ _SPI_CRCPR

#define _SPI_CRCPR _SFR(uint8_t, SPI_AddressBase+0x05)

SPI CRC polynomial register.

Definition at line 1294 of file STM8AF_STM8S.h.

◆ _SPI_CRCPR_RESET_VALUE

#define _SPI_CRCPR_RESET_VALUE ((uint8_t) 0x07)

SPI Polynomial Register reset value.

Definition at line 1304 of file STM8AF_STM8S.h.

◆ _SPI_DR

#define _SPI_DR _SFR(uint8_t, SPI_AddressBase+0x04)

SPI data register.

Definition at line 1293 of file STM8AF_STM8S.h.

◆ _SPI_DR_RESET_VALUE

#define _SPI_DR_RESET_VALUE ((uint8_t) 0x00)

SPI Data Register reset value.

Definition at line 1303 of file STM8AF_STM8S.h.

◆ _SPI_ERRIE

#define _SPI_ERRIE ((uint8_t) (0x01 << 5))

SPI Error interrupt enable [0] (in _SPI_ICR)

Definition at line 1332 of file STM8AF_STM8S.h.

◆ _SPI_ICR

#define _SPI_ICR _SFR(uint8_t, SPI_AddressBase+0x02)

SPI interrupt control register.

Definition at line 1291 of file STM8AF_STM8S.h.

◆ _SPI_ICR_RESET_VALUE

#define _SPI_ICR_RESET_VALUE ((uint8_t) 0x00)

SPI Interrupt Control Register reset value.

Definition at line 1301 of file STM8AF_STM8S.h.

◆ _SPI_LSBFIRST

#define _SPI_LSBFIRST ((uint8_t) (0x01 << 7))

SPI Frame format [0] (in _SPI_CR1)

Definition at line 1317 of file STM8AF_STM8S.h.

◆ _SPI_MODF

#define _SPI_MODF ((uint8_t) (0x01 << 5))

SPI Mode fault [0] (in _SPI_SR)

Definition at line 1342 of file STM8AF_STM8S.h.

◆ _SPI_MSTR

#define _SPI_MSTR ((uint8_t) (0x01 << 2))

SPI Master/slave selection [0] (in _SPI_CR1)

Definition at line 1311 of file STM8AF_STM8S.h.

◆ _SPI_OVR

#define _SPI_OVR ((uint8_t) (0x01 << 6))

SPI Overrun flag [0] (in _SPI_SR)

Definition at line 1343 of file STM8AF_STM8S.h.

◆ _SPI_RXCRCR

#define _SPI_RXCRCR _SFR(uint8_t, SPI_AddressBase+0x06)

SPI Rx CRC register.

Definition at line 1295 of file STM8AF_STM8S.h.

◆ _SPI_RXCRCR_RESET_VALUE

#define _SPI_RXCRCR_RESET_VALUE ((uint8_t) 0x00)

SPI RX CRC Register reset value.

Definition at line 1305 of file STM8AF_STM8S.h.

◆ _SPI_RXIE

#define _SPI_RXIE ((uint8_t) (0x01 << 6))

SPI Rx buffer not empty interrupt enable [0] (in _SPI_ICR)

Definition at line 1333 of file STM8AF_STM8S.h.

◆ _SPI_RXNE

#define _SPI_RXNE ((uint8_t) (0x01 << 0))

SPI Receive buffer not empty [0] (in _SPI_SR)

Definition at line 1337 of file STM8AF_STM8S.h.

◆ _SPI_RXONLY

#define _SPI_RXONLY ((uint8_t) (0x01 << 2))

SPI Receive only [0] (in _SPI_CR2)

Definition at line 1322 of file STM8AF_STM8S.h.

◆ _SPI_SPE

#define _SPI_SPE ((uint8_t) (0x01 << 6))

SPI enable [0] (in _SPI_CR1)

Definition at line 1316 of file STM8AF_STM8S.h.

◆ _SPI_SR

#define _SPI_SR _SFR(uint8_t, SPI_AddressBase+0x03)

SPI status register.

Definition at line 1292 of file STM8AF_STM8S.h.

◆ _SPI_SR_RESET_VALUE

#define _SPI_SR_RESET_VALUE ((uint8_t) 0x02)

SPI Status Register reset value.

Definition at line 1302 of file STM8AF_STM8S.h.

◆ _SPI_SSI

#define _SPI_SSI ((uint8_t) (0x01 << 0))

SPI Internal slave select [0] (in _SPI_CR2)

Definition at line 1320 of file STM8AF_STM8S.h.

◆ _SPI_SSM

#define _SPI_SSM ((uint8_t) (0x01 << 1))

SPI Software slave management [0] (in _SPI_CR2)

Definition at line 1321 of file STM8AF_STM8S.h.

◆ _SPI_TXCRCR

#define _SPI_TXCRCR _SFR(uint8_t, SPI_AddressBase+0x07)

SPI Tx CRC register.

Definition at line 1296 of file STM8AF_STM8S.h.

◆ _SPI_TXCRCR_RESET_VALUE

#define _SPI_TXCRCR_RESET_VALUE ((uint8_t) 0x00)

SPI TX CRC Register reset value.

Definition at line 1306 of file STM8AF_STM8S.h.

◆ _SPI_TXE

#define _SPI_TXE ((uint8_t) (0x01 << 1))

SPI Transmit buffer empty [0] (in _SPI_SR)

Definition at line 1338 of file STM8AF_STM8S.h.

◆ _SPI_TXIE

#define _SPI_TXIE ((uint8_t) (0x01 << 7))

SPI Tx buffer empty interrupt enable [0] (in _SPI_ICR)

Definition at line 1334 of file STM8AF_STM8S.h.

◆ _SPI_WKIE

#define _SPI_WKIE ((uint8_t) (0x01 << 4))

SPI Wakeup interrupt enable [0] (in _SPI_ICR)

Definition at line 1331 of file STM8AF_STM8S.h.

◆ _SPI_WKUP

#define _SPI_WKUP ((uint8_t) (0x01 << 3))

SPI Wakeup flag [0] (in _SPI_SR)

Definition at line 1340 of file STM8AF_STM8S.h.

◆ _TIM1

#define _TIM1 _SFR(TIM1_t, TIM1_AddressBase)

TIM1 struct/bit access.

Definition at line 2803 of file STM8AF_STM8S.h.

◆ _TIM1_AOE

#define _TIM1_AOE ((uint8_t) (0x01 << 6))

TIM1 Automatic output enable [0] (in _TIM1_BKR)

Definition at line 3074 of file STM8AF_STM8S.h.

◆ _TIM1_ARPE

#define _TIM1_ARPE ((uint8_t) (0x01 << 7))

TIM1 Auto-reload preload enable [0] (in _TIM1_CR1)

Definition at line 2880 of file STM8AF_STM8S.h.

◆ _TIM1_ARRH

#define _TIM1_ARRH _SFR(uint8_t, TIM1_AddressBase+0x12)

TIM1 auto-reload register high byte.

Definition at line 2822 of file STM8AF_STM8S.h.

◆ _TIM1_ARRH_RESET_VALUE

#define _TIM1_ARRH_RESET_VALUE ((uint8_t) 0xFF)

TIM1 auto-reload register high byte reset value.

Definition at line 2856 of file STM8AF_STM8S.h.

◆ _TIM1_ARRL

#define _TIM1_ARRL _SFR(uint8_t, TIM1_AddressBase+0x13)

TIM1 auto-reload register low byte.

Definition at line 2823 of file STM8AF_STM8S.h.

◆ _TIM1_ARRL_RESET_VALUE

#define _TIM1_ARRL_RESET_VALUE ((uint8_t) 0xFF)

TIM1 auto-reload register low byte reset value.

Definition at line 2857 of file STM8AF_STM8S.h.

◆ _TIM1_BG

#define _TIM1_BG ((uint8_t) (0x01 << 7))

TIM1 Break generation [0] (in _TIM1_EGR)

Definition at line 2953 of file STM8AF_STM8S.h.

◆ _TIM1_BIE

#define _TIM1_BIE ((uint8_t) (0x01 << 7))

TIM1 Break interrupt enable [0] (in _TIM1_IER)

Definition at line 2925 of file STM8AF_STM8S.h.

◆ _TIM1_BIF

#define _TIM1_BIF ((uint8_t) (0x01 << 7))

TIM1 Break interrupt flag [0] (in _TIM1_SR1)

Definition at line 2935 of file STM8AF_STM8S.h.

◆ _TIM1_BKE

#define _TIM1_BKE ((uint8_t) (0x01 << 4))

TIM1 Break enable [0] (in _TIM1_BKR)

Definition at line 3072 of file STM8AF_STM8S.h.

◆ _TIM1_BKP

#define _TIM1_BKP ((uint8_t) (0x01 << 5))

TIM1 Break polarity [0] (in _TIM1_BKR)

Definition at line 3073 of file STM8AF_STM8S.h.

◆ _TIM1_BKR

#define _TIM1_BKR _SFR(uint8_t, TIM1_AddressBase+0x1D)

TIM1 Break register.

Definition at line 2833 of file STM8AF_STM8S.h.

◆ _TIM1_BKR_RESET_VALUE

#define _TIM1_BKR_RESET_VALUE ((uint8_t) 0x00)

TIM1 Break register reset value.

Definition at line 2867 of file STM8AF_STM8S.h.

◆ _TIM1_CC1E

#define _TIM1_CC1E ((uint8_t) (0x01 << 0))

TIM1 Capture/compare 1 output enable [0] (in _TIM1_CCER1)

Definition at line 3048 of file STM8AF_STM8S.h.

◆ _TIM1_CC1G

#define _TIM1_CC1G ((uint8_t) (0x01 << 1))

TIM1 Capture/compare 1 generation [0] (in _TIM1_EGR)

Definition at line 2947 of file STM8AF_STM8S.h.

◆ _TIM1_CC1IE

#define _TIM1_CC1IE ((uint8_t) (0x01 << 1))

TIM1 Capture/compare 1 interrupt enable [0] (in _TIM1_IER)

Definition at line 2919 of file STM8AF_STM8S.h.

◆ _TIM1_CC1IF

#define _TIM1_CC1IF ((uint8_t) (0x01 << 1))

TIM1 Capture/compare 1 interrupt flag [0] (in _TIM1_SR1)

Definition at line 2929 of file STM8AF_STM8S.h.

◆ _TIM1_CC1NE

#define _TIM1_CC1NE ((uint8_t) (0x01 << 2))

TIM1 Capture/compare 1 complementary output enable [0] (in _TIM1_CCER1)

Definition at line 3050 of file STM8AF_STM8S.h.

◆ _TIM1_CC1NP

#define _TIM1_CC1NP ((uint8_t) (0x01 << 3))

TIM1 Capture/compare 1 complementary output polarity [0] (in _TIM1_CCER1)

Definition at line 3051 of file STM8AF_STM8S.h.

◆ _TIM1_CC1OF

#define _TIM1_CC1OF ((uint8_t) (0x01 << 1))

TIM1 Capture/compare 1 overcapture flag [0] (in _TIM1_SR2)

Definition at line 2939 of file STM8AF_STM8S.h.

◆ _TIM1_CC1P

#define _TIM1_CC1P ((uint8_t) (0x01 << 1))

TIM1 Capture/compare 1 output polarity [0] (in _TIM1_CCER1)

Definition at line 3049 of file STM8AF_STM8S.h.

◆ _TIM1_CC1S

#define _TIM1_CC1S ((uint8_t) (0x03 << 0))

TIM1 Compare 1 selection [1:0] (in _TIM1_CCMR1)

Definition at line 2956 of file STM8AF_STM8S.h.

◆ _TIM1_CC1S0

#define _TIM1_CC1S0 ((uint8_t) (0x01 << 0))

TIM1 Compare 1 selection [0] (in _TIM1_CCMR1)

Definition at line 2957 of file STM8AF_STM8S.h.

◆ _TIM1_CC1S1

#define _TIM1_CC1S1 ((uint8_t) (0x01 << 1))

TIM1 Compare 1 selection [1] (in _TIM1_CCMR1)

Definition at line 2958 of file STM8AF_STM8S.h.

◆ _TIM1_CC2E

#define _TIM1_CC2E ((uint8_t) (0x01 << 4))

TIM1 Capture/compare 2 output enable [0] (in _TIM1_CCER1)

Definition at line 3052 of file STM8AF_STM8S.h.

◆ _TIM1_CC2G

#define _TIM1_CC2G ((uint8_t) (0x01 << 2))

TIM1 Capture/compare 2 generation [0] (in _TIM1_EGR)

Definition at line 2948 of file STM8AF_STM8S.h.

◆ _TIM1_CC2IE

#define _TIM1_CC2IE ((uint8_t) (0x01 << 2))

TIM1 Capture/compare 2 interrupt enable [0] (in _TIM1_IER)

Definition at line 2920 of file STM8AF_STM8S.h.

◆ _TIM1_CC2IF

#define _TIM1_CC2IF ((uint8_t) (0x01 << 2))

TIM1 Capture/compare 2 interrupt flag [0] (in _TIM1_SR1)

Definition at line 2930 of file STM8AF_STM8S.h.

◆ _TIM1_CC2NE

#define _TIM1_CC2NE ((uint8_t) (0x01 << 6))

TIM1 Capture/compare 2 complementary output enable [0] (in _TIM1_CCER1)

Definition at line 3054 of file STM8AF_STM8S.h.

◆ _TIM1_CC2NP

#define _TIM1_CC2NP ((uint8_t) (0x01 << 7))

TIM1 Capture/compare 2 complementary output polarity [0] (in _TIM1_CCER1)

Definition at line 3055 of file STM8AF_STM8S.h.

◆ _TIM1_CC2OF

#define _TIM1_CC2OF ((uint8_t) (0x01 << 2))

TIM1 Capture/compare 2 overcapture flag [0] (in _TIM1_SR2)

Definition at line 2940 of file STM8AF_STM8S.h.

◆ _TIM1_CC2P

#define _TIM1_CC2P ((uint8_t) (0x01 << 5))

TIM1 Capture/compare 2 output polarity [0] (in _TIM1_CCER1)

Definition at line 3053 of file STM8AF_STM8S.h.

◆ _TIM1_CC2S

#define _TIM1_CC2S ((uint8_t) (0x03 << 0))

TIM1 Compare 2 selection [1:0] (in _TIM1_CCMR2)

Definition at line 2979 of file STM8AF_STM8S.h.

◆ _TIM1_CC2S0

#define _TIM1_CC2S0 ((uint8_t) (0x01 << 0))

TIM1 Compare 2 selection [0] (in _TIM1_CCMR2)

Definition at line 2980 of file STM8AF_STM8S.h.

◆ _TIM1_CC2S1

#define _TIM1_CC2S1 ((uint8_t) (0x01 << 1))

TIM1 Compare 2 selection [1] (in _TIM1_CCMR2)

Definition at line 2981 of file STM8AF_STM8S.h.

◆ _TIM1_CC3E

#define _TIM1_CC3E ((uint8_t) (0x01 << 0))

TIM1 Capture/compare 3 output enable [0] (in _TIM1_CCER2)

Definition at line 3058 of file STM8AF_STM8S.h.

◆ _TIM1_CC3G

#define _TIM1_CC3G ((uint8_t) (0x01 << 3))

TIM1 Capture/compare 3 generation [0] (in _TIM1_EGR)

Definition at line 2949 of file STM8AF_STM8S.h.

◆ _TIM1_CC3IE

#define _TIM1_CC3IE ((uint8_t) (0x01 << 3))

TIM1 Capture/compare 3 interrupt enable [0] (in _TIM1_IER)

Definition at line 2921 of file STM8AF_STM8S.h.

◆ _TIM1_CC3IF

#define _TIM1_CC3IF ((uint8_t) (0x01 << 3))

TIM1 Capture/compare 3 interrupt flag [0] (in _TIM1_SR1)

Definition at line 2931 of file STM8AF_STM8S.h.

◆ _TIM1_CC3NE

#define _TIM1_CC3NE ((uint8_t) (0x01 << 2))

TIM1 Capture/compare 3 complementary output enable [0] (in _TIM1_CCER2)

Definition at line 3060 of file STM8AF_STM8S.h.

◆ _TIM1_CC3NP

#define _TIM1_CC3NP ((uint8_t) (0x01 << 3))

TIM1 Capture/compare 3 complementary output polarity [0] (in _TIM1_CCER2)

Definition at line 3061 of file STM8AF_STM8S.h.

◆ _TIM1_CC3OF

#define _TIM1_CC3OF ((uint8_t) (0x01 << 3))

TIM1 Capture/compare 3 overcapture flag [0] (in _TIM1_SR2)

Definition at line 2941 of file STM8AF_STM8S.h.

◆ _TIM1_CC3P

#define _TIM1_CC3P ((uint8_t) (0x01 << 1))

TIM1 Capture/compare 3 output polarity [0] (in _TIM1_CCER2)

Definition at line 3059 of file STM8AF_STM8S.h.

◆ _TIM1_CC3S

#define _TIM1_CC3S ((uint8_t) (0x03 << 0))

TIM1 Compare 3 selection [1:0] (in _TIM1_CCMR3)

Definition at line 3002 of file STM8AF_STM8S.h.

◆ _TIM1_CC3S0

#define _TIM1_CC3S0 ((uint8_t) (0x01 << 0))

TIM1 Compare 3 selection [0] (in _TIM1_CCMR3)

Definition at line 3003 of file STM8AF_STM8S.h.

◆ _TIM1_CC3S1

#define _TIM1_CC3S1 ((uint8_t) (0x01 << 1))

TIM1 Compare 3 selection [1] (in _TIM1_CCMR3)

Definition at line 3004 of file STM8AF_STM8S.h.

◆ _TIM1_CC4E

#define _TIM1_CC4E ((uint8_t) (0x01 << 4))

TIM1 Capture/compare 4 output enable [0] (in _TIM1_CCER2)

Definition at line 3062 of file STM8AF_STM8S.h.

◆ _TIM1_CC4G

#define _TIM1_CC4G ((uint8_t) (0x01 << 4))

TIM1 Capture/compare 4 generation [0] (in _TIM1_EGR)

Definition at line 2950 of file STM8AF_STM8S.h.

◆ _TIM1_CC4IE

#define _TIM1_CC4IE ((uint8_t) (0x01 << 4))

TIM1 Capture/compare 4 interrupt enable [0] (in _TIM1_IER)

Definition at line 2922 of file STM8AF_STM8S.h.

◆ _TIM1_CC4IF

#define _TIM1_CC4IF ((uint8_t) (0x01 << 4))

TIM1 Capture/compare 4 interrupt flag [0] (in _TIM1_SR1)

Definition at line 2932 of file STM8AF_STM8S.h.

◆ _TIM1_CC4OF

#define _TIM1_CC4OF ((uint8_t) (0x01 << 4))

TIM1 Capture/compare 4 overcapture flag [0] (in _TIM1_SR2)

Definition at line 2942 of file STM8AF_STM8S.h.

◆ _TIM1_CC4P

#define _TIM1_CC4P ((uint8_t) (0x01 << 5))

TIM1 Capture/compare 4 output polarity [0] (in _TIM1_CCER2)

Definition at line 3063 of file STM8AF_STM8S.h.

◆ _TIM1_CC4S

#define _TIM1_CC4S ((uint8_t) (0x03 << 0))

TIM1 Compare 4 selection [1:0] (in _TIM1_CCMR4)

Definition at line 3025 of file STM8AF_STM8S.h.

◆ _TIM1_CC4S0

#define _TIM1_CC4S0 ((uint8_t) (0x01 << 0))

TIM1 Compare 4 selection [0] (in _TIM1_CCMR4)

Definition at line 3026 of file STM8AF_STM8S.h.

◆ _TIM1_CC4S1

#define _TIM1_CC4S1 ((uint8_t) (0x01 << 1))

TIM1 Compare 4 selection [1] (in _TIM1_CCMR4)

Definition at line 3027 of file STM8AF_STM8S.h.

◆ _TIM1_CCER1

#define _TIM1_CCER1 _SFR(uint8_t, TIM1_AddressBase+0x0C)

TIM1 Capture/compare enable register 1.

Definition at line 2816 of file STM8AF_STM8S.h.

◆ _TIM1_CCER1_RESET_VALUE

#define _TIM1_CCER1_RESET_VALUE ((uint8_t) 0x00)

TIM1 Capture/compare enable register 1 reset value.

Definition at line 2850 of file STM8AF_STM8S.h.

◆ _TIM1_CCER2

#define _TIM1_CCER2 _SFR(uint8_t, TIM1_AddressBase+0x0D)

TIM1 Capture/compare enable register 2.

Definition at line 2817 of file STM8AF_STM8S.h.

◆ _TIM1_CCER2_RESET_VALUE

#define _TIM1_CCER2_RESET_VALUE ((uint8_t) 0x00)

TIM1 Capture/compare enable register 2 reset value.

Definition at line 2851 of file STM8AF_STM8S.h.

◆ _TIM1_CCMR1

#define _TIM1_CCMR1 _SFR(uint8_t, TIM1_AddressBase+0x08)

TIM1 Capture/compare mode register 1.

Definition at line 2812 of file STM8AF_STM8S.h.

◆ _TIM1_CCMR1_RESET_VALUE

#define _TIM1_CCMR1_RESET_VALUE ((uint8_t) 0x00)

TIM1 Capture/compare mode register 1 reset value.

Definition at line 2846 of file STM8AF_STM8S.h.

◆ _TIM1_CCMR2

#define _TIM1_CCMR2 _SFR(uint8_t, TIM1_AddressBase+0x09)

TIM1 Capture/compare mode register 2.

Definition at line 2813 of file STM8AF_STM8S.h.

◆ _TIM1_CCMR2_RESET_VALUE

#define _TIM1_CCMR2_RESET_VALUE ((uint8_t) 0x00)

TIM1 Capture/compare mode register 2 reset value.

Definition at line 2847 of file STM8AF_STM8S.h.

◆ _TIM1_CCMR3

#define _TIM1_CCMR3 _SFR(uint8_t, TIM1_AddressBase+0x0A)

TIM1 Capture/compare mode register 3.

Definition at line 2814 of file STM8AF_STM8S.h.

◆ _TIM1_CCMR3_RESET_VALUE

#define _TIM1_CCMR3_RESET_VALUE ((uint8_t) 0x00)

TIM1 Capture/compare mode register 3 reset value.

Definition at line 2848 of file STM8AF_STM8S.h.

◆ _TIM1_CCMR4

#define _TIM1_CCMR4 _SFR(uint8_t, TIM1_AddressBase+0x0B)

TIM1 Capture/compare mode register 4.

Definition at line 2815 of file STM8AF_STM8S.h.

◆ _TIM1_CCMR4_RESET_VALUE

#define _TIM1_CCMR4_RESET_VALUE ((uint8_t) 0x00)

TIM1 Capture/compare mode register 4 reset value.

Definition at line 2849 of file STM8AF_STM8S.h.

◆ _TIM1_CCPC

#define _TIM1_CCPC ((uint8_t) (0x01 << 0))

TIM1 Capture/compare preloaded control [0] (in _TIM1_CR2)

Definition at line 2883 of file STM8AF_STM8S.h.

◆ _TIM1_CCR1H

#define _TIM1_CCR1H _SFR(uint8_t, TIM1_AddressBase+0x15)

TIM1 16-bit capture/compare value 1 high byte.

Definition at line 2825 of file STM8AF_STM8S.h.

◆ _TIM1_CCR1H_RESET_VALUE

#define _TIM1_CCR1H_RESET_VALUE ((uint8_t) 0x00)

TIM1 16-bit capture/compare value 1 high byte reset value.

Definition at line 2859 of file STM8AF_STM8S.h.

◆ _TIM1_CCR1L

#define _TIM1_CCR1L _SFR(uint8_t, TIM1_AddressBase+0x16)

TIM1 16-bit capture/compare value 1 low byte.

Definition at line 2826 of file STM8AF_STM8S.h.

◆ _TIM1_CCR1L_RESET_VALUE

#define _TIM1_CCR1L_RESET_VALUE ((uint8_t) 0x00)

TIM1 16-bit capture/compare value 1 low byte reset value.

Definition at line 2860 of file STM8AF_STM8S.h.

◆ _TIM1_CCR2H

#define _TIM1_CCR2H _SFR(uint8_t, TIM1_AddressBase+0x17)

TIM1 16-bit capture/compare value 2 high byte.

Definition at line 2827 of file STM8AF_STM8S.h.

◆ _TIM1_CCR2H_RESET_VALUE

#define _TIM1_CCR2H_RESET_VALUE ((uint8_t) 0x00)

TIM1 16-bit capture/compare value 2 high byte reset value.

Definition at line 2861 of file STM8AF_STM8S.h.

◆ _TIM1_CCR2L

#define _TIM1_CCR2L _SFR(uint8_t, TIM1_AddressBase+0x18)

TIM1 16-bit capture/compare value 2 low byte.

Definition at line 2828 of file STM8AF_STM8S.h.

◆ _TIM1_CCR2L_RESET_VALUE

#define _TIM1_CCR2L_RESET_VALUE ((uint8_t) 0x00)

TIM1 16-bit capture/compare value 2 low byte reset value.

Definition at line 2862 of file STM8AF_STM8S.h.

◆ _TIM1_CCR3H

#define _TIM1_CCR3H _SFR(uint8_t, TIM1_AddressBase+0x19)

TIM1 16-bit capture/compare value 3 high byte.

Definition at line 2829 of file STM8AF_STM8S.h.

◆ _TIM1_CCR3H_RESET_VALUE

#define _TIM1_CCR3H_RESET_VALUE ((uint8_t) 0x00)

TIM1 16-bit capture/compare value 3 high byte reset value.

Definition at line 2863 of file STM8AF_STM8S.h.

◆ _TIM1_CCR3L

#define _TIM1_CCR3L _SFR(uint8_t, TIM1_AddressBase+0x1A)

TIM1 16-bit capture/compare value 3 low byte.

Definition at line 2830 of file STM8AF_STM8S.h.

◆ _TIM1_CCR3L_RESET_VALUE

#define _TIM1_CCR3L_RESET_VALUE ((uint8_t) 0x00)

TIM1 16-bit capture/compare value 3 low byte reset value.

Definition at line 2864 of file STM8AF_STM8S.h.

◆ _TIM1_CCR4H

#define _TIM1_CCR4H _SFR(uint8_t, TIM1_AddressBase+0x1B)

TIM1 16-bit capture/compare value 4 high byte.

Definition at line 2831 of file STM8AF_STM8S.h.

◆ _TIM1_CCR4H_RESET_VALUE

#define _TIM1_CCR4H_RESET_VALUE ((uint8_t) 0x00)

TIM1 16-bit capture/compare value 4 high byte reset value.

Definition at line 2865 of file STM8AF_STM8S.h.

◆ _TIM1_CCR4L

#define _TIM1_CCR4L _SFR(uint8_t, TIM1_AddressBase+0x1C)

TIM1 16-bit capture/compare value 4 low byte.

Definition at line 2832 of file STM8AF_STM8S.h.

◆ _TIM1_CCR4L_RESET_VALUE

#define _TIM1_CCR4L_RESET_VALUE ((uint8_t) 0x00)

TIM1 16-bit capture/compare value 4 low byte reset value.

Definition at line 2866 of file STM8AF_STM8S.h.

◆ _TIM1_CEN

#define _TIM1_CEN ((uint8_t) (0x01 << 0))

TIM1 Counter enable [0] (in _TIM1_CR1)

Definition at line 2872 of file STM8AF_STM8S.h.

◆ _TIM1_CMS

#define _TIM1_CMS ((uint8_t) (0x03 << 5))

TIM1 Center-aligned mode selection [1:0] (in _TIM1_CR1)

Definition at line 2877 of file STM8AF_STM8S.h.

◆ _TIM1_CMS0

#define _TIM1_CMS0 ((uint8_t) (0x01 << 5))

TIM1 Center-aligned mode selection [0] (in _TIM1_CR1)

Definition at line 2878 of file STM8AF_STM8S.h.

◆ _TIM1_CMS1

#define _TIM1_CMS1 ((uint8_t) (0x01 << 6))

TIM1 Center-aligned mode selection [1] (in _TIM1_CR1)

Definition at line 2879 of file STM8AF_STM8S.h.

◆ _TIM1_CNTRH

#define _TIM1_CNTRH _SFR(uint8_t, TIM1_AddressBase+0x0E)

TIM1 counter register high byte.

Definition at line 2818 of file STM8AF_STM8S.h.

◆ _TIM1_CNTRH_RESET_VALUE

#define _TIM1_CNTRH_RESET_VALUE ((uint8_t) 0x00)

TIM1 counter register high byte reset value.

Definition at line 2852 of file STM8AF_STM8S.h.

◆ _TIM1_CNTRL

#define _TIM1_CNTRL _SFR(uint8_t, TIM1_AddressBase+0x0F)

TIM1 counter register low byte.

Definition at line 2819 of file STM8AF_STM8S.h.

◆ _TIM1_CNTRL_RESET_VALUE

#define _TIM1_CNTRL_RESET_VALUE ((uint8_t) 0x00)

TIM1 counter register low byte reset value.

Definition at line 2853 of file STM8AF_STM8S.h.

◆ _TIM1_COMG

#define _TIM1_COMG ((uint8_t) (0x01 << 5))

TIM1 Capture/compare control update generation [0] (in _TIM1_EGR)

Definition at line 2951 of file STM8AF_STM8S.h.

◆ _TIM1_COMIE

#define _TIM1_COMIE ((uint8_t) (0x01 << 5))

TIM1 Commutation interrupt enable [0] (in _TIM1_IER)

Definition at line 2923 of file STM8AF_STM8S.h.

◆ _TIM1_COMIF

#define _TIM1_COMIF ((uint8_t) (0x01 << 5))

TIM1 Commutation interrupt flag [0] (in _TIM1_SR1)

Definition at line 2933 of file STM8AF_STM8S.h.

◆ _TIM1_COMS

#define _TIM1_COMS ((uint8_t) (0x01 << 2))

TIM1 Capture/compare control update selection [0] (in _TIM1_CR2)

Definition at line 2885 of file STM8AF_STM8S.h.

◆ _TIM1_CR1

#define _TIM1_CR1 _SFR(uint8_t, TIM1_AddressBase+0x00)

TIM1 control register 1.

Definition at line 2804 of file STM8AF_STM8S.h.

◆ _TIM1_CR1_RESET_VALUE

#define _TIM1_CR1_RESET_VALUE ((uint8_t) 0x00)

TIM1 control register 1 reset value.

Definition at line 2838 of file STM8AF_STM8S.h.

◆ _TIM1_CR2

#define _TIM1_CR2 _SFR(uint8_t, TIM1_AddressBase+0x01)

TIM1 control register 2.

Definition at line 2805 of file STM8AF_STM8S.h.

◆ _TIM1_CR2_RESET_VALUE

#define _TIM1_CR2_RESET_VALUE ((uint8_t) 0x00)

TIM1 control register 2 reset value.

Definition at line 2839 of file STM8AF_STM8S.h.

◆ _TIM1_DIR

#define _TIM1_DIR ((uint8_t) (0x01 << 4))

TIM1 Direction [0] (in _TIM1_CR1)

Definition at line 2876 of file STM8AF_STM8S.h.

◆ _TIM1_DTR

#define _TIM1_DTR _SFR(uint8_t, TIM1_AddressBase+0x1E)

TIM1 Dead-time register.

Definition at line 2834 of file STM8AF_STM8S.h.

◆ _TIM1_DTR_RESET_VALUE

#define _TIM1_DTR_RESET_VALUE ((uint8_t) 0x00)

TIM1 Dead-time register reset value.

Definition at line 2868 of file STM8AF_STM8S.h.

◆ _TIM1_ECE

#define _TIM1_ECE ((uint8_t) (0x01 << 6))

TIM1 External clock enable [0] (in _TIM1_ETR)

Definition at line 2914 of file STM8AF_STM8S.h.

◆ _TIM1_EGR

#define _TIM1_EGR _SFR(uint8_t, TIM1_AddressBase+0x07)

TIM1 Event generation register.

Definition at line 2811 of file STM8AF_STM8S.h.

◆ _TIM1_EGR_RESET_VALUE

#define _TIM1_EGR_RESET_VALUE ((uint8_t) 0x00)

TIM1 Event generation register reset value.

Definition at line 2845 of file STM8AF_STM8S.h.

◆ _TIM1_ETF

#define _TIM1_ETF ((uint8_t) (0x0F << 0))

TIM1 External trigger filter [3:0] (in _TIM1_ETR)

Definition at line 2906 of file STM8AF_STM8S.h.

◆ _TIM1_ETF0

#define _TIM1_ETF0 ((uint8_t) (0x01 << 0))

TIM1 External trigger filter [0] (in _TIM1_ETR)

Definition at line 2907 of file STM8AF_STM8S.h.

◆ _TIM1_ETF1

#define _TIM1_ETF1 ((uint8_t) (0x01 << 1))

TIM1 External trigger filter [1] (in _TIM1_ETR)

Definition at line 2908 of file STM8AF_STM8S.h.

◆ _TIM1_ETF2

#define _TIM1_ETF2 ((uint8_t) (0x01 << 2))

TIM1 External trigger filter [2] (in _TIM1_ETR)

Definition at line 2909 of file STM8AF_STM8S.h.

◆ _TIM1_ETF3

#define _TIM1_ETF3 ((uint8_t) (0x01 << 3))

TIM1 External trigger filter [3] (in _TIM1_ETR)

Definition at line 2910 of file STM8AF_STM8S.h.

◆ _TIM1_ETP

#define _TIM1_ETP ((uint8_t) (0x01 << 7))

TIM1 External trigger polarity [0] (in _TIM1_ETR)

Definition at line 2915 of file STM8AF_STM8S.h.

◆ _TIM1_ETPS

#define _TIM1_ETPS ((uint8_t) (0x03 << 4))

TIM1 External trigger prescaler [1:0] (in _TIM1_ETR)

Definition at line 2911 of file STM8AF_STM8S.h.

◆ _TIM1_ETPS0

#define _TIM1_ETPS0 ((uint8_t) (0x01 << 4))

TIM1 External trigger prescaler [0] (in _TIM1_ETR)

Definition at line 2912 of file STM8AF_STM8S.h.

◆ _TIM1_ETPS1

#define _TIM1_ETPS1 ((uint8_t) (0x01 << 5))

TIM1 External trigger prescaler [1] (in _TIM1_ETR)

Definition at line 2913 of file STM8AF_STM8S.h.

◆ _TIM1_ETR

#define _TIM1_ETR _SFR(uint8_t, TIM1_AddressBase+0x03)

TIM1 External trigger register.

Definition at line 2807 of file STM8AF_STM8S.h.

◆ _TIM1_ETR_RESET_VALUE

#define _TIM1_ETR_RESET_VALUE ((uint8_t) 0x00)

TIM1 External trigger register reset value.

Definition at line 2841 of file STM8AF_STM8S.h.

◆ _TIM1_IC1F

#define _TIM1_IC1F ((uint8_t) (0x0F << 4))

TIM1 Output compare 1 mode [3:0] (in _TIM1_CCMR1)

Definition at line 2972 of file STM8AF_STM8S.h.

◆ _TIM1_IC1F0

#define _TIM1_IC1F0 ((uint8_t) (0x01 << 4))

TIM1 Input capture 1 filter [0] (in _TIM1_CCMR1)

Definition at line 2973 of file STM8AF_STM8S.h.

◆ _TIM1_IC1F1

#define _TIM1_IC1F1 ((uint8_t) (0x01 << 5))

TIM1 Input capture 1 filter [1] (in _TIM1_CCMR1)

Definition at line 2974 of file STM8AF_STM8S.h.

◆ _TIM1_IC1F2

#define _TIM1_IC1F2 ((uint8_t) (0x01 << 6))

TIM1 Input capture 1 filter [2] (in _TIM1_CCMR1)

Definition at line 2975 of file STM8AF_STM8S.h.

◆ _TIM1_IC1F3

#define _TIM1_IC1F3 ((uint8_t) (0x01 << 7))

TIM1 Input capture 1 filter [3] (in _TIM1_CCMR1)

Definition at line 2976 of file STM8AF_STM8S.h.

◆ _TIM1_IC1PSC

#define _TIM1_IC1PSC ((uint8_t) (0x03 << 2))

TIM1 Input capture 1 prescaler [1:0] (in _TIM1_CCMR1)

Definition at line 2969 of file STM8AF_STM8S.h.

◆ _TIM1_IC1PSC0

#define _TIM1_IC1PSC0 ((uint8_t) (0x01 << 2))

TIM1 Input capture 1 prescaler [0] (in _TIM1_CCMR1)

Definition at line 2970 of file STM8AF_STM8S.h.

◆ _TIM1_IC1PSC1

#define _TIM1_IC1PSC1 ((uint8_t) (0x01 << 3))

TIM1 Input capture 1 prescaler [1] (in _TIM1_CCMR1)

Definition at line 2971 of file STM8AF_STM8S.h.

◆ _TIM1_IC2F

#define _TIM1_IC2F ((uint8_t) (0x0F << 4))

TIM1 Output compare 2 mode [3:0] (in _TIM1_CCMR2)

Definition at line 2995 of file STM8AF_STM8S.h.

◆ _TIM1_IC2F0

#define _TIM1_IC2F0 ((uint8_t) (0x01 << 4))

TIM1 Input capture 2 filter [0] (in _TIM1_CCMR2)

Definition at line 2996 of file STM8AF_STM8S.h.

◆ _TIM1_IC2F1

#define _TIM1_IC2F1 ((uint8_t) (0x01 << 5))

TIM1 Input capture 2 filter [1] (in _TIM1_CCMR2)

Definition at line 2997 of file STM8AF_STM8S.h.

◆ _TIM1_IC2F2

#define _TIM1_IC2F2 ((uint8_t) (0x01 << 6))

TIM1 Input capture 2 filter [2] (in _TIM1_CCMR2)

Definition at line 2998 of file STM8AF_STM8S.h.

◆ _TIM1_IC2F3

#define _TIM1_IC2F3 ((uint8_t) (0x01 << 7))

TIM1 Input capture 2 filter [3] (in _TIM1_CCMR2)

Definition at line 2999 of file STM8AF_STM8S.h.

◆ _TIM1_IC2PSC

#define _TIM1_IC2PSC ((uint8_t) (0x03 << 2))

TIM1 Input capture 2 prescaler [1:0] (in _TIM1_CCMR2)

Definition at line 2992 of file STM8AF_STM8S.h.

◆ _TIM1_IC2PSC0

#define _TIM1_IC2PSC0 ((uint8_t) (0x01 << 2))

TIM1 Input capture 2 prescaler [0] (in _TIM1_CCMR2)

Definition at line 2993 of file STM8AF_STM8S.h.

◆ _TIM1_IC2PSC1

#define _TIM1_IC2PSC1 ((uint8_t) (0x01 << 3))

TIM1 Input capture 2 prescaler [1] (in _TIM1_CCMR2)

Definition at line 2994 of file STM8AF_STM8S.h.

◆ _TIM1_IC3F

#define _TIM1_IC3F ((uint8_t) (0x0F << 4))

TIM1 Output compare 3 mode [3:0] (in _TIM1_CCMR3)

Definition at line 3018 of file STM8AF_STM8S.h.

◆ _TIM1_IC3F0

#define _TIM1_IC3F0 ((uint8_t) (0x01 << 4))

TIM1 Input capture 3 filter [0] (in _TIM1_CCMR3)

Definition at line 3019 of file STM8AF_STM8S.h.

◆ _TIM1_IC3F1

#define _TIM1_IC3F1 ((uint8_t) (0x01 << 5))

TIM1 Input capture 3 filter [1] (in _TIM1_CCMR3)

Definition at line 3020 of file STM8AF_STM8S.h.

◆ _TIM1_IC3F2

#define _TIM1_IC3F2 ((uint8_t) (0x01 << 6))

TIM1 Input capture 3 filter [2] (in _TIM1_CCMR3)

Definition at line 3021 of file STM8AF_STM8S.h.

◆ _TIM1_IC3F3

#define _TIM1_IC3F3 ((uint8_t) (0x01 << 7))

TIM1 Input capture 3 filter [3] (in _TIM1_CCMR3)

Definition at line 3022 of file STM8AF_STM8S.h.

◆ _TIM1_IC3PSC

#define _TIM1_IC3PSC ((uint8_t) (0x03 << 2))

TIM1 Input capture 3 prescaler [1:0] (in _TIM1_CCMR3)

Definition at line 3015 of file STM8AF_STM8S.h.

◆ _TIM1_IC3PSC0

#define _TIM1_IC3PSC0 ((uint8_t) (0x01 << 2))

TIM1 Input capture 3 prescaler [0] (in _TIM1_CCMR3)

Definition at line 3016 of file STM8AF_STM8S.h.

◆ _TIM1_IC3PSC1

#define _TIM1_IC3PSC1 ((uint8_t) (0x01 << 3))

TIM1 Input capture 3 prescaler [1] (in _TIM1_CCMR3)

Definition at line 3017 of file STM8AF_STM8S.h.

◆ _TIM1_IC4F

#define _TIM1_IC4F ((uint8_t) (0x0F << 4))

TIM1 Output compare 4 mode [3:0] (in _TIM1_CCMR4)

Definition at line 3041 of file STM8AF_STM8S.h.

◆ _TIM1_IC4F0

#define _TIM1_IC4F0 ((uint8_t) (0x01 << 4))

TIM1 Input capture 4 filter [0] (in _TIM1_CCMR4)

Definition at line 3042 of file STM8AF_STM8S.h.

◆ _TIM1_IC4F1

#define _TIM1_IC4F1 ((uint8_t) (0x01 << 5))

TIM1 Input capture 4 filter [1] (in _TIM1_CCMR4)

Definition at line 3043 of file STM8AF_STM8S.h.

◆ _TIM1_IC4F2

#define _TIM1_IC4F2 ((uint8_t) (0x01 << 6))

TIM1 Input capture 4 filter [2] (in _TIM1_CCMR4)

Definition at line 3044 of file STM8AF_STM8S.h.

◆ _TIM1_IC4F3

#define _TIM1_IC4F3 ((uint8_t) (0x01 << 7))

TIM1 Input capture 4 filter [3] (in _TIM1_CCMR4)

Definition at line 3045 of file STM8AF_STM8S.h.

◆ _TIM1_IC4PSC

#define _TIM1_IC4PSC ((uint8_t) (0x03 << 2))

TIM1 Input capture 4 prescaler [1:0] (in _TIM1_CCMR4)

Definition at line 3038 of file STM8AF_STM8S.h.

◆ _TIM1_IC4PSC0

#define _TIM1_IC4PSC0 ((uint8_t) (0x01 << 2))

TIM1 Input capture 4 prescaler [0] (in _TIM1_CCMR4)

Definition at line 3039 of file STM8AF_STM8S.h.

◆ _TIM1_IC4PSC1

#define _TIM1_IC4PSC1 ((uint8_t) (0x01 << 3))

TIM1 Input capture 4 prescaler [1] (in _TIM1_CCMR4)

Definition at line 3040 of file STM8AF_STM8S.h.

◆ _TIM1_IER

#define _TIM1_IER _SFR(uint8_t, TIM1_AddressBase+0x04)

TIM1 interrupt enable register.

Definition at line 2808 of file STM8AF_STM8S.h.

◆ _TIM1_IER_RESET_VALUE

#define _TIM1_IER_RESET_VALUE ((uint8_t) 0x00)

TIM1 interrupt enable register reset value.

Definition at line 2842 of file STM8AF_STM8S.h.

◆ _TIM1_LOCK

#define _TIM1_LOCK ((int8_t) (0x03 << 0))

TIM1 Lock configuration [1:0] (in _TIM1_BKR)

Definition at line 3067 of file STM8AF_STM8S.h.

◆ _TIM1_LOCK0

#define _TIM1_LOCK0 ((uint8_t) (0x01 << 0))

TIM1 Lock configuration [0] (in _TIM1_BKR)

Definition at line 3068 of file STM8AF_STM8S.h.

◆ _TIM1_LOCK1

#define _TIM1_LOCK1 ((uint8_t) (0x01 << 1))

TIM1 Lock configuration [1] (in _TIM1_BKR)

Definition at line 3069 of file STM8AF_STM8S.h.

◆ _TIM1_MMS

#define _TIM1_MMS ((uint8_t) (0x07 << 4))

TIM1 Master mode selection [2:0] (in _TIM1_CR2)

Definition at line 2887 of file STM8AF_STM8S.h.

◆ _TIM1_MMS0

#define _TIM1_MMS0 ((uint8_t) (0x01 << 4))

TIM1 Master mode selection [0] (in _TIM1_CR2)

Definition at line 2888 of file STM8AF_STM8S.h.

◆ _TIM1_MMS1

#define _TIM1_MMS1 ((uint8_t) (0x01 << 5))

TIM1 Master mode selection [1] (in _TIM1_CR2)

Definition at line 2889 of file STM8AF_STM8S.h.

◆ _TIM1_MMS2

#define _TIM1_MMS2 ((uint8_t) (0x01 << 6))

TIM1 Master mode selection [2] (in _TIM1_CR2)

Definition at line 2890 of file STM8AF_STM8S.h.

◆ _TIM1_MOE

#define _TIM1_MOE ((uint8_t) (0x01 << 7))

TIM1 Main output enable [0] (in _TIM1_BKR)

Definition at line 3075 of file STM8AF_STM8S.h.

◆ _TIM1_MSM

#define _TIM1_MSM ((uint8_t) (0x01 << 7))

TIM1 Master/slave mode [0] (in _TIM1_SMCR)

Definition at line 2903 of file STM8AF_STM8S.h.

◆ _TIM1_OC1CE

#define _TIM1_OC1CE ((uint8_t) (0x01 << 7))

TIM1 Output compare 1 clear enable [0] (in _TIM1_CCMR1)

Definition at line 2965 of file STM8AF_STM8S.h.

◆ _TIM1_OC1FE

#define _TIM1_OC1FE ((uint8_t) (0x01 << 2))

TIM1 Output compare 1 fast enable [0] (in _TIM1_CCMR1)

Definition at line 2959 of file STM8AF_STM8S.h.

◆ _TIM1_OC1M

#define _TIM1_OC1M ((uint8_t) (0x07 << 4))

TIM1 Output compare 1 mode [2:0] (in _TIM1_CCMR1)

Definition at line 2961 of file STM8AF_STM8S.h.

◆ _TIM1_OC1M0

#define _TIM1_OC1M0 ((uint8_t) (0x01 << 4))

TIM1 Output compare 1 mode [0] (in _TIM1_CCMR1)

Definition at line 2962 of file STM8AF_STM8S.h.

◆ _TIM1_OC1M1

#define _TIM1_OC1M1 ((uint8_t) (0x01 << 5))

TIM1 Output compare 1 mode [1] (in _TIM1_CCMR1)

Definition at line 2963 of file STM8AF_STM8S.h.

◆ _TIM1_OC1M2

#define _TIM1_OC1M2 ((uint8_t) (0x01 << 6))

TIM1 Output compare 1 mode [2] (in _TIM1_CCMR1)

Definition at line 2964 of file STM8AF_STM8S.h.

◆ _TIM1_OC1PE

#define _TIM1_OC1PE ((uint8_t) (0x01 << 3))

TIM1 Output compare 1 preload enable [0] (in _TIM1_CCMR1)

Definition at line 2960 of file STM8AF_STM8S.h.

◆ _TIM1_OC2CE

#define _TIM1_OC2CE ((uint8_t) (0x01 << 7))

TIM1 Output compare 2 clear enable [0] (in _TIM1_CCMR2)

Definition at line 2988 of file STM8AF_STM8S.h.

◆ _TIM1_OC2FE

#define _TIM1_OC2FE ((uint8_t) (0x01 << 2))

TIM1 Output compare 2 fast enable [0] (in _TIM1_CCMR2)

Definition at line 2982 of file STM8AF_STM8S.h.

◆ _TIM1_OC2M

#define _TIM1_OC2M ((uint8_t) (0x07 << 4))

TIM1 Output compare 2 mode [2:0] (in _TIM1_CCMR2)

Definition at line 2984 of file STM8AF_STM8S.h.

◆ _TIM1_OC2M0

#define _TIM1_OC2M0 ((uint8_t) (0x01 << 4))

TIM1 Output compare 2 mode [0] (in _TIM1_CCMR2)

Definition at line 2985 of file STM8AF_STM8S.h.

◆ _TIM1_OC2M1

#define _TIM1_OC2M1 ((uint8_t) (0x01 << 5))

TIM1 Output compare 2 mode [1] (in _TIM1_CCMR2)

Definition at line 2986 of file STM8AF_STM8S.h.

◆ _TIM1_OC2M2

#define _TIM1_OC2M2 ((uint8_t) (0x01 << 6))

TIM1 Output compare 2 mode [2] (in _TIM1_CCMR2)

Definition at line 2987 of file STM8AF_STM8S.h.

◆ _TIM1_OC2PE

#define _TIM1_OC2PE ((uint8_t) (0x01 << 3))

TIM1 Output compare 2 preload enable [0] (in _TIM1_CCMR2)

Definition at line 2983 of file STM8AF_STM8S.h.

◆ _TIM1_OC3CE

#define _TIM1_OC3CE ((uint8_t) (0x01 << 7))

TIM1 Output compare 3 clear enable [0] (in _TIM1_CCMR3)

Definition at line 3011 of file STM8AF_STM8S.h.

◆ _TIM1_OC3FE

#define _TIM1_OC3FE ((uint8_t) (0x01 << 2))

TIM1 Output compare 3 fast enable [0] (in _TIM1_CCMR3)

Definition at line 3005 of file STM8AF_STM8S.h.

◆ _TIM1_OC3M

#define _TIM1_OC3M ((uint8_t) (0x07 << 4))

TIM1 Output compare 3 mode [2:0] (in _TIM1_CCMR3)

Definition at line 3007 of file STM8AF_STM8S.h.

◆ _TIM1_OC3M0

#define _TIM1_OC3M0 ((uint8_t) (0x01 << 4))

TIM1 Output compare 3 mode [0] (in _TIM1_CCMR3)

Definition at line 3008 of file STM8AF_STM8S.h.

◆ _TIM1_OC3M1

#define _TIM1_OC3M1 ((uint8_t) (0x01 << 5))

TIM1 Output compare 3 mode [1] (in _TIM1_CCMR3)

Definition at line 3009 of file STM8AF_STM8S.h.

◆ _TIM1_OC3M2

#define _TIM1_OC3M2 ((uint8_t) (0x01 << 6))

TIM1 Output compare 3 mode [2] (in _TIM1_CCMR3)

Definition at line 3010 of file STM8AF_STM8S.h.

◆ _TIM1_OC3PE

#define _TIM1_OC3PE ((uint8_t) (0x01 << 3))

TIM1 Output compare 3 preload enable [0] (in _TIM1_CCMR3)

Definition at line 3006 of file STM8AF_STM8S.h.

◆ _TIM1_OC4CE

#define _TIM1_OC4CE ((uint8_t) (0x01 << 7))

TIM1 Output compare 4 clear enable [0] (in _TIM1_CCMR4)

Definition at line 3034 of file STM8AF_STM8S.h.

◆ _TIM1_OC4FE

#define _TIM1_OC4FE ((uint8_t) (0x01 << 2))

TIM1 Output compare 4 fast enable [0] (in _TIM1_CCMR4)

Definition at line 3028 of file STM8AF_STM8S.h.

◆ _TIM1_OC4M

#define _TIM1_OC4M ((uint8_t) (0x07 << 4))

TIM1 Output compare 4 mode [2:0] (in _TIM1_CCMR4)

Definition at line 3030 of file STM8AF_STM8S.h.

◆ _TIM1_OC4M0

#define _TIM1_OC4M0 ((uint8_t) (0x01 << 4))

TIM1 Output compare 4 mode [0] (in _TIM1_CCMR4)

Definition at line 3031 of file STM8AF_STM8S.h.

◆ _TIM1_OC4M1

#define _TIM1_OC4M1 ((uint8_t) (0x01 << 5))

TIM1 Output compare 4 mode [1] (in _TIM1_CCMR4)

Definition at line 3032 of file STM8AF_STM8S.h.

◆ _TIM1_OC4M2

#define _TIM1_OC4M2 ((uint8_t) (0x01 << 6))

TIM1 Output compare 4 mode [2] (in _TIM1_CCMR4)

Definition at line 3033 of file STM8AF_STM8S.h.

◆ _TIM1_OC4PE

#define _TIM1_OC4PE ((uint8_t) (0x01 << 3))

TIM1 Output compare 4 preload enable [0] (in _TIM1_CCMR4)

Definition at line 3029 of file STM8AF_STM8S.h.

◆ _TIM1_OIS1

#define _TIM1_OIS1 ((uint8_t) (0x01 << 0))

TIM1 Output idle state 1 (OC1 output) [0] (in _TIM1_OISR)

Definition at line 3078 of file STM8AF_STM8S.h.

◆ _TIM1_OIS1N

#define _TIM1_OIS1N ((uint8_t) (0x01 << 1))

TIM1 Output idle state 1 (OC1N output) [0] (in _TIM1_OISR)

Definition at line 3079 of file STM8AF_STM8S.h.

◆ _TIM1_OIS2

#define _TIM1_OIS2 ((uint8_t) (0x01 << 2))

TIM1 Output idle state 2 (OC2 output) [0] (in _TIM1_OISR)

Definition at line 3080 of file STM8AF_STM8S.h.

◆ _TIM1_OIS2N

#define _TIM1_OIS2N ((uint8_t) (0x01 << 3))

TIM1 Output idle state 2 (OC2N output) [0] (in _TIM1_OISR)

Definition at line 3081 of file STM8AF_STM8S.h.

◆ _TIM1_OIS3

#define _TIM1_OIS3 ((uint8_t) (0x01 << 4))

TIM1 Output idle state 3 (OC3 output) [0] (in _TIM1_OISR)

Definition at line 3082 of file STM8AF_STM8S.h.

◆ _TIM1_OIS3N

#define _TIM1_OIS3N ((uint8_t) (0x01 << 5))

TIM1 Output idle state 3 (OC3N output) [0] (in _TIM1_OISR)

Definition at line 3083 of file STM8AF_STM8S.h.

◆ _TIM1_OIS4

#define _TIM1_OIS4 ((uint8_t) (0x01 << 6))

TIM1 Output idle state 4 (OC4 output) [0] (in _TIM1_OISR)

Definition at line 3084 of file STM8AF_STM8S.h.

◆ _TIM1_OISR

#define _TIM1_OISR _SFR(uint8_t, TIM1_AddressBase+0x1F)

TIM1 Output idle state register.

Definition at line 2835 of file STM8AF_STM8S.h.

◆ _TIM1_OISR_RESET_VALUE

#define _TIM1_OISR_RESET_VALUE ((uint8_t) 0x00)

TIM1 Output idle state register reset value.

Definition at line 2869 of file STM8AF_STM8S.h.

◆ _TIM1_OPM

#define _TIM1_OPM ((uint8_t) (0x01 << 3))

TIM1 One-pulse mode [0] (in _TIM1_CR1)

Definition at line 2875 of file STM8AF_STM8S.h.

◆ _TIM1_OSSI

#define _TIM1_OSSI ((uint8_t) (0x01 << 2))

TIM1 Off state selection for idle mode [0] (in _TIM1_BKR)

Definition at line 3070 of file STM8AF_STM8S.h.

◆ _TIM1_OSSR

#define _TIM1_OSSR ((uint8_t) (0x01 << 3))

TIM1 Off state selection for Run mode [0] (in _TIM1_BKR)

Definition at line 3071 of file STM8AF_STM8S.h.

◆ _TIM1_PSCRH

#define _TIM1_PSCRH _SFR(uint8_t, TIM1_AddressBase+0x10)

TIM1 clock prescaler register high byte.

Definition at line 2820 of file STM8AF_STM8S.h.

◆ _TIM1_PSCRH_RESET_VALUE

#define _TIM1_PSCRH_RESET_VALUE ((uint8_t) 0x00)

TIM1 clock prescaler register high byte reset value.

Definition at line 2854 of file STM8AF_STM8S.h.

◆ _TIM1_PSCRL

#define _TIM1_PSCRL _SFR(uint8_t, TIM1_AddressBase+0x11)

TIM1 clock prescaler register low byte.

Definition at line 2821 of file STM8AF_STM8S.h.

◆ _TIM1_PSCRL_RESET_VALUE

#define _TIM1_PSCRL_RESET_VALUE ((uint8_t) 0x00)

TIM1 clock prescaler register low byte reset value.

Definition at line 2855 of file STM8AF_STM8S.h.

◆ _TIM1_RCR

#define _TIM1_RCR _SFR(uint8_t, TIM1_AddressBase+0x14)

TIM1 Repetition counter.

Definition at line 2824 of file STM8AF_STM8S.h.

◆ _TIM1_RCR_RESET_VALUE

#define _TIM1_RCR_RESET_VALUE ((uint8_t) 0x00)

TIM1 Repetition counter reset value.

Definition at line 2858 of file STM8AF_STM8S.h.

◆ _TIM1_SMCR

#define _TIM1_SMCR _SFR(uint8_t, TIM1_AddressBase+0x02)

TIM1 Slave mode control register.

Definition at line 2806 of file STM8AF_STM8S.h.

◆ _TIM1_SMCR_RESET_VALUE

#define _TIM1_SMCR_RESET_VALUE ((uint8_t) 0x00)

TIM1 Slave mode control register reset value.

Definition at line 2840 of file STM8AF_STM8S.h.

◆ _TIM1_SMS

#define _TIM1_SMS ((uint8_t) (0x07 << 0))

TIM1 Clock/trigger/slave mode selection [2:0] (in _TIM1_SMCR)

Definition at line 2894 of file STM8AF_STM8S.h.

◆ _TIM1_SMS0

#define _TIM1_SMS0 ((uint8_t) (0x01 << 0))

TIM1 Clock/trigger/slave mode selection [0] (in _TIM1_SMCR)

Definition at line 2895 of file STM8AF_STM8S.h.

◆ _TIM1_SMS1

#define _TIM1_SMS1 ((uint8_t) (0x01 << 1))

TIM1 Clock/trigger/slave mode selection [1] (in _TIM1_SMCR)

Definition at line 2896 of file STM8AF_STM8S.h.

◆ _TIM1_SMS2

#define _TIM1_SMS2 ((uint8_t) (0x01 << 2))

TIM1 Clock/trigger/slave mode selection [2] (in _TIM1_SMCR)

Definition at line 2897 of file STM8AF_STM8S.h.

◆ _TIM1_SR1

#define _TIM1_SR1 _SFR(uint8_t, TIM1_AddressBase+0x05)

TIM1 status register 1.

Definition at line 2809 of file STM8AF_STM8S.h.

◆ _TIM1_SR1_RESET_VALUE

#define _TIM1_SR1_RESET_VALUE ((uint8_t) 0x00)

TIM1 status register 1 reset value.

Definition at line 2843 of file STM8AF_STM8S.h.

◆ _TIM1_SR2

#define _TIM1_SR2 _SFR(uint8_t, TIM1_AddressBase+0x06)

TIM1 status register 2.

Definition at line 2810 of file STM8AF_STM8S.h.

◆ _TIM1_SR2_RESET_VALUE

#define _TIM1_SR2_RESET_VALUE ((uint8_t) 0x00)

TIM1 status register 2 reset value.

Definition at line 2844 of file STM8AF_STM8S.h.

◆ _TIM1_TG

#define _TIM1_TG ((uint8_t) (0x01 << 6))

TIM1 Trigger generation [0] (in _TIM1_EGR)

Definition at line 2952 of file STM8AF_STM8S.h.

◆ _TIM1_TIE

#define _TIM1_TIE ((uint8_t) (0x01 << 6))

TIM1 Trigger interrupt enable [0] (in _TIM1_IER)

Definition at line 2924 of file STM8AF_STM8S.h.

◆ _TIM1_TIF

#define _TIM1_TIF ((uint8_t) (0x01 << 6))

TIM1 Trigger interrupt flag [0] (in _TIM1_SR1)

Definition at line 2934 of file STM8AF_STM8S.h.

◆ _TIM1_TS

#define _TIM1_TS ((uint8_t) (0x07 << 4))

TIM1 Trigger selection [2:0] (in _TIM1_SMCR)

Definition at line 2899 of file STM8AF_STM8S.h.

◆ _TIM1_TS0

#define _TIM1_TS0 ((uint8_t) (0x01 << 4))

TIM1 Trigger selection [0] (in _TIM1_SMCR)

Definition at line 2900 of file STM8AF_STM8S.h.

◆ _TIM1_TS1

#define _TIM1_TS1 ((uint8_t) (0x01 << 5))

TIM1 Trigger selection [1] (in _TIM1_SMCR)

Definition at line 2901 of file STM8AF_STM8S.h.

◆ _TIM1_TS2

#define _TIM1_TS2 ((uint8_t) (0x01 << 6))

TIM1 Trigger selection [2] (in _TIM1_SMCR)

Definition at line 2902 of file STM8AF_STM8S.h.

◆ _TIM1_UDIS

#define _TIM1_UDIS ((uint8_t) (0x01 << 1))

TIM1 Update disable [0] (in _TIM1_CR1)

Definition at line 2873 of file STM8AF_STM8S.h.

◆ _TIM1_UG

#define _TIM1_UG ((uint8_t) (0x01 << 0))

TIM1 Update generation [0] (in _TIM1_EGR)

Definition at line 2946 of file STM8AF_STM8S.h.

◆ _TIM1_UIE

#define _TIM1_UIE ((uint8_t) (0x01 << 0))

TIM1 Update interrupt enable [0] (in _TIM1_IER)

Definition at line 2918 of file STM8AF_STM8S.h.

◆ _TIM1_UIF

#define _TIM1_UIF ((uint8_t) (0x01 << 0))

TIM1 Update interrupt flag [0] (in _TIM1_SR1)

Definition at line 2928 of file STM8AF_STM8S.h.

◆ _TIM1_URS

#define _TIM1_URS ((uint8_t) (0x01 << 2))

TIM1 Update request source [0] (in _TIM1_CR1)

Definition at line 2874 of file STM8AF_STM8S.h.

◆ _TIM2

#define _TIM2 _SFR(TIM2_t, TIM2_AddressBase)

TIM2 struct/bit access.

Definition at line 3310 of file STM8AF_STM8S.h.

◆ _TIM2_ARPE

#define _TIM2_ARPE ((uint8_t) (0x01 << 7))

TIM2 Auto-reload preload enable [0] (in _TIM2_CR1)

Definition at line 3386 of file STM8AF_STM8S.h.

◆ _TIM2_ARRH

#define _TIM2_ARRH _SFR(uint8_t, TIM2_AddressBase+0x0D)

TIM2 auto-reload register high byte.

Definition at line 3347 of file STM8AF_STM8S.h.

◆ _TIM2_ARRH_RESET_VALUE

#define _TIM2_ARRH_RESET_VALUE ((uint8_t) 0xFF)

TIM2 auto-reload register high byte reset value.

Definition at line 3371 of file STM8AF_STM8S.h.

◆ _TIM2_ARRL

#define _TIM2_ARRL _SFR(uint8_t, TIM2_AddressBase+0x0E)

TIM2 auto-reload register low byte.

Definition at line 3348 of file STM8AF_STM8S.h.

◆ _TIM2_ARRL_RESET_VALUE

#define _TIM2_ARRL_RESET_VALUE ((uint8_t) 0xFF)

TIM2 auto-reload register low byte reset value.

Definition at line 3372 of file STM8AF_STM8S.h.

◆ _TIM2_CC1E

#define _TIM2_CC1E ((uint8_t) (0x01 << 0))

TIM2 Capture/compare 1 output enable [0] (in _TIM2_CCER1)

Definition at line 3486 of file STM8AF_STM8S.h.

◆ _TIM2_CC1G

#define _TIM2_CC1G ((uint8_t) (0x01 << 1))

TIM2 Capture/compare 1 generation [0] (in _TIM2_EGR)

Definition at line 3411 of file STM8AF_STM8S.h.

◆ _TIM2_CC1IE

#define _TIM2_CC1IE ((uint8_t) (0x01 << 1))

TIM2 Capture/compare 1 interrupt enable [0] (in _TIM2_IER)

Definition at line 3390 of file STM8AF_STM8S.h.

◆ _TIM2_CC1IF

#define _TIM2_CC1IF ((uint8_t) (0x01 << 1))

TIM2 Capture/compare 1 interrupt flag [0] (in _TIM2_SR1)

Definition at line 3397 of file STM8AF_STM8S.h.

◆ _TIM2_CC1OF

#define _TIM2_CC1OF ((uint8_t) (0x01 << 1))

TIM2 Capture/compare 1 overcapture flag [0] (in _TIM2_SR2)

Definition at line 3404 of file STM8AF_STM8S.h.

◆ _TIM2_CC1P

#define _TIM2_CC1P ((uint8_t) (0x01 << 1))

TIM2 Capture/compare 1 output polarity [0] (in _TIM2_CCER1)

Definition at line 3487 of file STM8AF_STM8S.h.

◆ _TIM2_CC1S

#define _TIM2_CC1S ((uint8_t) (0x03 << 0))

TIM2 Compare 1 selection [1:0] (in _TIM2_CCMR1)

Definition at line 3417 of file STM8AF_STM8S.h.

◆ _TIM2_CC1S0

#define _TIM2_CC1S0 ((uint8_t) (0x01 << 0))

TIM2 Compare 1 selection [0] (in _TIM2_CCMR1)

Definition at line 3418 of file STM8AF_STM8S.h.

◆ _TIM2_CC1S1

#define _TIM2_CC1S1 ((uint8_t) (0x01 << 1))

TIM2 Compare 1 selection [1] (in _TIM2_CCMR1)

Definition at line 3419 of file STM8AF_STM8S.h.

◆ _TIM2_CC2E

#define _TIM2_CC2E ((uint8_t) (0x01 << 4))

TIM2 Capture/compare 2 output enable [0] (in _TIM2_CCER1)

Definition at line 3489 of file STM8AF_STM8S.h.

◆ _TIM2_CC2G

#define _TIM2_CC2G ((uint8_t) (0x01 << 2))

TIM2 Capture/compare 2 generation [0] (in _TIM2_EGR)

Definition at line 3412 of file STM8AF_STM8S.h.

◆ _TIM2_CC2IE

#define _TIM2_CC2IE ((uint8_t) (0x01 << 2))

TIM2 Capture/compare 2 interrupt enable [0] (in _TIM2_IER)

Definition at line 3391 of file STM8AF_STM8S.h.

◆ _TIM2_CC2IF

#define _TIM2_CC2IF ((uint8_t) (0x01 << 2))

TIM2 Capture/compare 2 interrupt flag [0] (in _TIM2_SR1)

Definition at line 3398 of file STM8AF_STM8S.h.

◆ _TIM2_CC2OF

#define _TIM2_CC2OF ((uint8_t) (0x01 << 2))

TIM2 Capture/compare 2 overcapture flag [0] (in _TIM2_SR2)

Definition at line 3405 of file STM8AF_STM8S.h.

◆ _TIM2_CC2P

#define _TIM2_CC2P ((uint8_t) (0x01 << 5))

TIM2 Capture/compare 2 output polarity [0] (in _TIM2_CCER1)

Definition at line 3490 of file STM8AF_STM8S.h.

◆ _TIM2_CC2S

#define _TIM2_CC2S ((uint8_t) (0x03 << 0))

TIM2 Compare 2 selection [1:0] (in _TIM2_CCMR2)

Definition at line 3440 of file STM8AF_STM8S.h.

◆ _TIM2_CC2S0

#define _TIM2_CC2S0 ((uint8_t) (0x01 << 0))

TIM2 Compare 2 selection [0] (in _TIM2_CCMR2)

Definition at line 3441 of file STM8AF_STM8S.h.

◆ _TIM2_CC2S1

#define _TIM2_CC2S1 ((uint8_t) (0x01 << 1))

TIM2 Compare 2 selection [1] (in _TIM2_CCMR2)

Definition at line 3442 of file STM8AF_STM8S.h.

◆ _TIM2_CC3E

#define _TIM2_CC3E ((uint8_t) (0x01 << 0))

TIM2 Capture/compare 3 output enable [0] (in _TIM2_CCER2)

Definition at line 3494 of file STM8AF_STM8S.h.

◆ _TIM2_CC3G

#define _TIM2_CC3G ((uint8_t) (0x01 << 3))

TIM2 Capture/compare 3 generation [0] (in _TIM2_EGR)

Definition at line 3413 of file STM8AF_STM8S.h.

◆ _TIM2_CC3IE

#define _TIM2_CC3IE ((uint8_t) (0x01 << 3))

TIM2 Capture/compare 3 interrupt enable [0] (in _TIM2_IER)

Definition at line 3392 of file STM8AF_STM8S.h.

◆ _TIM2_CC3IF

#define _TIM2_CC3IF ((uint8_t) (0x01 << 3))

TIM2 Capture/compare 3 interrupt flag [0] (in _TIM2_SR1)

Definition at line 3399 of file STM8AF_STM8S.h.

◆ _TIM2_CC3OF

#define _TIM2_CC3OF ((uint8_t) (0x01 << 3))

TIM2 Capture/compare 3 overcapture flag [0] (in _TIM2_SR2)

Definition at line 3406 of file STM8AF_STM8S.h.

◆ _TIM2_CC3P

#define _TIM2_CC3P ((uint8_t) (0x01 << 1))

TIM2 Capture/compare 3 output polarity [0] (in _TIM2_CCER2)

Definition at line 3495 of file STM8AF_STM8S.h.

◆ _TIM2_CC3S

#define _TIM2_CC3S ((uint8_t) (0x03 << 0))

TIM2 Compare 3 selection [1:0] (in _TIM2_CCMR3)

Definition at line 3463 of file STM8AF_STM8S.h.

◆ _TIM2_CC3S0

#define _TIM2_CC3S0 ((uint8_t) (0x01 << 0))

TIM2 Compare 3 selection [0] (in _TIM2_CCMR3)

Definition at line 3464 of file STM8AF_STM8S.h.

◆ _TIM2_CC3S1

#define _TIM2_CC3S1 ((uint8_t) (0x01 << 1))

TIM2 Compare 3 selection [1] (in _TIM2_CCMR3)

Definition at line 3465 of file STM8AF_STM8S.h.

◆ _TIM2_CCER1

#define _TIM2_CCER1 _SFR(uint8_t, TIM2_AddressBase+0x08)

TIM2 Capture/compare enable register 1.

Definition at line 3342 of file STM8AF_STM8S.h.

◆ _TIM2_CCER1_RESET_VALUE

#define _TIM2_CCER1_RESET_VALUE ((uint8_t) 0x00)

TIM2 Capture/compare enable register 1 reset value.

Definition at line 3366 of file STM8AF_STM8S.h.

◆ _TIM2_CCER2

#define _TIM2_CCER2 _SFR(uint8_t, TIM2_AddressBase+0x09)

TIM2 Capture/compare enable register 2.

Definition at line 3343 of file STM8AF_STM8S.h.

◆ _TIM2_CCER2_RESET_VALUE

#define _TIM2_CCER2_RESET_VALUE ((uint8_t) 0x00)

TIM2 Capture/compare enable register 2 reset value.

Definition at line 3367 of file STM8AF_STM8S.h.

◆ _TIM2_CCMR1

#define _TIM2_CCMR1 _SFR(uint8_t, TIM2_AddressBase+0x05)

TIM2 Capture/compare mode register 1.

Definition at line 3339 of file STM8AF_STM8S.h.

◆ _TIM2_CCMR1_RESET_VALUE

#define _TIM2_CCMR1_RESET_VALUE ((uint8_t) 0x00)

TIM2 Capture/compare mode register 1 reset value.

Definition at line 3363 of file STM8AF_STM8S.h.

◆ _TIM2_CCMR2

#define _TIM2_CCMR2 _SFR(uint8_t, TIM2_AddressBase+0x06)

TIM2 Capture/compare mode register 2.

Definition at line 3340 of file STM8AF_STM8S.h.

◆ _TIM2_CCMR2_RESET_VALUE

#define _TIM2_CCMR2_RESET_VALUE ((uint8_t) 0x00)

TIM2 Capture/compare mode register 2 reset value.

Definition at line 3364 of file STM8AF_STM8S.h.

◆ _TIM2_CCMR3

#define _TIM2_CCMR3 _SFR(uint8_t, TIM2_AddressBase+0x07)

TIM2 Capture/compare mode register 3.

Definition at line 3341 of file STM8AF_STM8S.h.

◆ _TIM2_CCMR3_RESET_VALUE

#define _TIM2_CCMR3_RESET_VALUE ((uint8_t) 0x00)

TIM2 Capture/compare mode register 3 reset value.

Definition at line 3365 of file STM8AF_STM8S.h.

◆ _TIM2_CCR1H

#define _TIM2_CCR1H _SFR(uint8_t, TIM2_AddressBase+0x0F)

TIM2 16-bit capture/compare value 1 high byte.

Definition at line 3349 of file STM8AF_STM8S.h.

◆ _TIM2_CCR1H_RESET_VALUE

#define _TIM2_CCR1H_RESET_VALUE ((uint8_t) 0x00)

TIM2 16-bit capture/compare value 1 high byte reset value.

Definition at line 3373 of file STM8AF_STM8S.h.

◆ _TIM2_CCR1L

#define _TIM2_CCR1L _SFR(uint8_t, TIM2_AddressBase+0x10)

TIM2 16-bit capture/compare value 1 low byte.

Definition at line 3350 of file STM8AF_STM8S.h.

◆ _TIM2_CCR1L_RESET_VALUE

#define _TIM2_CCR1L_RESET_VALUE ((uint8_t) 0x00)

TIM2 16-bit capture/compare value 1 low byte reset value.

Definition at line 3374 of file STM8AF_STM8S.h.

◆ _TIM2_CCR2H

#define _TIM2_CCR2H _SFR(uint8_t, TIM2_AddressBase+0x11)

TIM2 16-bit capture/compare value 2 high byte.

Definition at line 3351 of file STM8AF_STM8S.h.

◆ _TIM2_CCR2H_RESET_VALUE

#define _TIM2_CCR2H_RESET_VALUE ((uint8_t) 0x00)

TIM2 16-bit capture/compare value 2 high byte reset value.

Definition at line 3375 of file STM8AF_STM8S.h.

◆ _TIM2_CCR2L

#define _TIM2_CCR2L _SFR(uint8_t, TIM2_AddressBase+0x12)

TIM2 16-bit capture/compare value 2 low byte.

Definition at line 3352 of file STM8AF_STM8S.h.

◆ _TIM2_CCR2L_RESET_VALUE

#define _TIM2_CCR2L_RESET_VALUE ((uint8_t) 0x00)

TIM2 16-bit capture/compare value 2 low byte reset value.

Definition at line 3376 of file STM8AF_STM8S.h.

◆ _TIM2_CCR3H

#define _TIM2_CCR3H _SFR(uint8_t, TIM2_AddressBase+0x13)

TIM2 16-bit capture/compare value 3 high byte.

Definition at line 3353 of file STM8AF_STM8S.h.

◆ _TIM2_CCR3H_RESET_VALUE

#define _TIM2_CCR3H_RESET_VALUE ((uint8_t) 0x00)

TIM2 16-bit capture/compare value 3 high byte reset value.

Definition at line 3377 of file STM8AF_STM8S.h.

◆ _TIM2_CCR3L

#define _TIM2_CCR3L _SFR(uint8_t, TIM2_AddressBase+0x14)

TIM2 16-bit capture/compare value 3 low byte.

Definition at line 3354 of file STM8AF_STM8S.h.

◆ _TIM2_CCR3L_RESET_VALUE

#define _TIM2_CCR3L_RESET_VALUE ((uint8_t) 0x00)

TIM2 16-bit capture/compare value 3 low byte reset value.

Definition at line 3378 of file STM8AF_STM8S.h.

◆ _TIM2_CEN

#define _TIM2_CEN ((uint8_t) (0x01 << 0))

TIM2 Counter enable [0] (in _TIM2_CR1)

Definition at line 3381 of file STM8AF_STM8S.h.

◆ _TIM2_CNTRH

#define _TIM2_CNTRH _SFR(uint8_t, TIM2_AddressBase+0x0A)

TIM2 counter register high byte.

Definition at line 3344 of file STM8AF_STM8S.h.

◆ _TIM2_CNTRH_RESET_VALUE

#define _TIM2_CNTRH_RESET_VALUE ((uint8_t) 0x00)

TIM2 counter register high byte reset value.

Definition at line 3368 of file STM8AF_STM8S.h.

◆ _TIM2_CNTRL

#define _TIM2_CNTRL _SFR(uint8_t, TIM2_AddressBase+0x0B)

TIM2 counter register low byte.

Definition at line 3345 of file STM8AF_STM8S.h.

◆ _TIM2_CNTRL_RESET_VALUE

#define _TIM2_CNTRL_RESET_VALUE ((uint8_t) 0x00)

TIM2 counter register low byte reset value.

Definition at line 3369 of file STM8AF_STM8S.h.

◆ _TIM2_CR1

#define _TIM2_CR1 _SFR(uint8_t, TIM2_AddressBase+0x00)

TIM2 control register 1.

Definition at line 3311 of file STM8AF_STM8S.h.

◆ _TIM2_CR1_RESET_VALUE

#define _TIM2_CR1_RESET_VALUE ((uint8_t) 0x00)

TIM2 control register 1 reset value.

Definition at line 3358 of file STM8AF_STM8S.h.

◆ _TIM2_EGR

#define _TIM2_EGR _SFR(uint8_t, TIM2_AddressBase+0x04)

TIM2 Event generation register.

Definition at line 3338 of file STM8AF_STM8S.h.

◆ _TIM2_EGR_RESET_VALUE

#define _TIM2_EGR_RESET_VALUE ((uint8_t) 0x00)

TIM2 Event generation register reset value.

Definition at line 3362 of file STM8AF_STM8S.h.

◆ _TIM2_IC1F

#define _TIM2_IC1F ((uint8_t) (0x0F << 4))

TIM2 Output compare 1 mode [3:0] (in _TIM2_CCMR1)

Definition at line 3433 of file STM8AF_STM8S.h.

◆ _TIM2_IC1F0

#define _TIM2_IC1F0 ((uint8_t) (0x01 << 4))

TIM2 Output compare 1 mode [0] (in _TIM2_CCMR1)

Definition at line 3434 of file STM8AF_STM8S.h.

◆ _TIM2_IC1F1

#define _TIM2_IC1F1 ((uint8_t) (0x01 << 5))

TIM2 Output compare 1 mode [1] (in _TIM2_CCMR1)

Definition at line 3435 of file STM8AF_STM8S.h.

◆ _TIM2_IC1F2

#define _TIM2_IC1F2 ((uint8_t) (0x01 << 6))

TIM2 Output compare 1 mode [2] (in _TIM2_CCMR1)

Definition at line 3436 of file STM8AF_STM8S.h.

◆ _TIM2_IC1F3

#define _TIM2_IC1F3 ((uint8_t) (0x01 << 7))

TIM2 Output compare 1 mode [3] (in _TIM2_CCMR1)

Definition at line 3437 of file STM8AF_STM8S.h.

◆ _TIM2_IC1PSC

#define _TIM2_IC1PSC ((uint8_t) (0x03 << 2))

TIM2 Input capture 1 prescaler [1:0] (in _TIM2_CCMR1)

Definition at line 3430 of file STM8AF_STM8S.h.

◆ _TIM2_IC1PSC0

#define _TIM2_IC1PSC0 ((uint8_t) (0x01 << 2))

TIM2 Input capture 1 prescaler [0] (in _TIM2_CCMR1)

Definition at line 3431 of file STM8AF_STM8S.h.

◆ _TIM2_IC1PSC1

#define _TIM2_IC1PSC1 ((uint8_t) (0x01 << 3))

TIM2 Input capture 1 prescaler [1] (in _TIM2_CCMR1)

Definition at line 3432 of file STM8AF_STM8S.h.

◆ _TIM2_IC2F

#define _TIM2_IC2F ((uint8_t) (0x0F << 4))

TIM2 Output compare 2 mode [3:0] (in _TIM2_CCMR2)

Definition at line 3456 of file STM8AF_STM8S.h.

◆ _TIM2_IC2F0

#define _TIM2_IC2F0 ((uint8_t) (0x01 << 4))

TIM2 Output compare 2 mode [0] (in _TIM2_CCMR2)

Definition at line 3457 of file STM8AF_STM8S.h.

◆ _TIM2_IC2F1

#define _TIM2_IC2F1 ((uint8_t) (0x01 << 5))

TIM2 Output compare 2 mode [1] (in _TIM2_CCMR2)

Definition at line 3458 of file STM8AF_STM8S.h.

◆ _TIM2_IC2F2

#define _TIM2_IC2F2 ((uint8_t) (0x01 << 6))

TIM2 Output compare 2 mode [2] (in _TIM2_CCMR2)

Definition at line 3459 of file STM8AF_STM8S.h.

◆ _TIM2_IC2F3

#define _TIM2_IC2F3 ((uint8_t) (0x01 << 7))

TIM2 Output compare 2 mode [3] (in _TIM2_CCMR2)

Definition at line 3460 of file STM8AF_STM8S.h.

◆ _TIM2_IC2PSC

#define _TIM2_IC2PSC ((uint8_t) (0x03 << 2))

TIM2 Input capture 2 prescaler [1:0] (in _TIM2_CCMR2)

Definition at line 3453 of file STM8AF_STM8S.h.

◆ _TIM2_IC2PSC0

#define _TIM2_IC2PSC0 ((uint8_t) (0x01 << 2))

TIM2 Input capture 2 prescaler [0] (in _TIM2_CCMR2)

Definition at line 3454 of file STM8AF_STM8S.h.

◆ _TIM2_IC2PSC1

#define _TIM2_IC2PSC1 ((uint8_t) (0x01 << 3))

TIM2 Input capture 2 prescaler [1] (in _TIM2_CCMR2)

Definition at line 3455 of file STM8AF_STM8S.h.

◆ _TIM2_IC3F

#define _TIM2_IC3F ((uint8_t) (0x0F << 4))

TIM2 Output compare 3 mode [3:0] (in _TIM2_CCMR3)

Definition at line 3479 of file STM8AF_STM8S.h.

◆ _TIM2_IC3F0

#define _TIM2_IC3F0 ((uint8_t) (0x01 << 4))

TIM2 Output compare 3 mode [0] (in _TIM2_CCMR3)

Definition at line 3480 of file STM8AF_STM8S.h.

◆ _TIM2_IC3F1

#define _TIM2_IC3F1 ((uint8_t) (0x01 << 5))

TIM2 Output compare 3 mode [1] (in _TIM2_CCMR3)

Definition at line 3481 of file STM8AF_STM8S.h.

◆ _TIM2_IC3F2

#define _TIM2_IC3F2 ((uint8_t) (0x01 << 6))

TIM2 Output compare 3 mode [2] (in _TIM2_CCMR3)

Definition at line 3482 of file STM8AF_STM8S.h.

◆ _TIM2_IC3F3

#define _TIM2_IC3F3 ((uint8_t) (0x01 << 7))

TIM2 Output compare 3 mode [3] (in _TIM2_CCMR3)

Definition at line 3483 of file STM8AF_STM8S.h.

◆ _TIM2_IC3PSC

#define _TIM2_IC3PSC ((uint8_t) (0x03 << 2))

TIM2 Input capture 3 prescaler [1:0] (in _TIM2_CCMR3)

Definition at line 3476 of file STM8AF_STM8S.h.

◆ _TIM2_IC3PSC0

#define _TIM2_IC3PSC0 ((uint8_t) (0x01 << 2))

TIM2 Input capture 3 prescaler [0] (in _TIM2_CCMR3)

Definition at line 3477 of file STM8AF_STM8S.h.

◆ _TIM2_IC3PSC1

#define _TIM2_IC3PSC1 ((uint8_t) (0x01 << 3))

TIM2 Input capture 3 prescaler [1] (in _TIM2_CCMR3)

Definition at line 3478 of file STM8AF_STM8S.h.

◆ _TIM2_IER

#define _TIM2_IER _SFR(uint8_t, TIM2_AddressBase+0x01)

TIM2 interrupt enable register.

Definition at line 3335 of file STM8AF_STM8S.h.

◆ _TIM2_IER_RESET_VALUE

#define _TIM2_IER_RESET_VALUE ((uint8_t) 0x00)

TIM2 interrupt enable register reset value.

Definition at line 3359 of file STM8AF_STM8S.h.

◆ _TIM2_OC1M

#define _TIM2_OC1M ((uint8_t) (0x07 << 4))

TIM2 Output compare 1 mode [2:0] (in _TIM2_CCMR1)

Definition at line 3422 of file STM8AF_STM8S.h.

◆ _TIM2_OC1M0

#define _TIM2_OC1M0 ((uint8_t) (0x01 << 4))

TIM2 Output compare 1 mode [0] (in _TIM2_CCMR1)

Definition at line 3423 of file STM8AF_STM8S.h.

◆ _TIM2_OC1M1

#define _TIM2_OC1M1 ((uint8_t) (0x01 << 5))

TIM2 Output compare 1 mode [1] (in _TIM2_CCMR1)

Definition at line 3424 of file STM8AF_STM8S.h.

◆ _TIM2_OC1M2

#define _TIM2_OC1M2 ((uint8_t) (0x01 << 6))

TIM2 Output compare 1 mode [2] (in _TIM2_CCMR1)

Definition at line 3425 of file STM8AF_STM8S.h.

◆ _TIM2_OC1PE

#define _TIM2_OC1PE ((uint8_t) (0x01 << 3))

TIM2 Output compare 1 preload enable [0] (in _TIM2_CCMR1)

Definition at line 3421 of file STM8AF_STM8S.h.

◆ _TIM2_OC2M

#define _TIM2_OC2M ((uint8_t) (0x07 << 4))

TIM2 Output compare 2 mode [2:0] (in _TIM2_CCMR2)

Definition at line 3445 of file STM8AF_STM8S.h.

◆ _TIM2_OC2M0

#define _TIM2_OC2M0 ((uint8_t) (0x01 << 4))

TIM2 Output compare 2 mode [0] (in _TIM2_CCMR2)

Definition at line 3446 of file STM8AF_STM8S.h.

◆ _TIM2_OC2M1

#define _TIM2_OC2M1 ((uint8_t) (0x01 << 5))

TIM2 Output compare 2 mode [1] (in _TIM2_CCMR2)

Definition at line 3447 of file STM8AF_STM8S.h.

◆ _TIM2_OC2M2

#define _TIM2_OC2M2 ((uint8_t) (0x01 << 6))

TIM2 Output compare 2 mode [2] (in _TIM2_CCMR2)

Definition at line 3448 of file STM8AF_STM8S.h.

◆ _TIM2_OC2PE

#define _TIM2_OC2PE ((uint8_t) (0x01 << 3))

TIM2 Output compare 2 preload enable [0] (in _TIM2_CCMR2)

Definition at line 3444 of file STM8AF_STM8S.h.

◆ _TIM2_OC3M

#define _TIM2_OC3M ((uint8_t) (0x07 << 4))

TIM2 Output compare 3 mode [2:0] (in _TIM2_CCMR3)

Definition at line 3468 of file STM8AF_STM8S.h.

◆ _TIM2_OC3M0

#define _TIM2_OC3M0 ((uint8_t) (0x01 << 4))

TIM2 Output compare 3 mode [0] (in _TIM2_CCMR3)

Definition at line 3469 of file STM8AF_STM8S.h.

◆ _TIM2_OC3M1

#define _TIM2_OC3M1 ((uint8_t) (0x01 << 5))

TIM2 Output compare 3 mode [1] (in _TIM2_CCMR3)

Definition at line 3470 of file STM8AF_STM8S.h.

◆ _TIM2_OC3M2

#define _TIM2_OC3M2 ((uint8_t) (0x01 << 6))

TIM2 Output compare 3 mode [2] (in _TIM2_CCMR3)

Definition at line 3471 of file STM8AF_STM8S.h.

◆ _TIM2_OC3PE

#define _TIM2_OC3PE ((uint8_t) (0x01 << 3))

TIM2 Output compare 3 preload enable [0] (in _TIM2_CCMR3)

Definition at line 3467 of file STM8AF_STM8S.h.

◆ _TIM2_OPM

#define _TIM2_OPM ((uint8_t) (0x01 << 3))

TIM2 One-pulse mode [0] (in _TIM2_CR1)

Definition at line 3384 of file STM8AF_STM8S.h.

◆ _TIM2_PSC

#define _TIM2_PSC ((uint8_t) (0x0F << 0))

TIM2 prescaler [3:0] (in _TIM2_PSCR)

Definition at line 3499 of file STM8AF_STM8S.h.

◆ _TIM2_PSC0

#define _TIM2_PSC0 ((uint8_t) (0x01 << 0))

TIM2 prescaler [0] (in _TIM2_PSCR)

Definition at line 3500 of file STM8AF_STM8S.h.

◆ _TIM2_PSC1

#define _TIM2_PSC1 ((uint8_t) (0x01 << 1))

TIM2 prescaler [1] (in _TIM2_PSCR)

Definition at line 3501 of file STM8AF_STM8S.h.

◆ _TIM2_PSC2

#define _TIM2_PSC2 ((uint8_t) (0x01 << 2))

TIM2 prescaler [2] (in _TIM2_PSCR)

Definition at line 3502 of file STM8AF_STM8S.h.

◆ _TIM2_PSC3

#define _TIM2_PSC3 ((uint8_t) (0x01 << 3))

TIM2 prescaler [3] (in _TIM2_PSCR)

Definition at line 3503 of file STM8AF_STM8S.h.

◆ _TIM2_PSCR

#define _TIM2_PSCR _SFR(uint8_t, TIM2_AddressBase+0x0C)

TIM2 clock prescaler register.

Definition at line 3346 of file STM8AF_STM8S.h.

◆ _TIM2_PSCR_RESET_VALUE

#define _TIM2_PSCR_RESET_VALUE ((uint8_t) 0x00)

TIM2 clock prescaler register reset value.

Definition at line 3370 of file STM8AF_STM8S.h.

◆ _TIM2_SR1

#define _TIM2_SR1 _SFR(uint8_t, TIM2_AddressBase+0x02)

TIM2 status register 1.

Definition at line 3336 of file STM8AF_STM8S.h.

◆ _TIM2_SR1_RESET_VALUE

#define _TIM2_SR1_RESET_VALUE ((uint8_t) 0x00)

TIM2 status register 1 reset value.

Definition at line 3360 of file STM8AF_STM8S.h.

◆ _TIM2_SR2

#define _TIM2_SR2 _SFR(uint8_t, TIM2_AddressBase+0x03)

TIM2 status register 2.

Definition at line 3337 of file STM8AF_STM8S.h.

◆ _TIM2_SR2_RESET_VALUE

#define _TIM2_SR2_RESET_VALUE ((uint8_t) 0x00)

TIM2 status register 2 reset value.

Definition at line 3361 of file STM8AF_STM8S.h.

◆ _TIM2_UDIS

#define _TIM2_UDIS ((uint8_t) (0x01 << 1))

TIM2 Update disable [0] (in _TIM2_CR1)

Definition at line 3382 of file STM8AF_STM8S.h.

◆ _TIM2_UG

#define _TIM2_UG ((uint8_t) (0x01 << 0))

TIM2 Update generation [0] (in _TIM2_EGR)

Definition at line 3410 of file STM8AF_STM8S.h.

◆ _TIM2_UIE

#define _TIM2_UIE ((uint8_t) (0x01 << 0))

TIM2 Update interrupt enable [0] (in _TIM2_IER)

Definition at line 3389 of file STM8AF_STM8S.h.

◆ _TIM2_UIF

#define _TIM2_UIF ((uint8_t) (0x01 << 0))

TIM2 Update interrupt flag [0] (in _TIM2_SR1)

Definition at line 3396 of file STM8AF_STM8S.h.

◆ _TIM2_URS

#define _TIM2_URS ((uint8_t) (0x01 << 2))

TIM2 Update request source [0] (in _TIM2_CR1)

Definition at line 3383 of file STM8AF_STM8S.h.

◆ _TIM3

#define _TIM3 _SFR(TIM3_t, TIM3_AddressBase)

TIM3 struct/bit access.

Definition at line 3677 of file STM8AF_STM8S.h.

◆ _TIM3_ARPE

#define _TIM3_ARPE ((uint8_t) (0x01 << 7))

TIM3 Auto-reload preload enable [0] (in _TIM3_CR1)

Definition at line 3721 of file STM8AF_STM8S.h.

◆ _TIM3_ARRH

#define _TIM3_ARRH _SFR(uint8_t, TIM3_AddressBase+0x0D)

TIM3 auto-reload register high byte.

Definition at line 3689 of file STM8AF_STM8S.h.

◆ _TIM3_ARRH_RESET_VALUE

#define _TIM3_ARRH_RESET_VALUE ((uint8_t) 0xFF)

TIM3 auto-reload register high byte reset value.

Definition at line 3708 of file STM8AF_STM8S.h.

◆ _TIM3_ARRL

#define _TIM3_ARRL _SFR(uint8_t, TIM3_AddressBase+0x0E)

TIM3 auto-reload register low byte.

Definition at line 3690 of file STM8AF_STM8S.h.

◆ _TIM3_ARRL_RESET_VALUE

#define _TIM3_ARRL_RESET_VALUE ((uint8_t) 0xFF)

TIM3 auto-reload register low byte reset value.

Definition at line 3709 of file STM8AF_STM8S.h.

◆ _TIM3_CC1E

#define _TIM3_CC1E ((uint8_t) (0x01 << 0))

TIM3 Capture/compare 1 output enable [0] (in _TIM3_CCER1)

Definition at line 3794 of file STM8AF_STM8S.h.

◆ _TIM3_CC1G

#define _TIM3_CC1G ((uint8_t) (0x01 << 1))

TIM3 Capture/compare 1 generation [0] (in _TIM3_EGR)

Definition at line 3743 of file STM8AF_STM8S.h.

◆ _TIM3_CC1IE

#define _TIM3_CC1IE ((uint8_t) (0x01 << 1))

TIM3 Capture/compare 1 interrupt enable [0] (in _TIM3_IER)

Definition at line 3725 of file STM8AF_STM8S.h.

◆ _TIM3_CC1IF

#define _TIM3_CC1IF ((uint8_t) (0x01 << 1))

TIM3 Capture/compare 1 interrupt flag [0] (in _TIM3_SR1)

Definition at line 3731 of file STM8AF_STM8S.h.

◆ _TIM3_CC1OF

#define _TIM3_CC1OF ((uint8_t) (0x01 << 1))

TIM3 Capture/compare 1 overcapture flag [0] (in _TIM3_SR2)

Definition at line 3737 of file STM8AF_STM8S.h.

◆ _TIM3_CC1P

#define _TIM3_CC1P ((uint8_t) (0x01 << 1))

TIM3 Capture/compare 1 output polarity [0] (in _TIM3_CCER1)

Definition at line 3795 of file STM8AF_STM8S.h.

◆ _TIM3_CC1S

#define _TIM3_CC1S ((uint8_t) (0x03 << 0))

TIM3 Compare 1 selection [1:0] (in _TIM3_CCMR1)

Definition at line 3748 of file STM8AF_STM8S.h.

◆ _TIM3_CC1S0

#define _TIM3_CC1S0 ((uint8_t) (0x01 << 0))

TIM3 Compare 1 selection [0] (in _TIM3_CCMR1)

Definition at line 3749 of file STM8AF_STM8S.h.

◆ _TIM3_CC1S1

#define _TIM3_CC1S1 ((uint8_t) (0x01 << 1))

TIM3 Compare 1 selection [1] (in _TIM3_CCMR1)

Definition at line 3750 of file STM8AF_STM8S.h.

◆ _TIM3_CC2E

#define _TIM3_CC2E ((uint8_t) (0x01 << 4))

TIM3 Capture/compare 2 output enable [0] (in _TIM3_CCER1)

Definition at line 3797 of file STM8AF_STM8S.h.

◆ _TIM3_CC2G

#define _TIM3_CC2G ((uint8_t) (0x01 << 2))

TIM3 Capture/compare 2 generation [0] (in _TIM3_EGR)

Definition at line 3744 of file STM8AF_STM8S.h.

◆ _TIM3_CC2IE

#define _TIM3_CC2IE ((uint8_t) (0x01 << 2))

TIM3 Capture/compare 2 interrupt enable [0] (in _TIM3_IER)

Definition at line 3726 of file STM8AF_STM8S.h.

◆ _TIM3_CC2IF

#define _TIM3_CC2IF ((uint8_t) (0x01 << 2))

TIM3 Capture/compare 2 interrupt flag [0] (in _TIM3_SR1)

Definition at line 3732 of file STM8AF_STM8S.h.

◆ _TIM3_CC2OF

#define _TIM3_CC2OF ((uint8_t) (0x01 << 2))

TIM3 Capture/compare 2 overcapture flag [0] (in _TIM3_SR2)

Definition at line 3738 of file STM8AF_STM8S.h.

◆ _TIM3_CC2P

#define _TIM3_CC2P ((uint8_t) (0x01 << 5))

TIM3 Capture/compare 2 output polarity [0] (in _TIM3_CCER1)

Definition at line 3798 of file STM8AF_STM8S.h.

◆ _TIM3_CC2S

#define _TIM3_CC2S ((uint8_t) (0x03 << 0))

TIM3 Compare 2 selection [1:0] (in _TIM3_CCMR2)

Definition at line 3771 of file STM8AF_STM8S.h.

◆ _TIM3_CC2S0

#define _TIM3_CC2S0 ((uint8_t) (0x01 << 0))

TIM3 Compare 2 selection [0] (in _TIM3_CCMR2)

Definition at line 3772 of file STM8AF_STM8S.h.

◆ _TIM3_CC2S1

#define _TIM3_CC2S1 ((uint8_t) (0x01 << 1))

TIM3 Compare 2 selection [1] (in _TIM3_CCMR2)

Definition at line 3773 of file STM8AF_STM8S.h.

◆ _TIM3_CCER1

#define _TIM3_CCER1 _SFR(uint8_t, TIM3_AddressBase+0x08)

TIM3 Capture/compare enable register 1.

Definition at line 3685 of file STM8AF_STM8S.h.

◆ _TIM3_CCER1_RESET_VALUE

#define _TIM3_CCER1_RESET_VALUE ((uint8_t) 0x00)

TIM3 Capture/compare enable register 1 reset value.

Definition at line 3704 of file STM8AF_STM8S.h.

◆ _TIM3_CCMR1

#define _TIM3_CCMR1 _SFR(uint8_t, TIM3_AddressBase+0x05)

TIM3 Capture/compare mode register 1.

Definition at line 3683 of file STM8AF_STM8S.h.

◆ _TIM3_CCMR1_RESET_VALUE

#define _TIM3_CCMR1_RESET_VALUE ((uint8_t) 0x00)

TIM3 Capture/compare mode register 1 reset value.

Definition at line 3702 of file STM8AF_STM8S.h.

◆ _TIM3_CCMR2

#define _TIM3_CCMR2 _SFR(uint8_t, TIM3_AddressBase+0x06)

TIM3 Capture/compare mode register 2.

Definition at line 3684 of file STM8AF_STM8S.h.

◆ _TIM3_CCMR2_RESET_VALUE

#define _TIM3_CCMR2_RESET_VALUE ((uint8_t) 0x00)

TIM3 Capture/compare mode register 2 reset value.

Definition at line 3703 of file STM8AF_STM8S.h.

◆ _TIM3_CCR1H

#define _TIM3_CCR1H _SFR(uint8_t, TIM3_AddressBase+0x0F)

TIM3 16-bit capture/compare value 1 high byte.

Definition at line 3691 of file STM8AF_STM8S.h.

◆ _TIM3_CCR1H_RESET_VALUE

#define _TIM3_CCR1H_RESET_VALUE ((uint8_t) 0x00)

TIM3 16-bit capture/compare value 1 high byte reset value.

Definition at line 3710 of file STM8AF_STM8S.h.

◆ _TIM3_CCR1L

#define _TIM3_CCR1L _SFR(uint8_t, TIM3_AddressBase+0x10)

TIM3 16-bit capture/compare value 1 low byte.

Definition at line 3692 of file STM8AF_STM8S.h.

◆ _TIM3_CCR1L_RESET_VALUE

#define _TIM3_CCR1L_RESET_VALUE ((uint8_t) 0x00)

TIM3 16-bit capture/compare value 1 low byte reset value.

Definition at line 3711 of file STM8AF_STM8S.h.

◆ _TIM3_CCR2H

#define _TIM3_CCR2H _SFR(uint8_t, TIM3_AddressBase+0x11)

TIM3 16-bit capture/compare value 2 high byte.

Definition at line 3693 of file STM8AF_STM8S.h.

◆ _TIM3_CCR2H_RESET_VALUE

#define _TIM3_CCR2H_RESET_VALUE ((uint8_t) 0x00)

TIM3 16-bit capture/compare value 2 high byte reset value.

Definition at line 3712 of file STM8AF_STM8S.h.

◆ _TIM3_CCR2L

#define _TIM3_CCR2L _SFR(uint8_t, TIM3_AddressBase+0x12)

TIM3 16-bit capture/compare value 2 low byte.

Definition at line 3694 of file STM8AF_STM8S.h.

◆ _TIM3_CCR2L_RESET_VALUE

#define _TIM3_CCR2L_RESET_VALUE ((uint8_t) 0x00)

TIM3 16-bit capture/compare value 2 low byte reset value.

Definition at line 3713 of file STM8AF_STM8S.h.

◆ _TIM3_CEN

#define _TIM3_CEN ((uint8_t) (0x01 << 0))

TIM3 Counter enable [0] (in _TIM3_CR1)

Definition at line 3716 of file STM8AF_STM8S.h.

◆ _TIM3_CNTRH

#define _TIM3_CNTRH _SFR(uint8_t, TIM3_AddressBase+0x0A)

TIM3 counter register high byte.

Definition at line 3686 of file STM8AF_STM8S.h.

◆ _TIM3_CNTRH_RESET_VALUE

#define _TIM3_CNTRH_RESET_VALUE ((uint8_t) 0x00)

TIM3 counter register high byte reset value.

Definition at line 3705 of file STM8AF_STM8S.h.

◆ _TIM3_CNTRL

#define _TIM3_CNTRL _SFR(uint8_t, TIM3_AddressBase+0x0B)

TIM3 counter register low byte.

Definition at line 3687 of file STM8AF_STM8S.h.

◆ _TIM3_CNTRL_RESET_VALUE

#define _TIM3_CNTRL_RESET_VALUE ((uint8_t) 0x00)

TIM3 counter register low byte reset value.

Definition at line 3706 of file STM8AF_STM8S.h.

◆ _TIM3_CR1

#define _TIM3_CR1 _SFR(uint8_t, TIM3_AddressBase+0x00)

TIM3 control register 1.

Definition at line 3678 of file STM8AF_STM8S.h.

◆ _TIM3_CR1_RESET_VALUE

#define _TIM3_CR1_RESET_VALUE ((uint8_t) 0x00)

TIM3 control register 1 reset value.

Definition at line 3697 of file STM8AF_STM8S.h.

◆ _TIM3_EGR

#define _TIM3_EGR _SFR(uint8_t, TIM3_AddressBase+0x04)

TIM3 Event generation register.

Definition at line 3682 of file STM8AF_STM8S.h.

◆ _TIM3_EGR_RESET_VALUE

#define _TIM3_EGR_RESET_VALUE ((uint8_t) 0x00)

TIM3 Event generation register reset value.

Definition at line 3701 of file STM8AF_STM8S.h.

◆ _TIM3_IC1F

#define _TIM3_IC1F ((uint8_t) (0x0F << 4))

TIM3 Output compare 1 mode [3:0] (in _TIM3_CCMR1)

Definition at line 3764 of file STM8AF_STM8S.h.

◆ _TIM3_IC1F0

#define _TIM3_IC1F0 ((uint8_t) (0x01 << 4))

TIM3 Output compare 1 mode [0] (in _TIM3_CCMR1)

Definition at line 3765 of file STM8AF_STM8S.h.

◆ _TIM3_IC1F1

#define _TIM3_IC1F1 ((uint8_t) (0x01 << 5))

TIM3 Output compare 1 mode [1] (in _TIM3_CCMR1)

Definition at line 3766 of file STM8AF_STM8S.h.

◆ _TIM3_IC1F2

#define _TIM3_IC1F2 ((uint8_t) (0x01 << 6))

TIM3 Output compare 1 mode [2] (in _TIM3_CCMR1)

Definition at line 3767 of file STM8AF_STM8S.h.

◆ _TIM3_IC1F3

#define _TIM3_IC1F3 ((uint8_t) (0x01 << 7))

TIM3 Output compare 1 mode [3] (in _TIM3_CCMR1)

Definition at line 3768 of file STM8AF_STM8S.h.

◆ _TIM3_IC1PSC

#define _TIM3_IC1PSC ((uint8_t) (0x03 << 2))

TIM3 Input capture 1 prescaler [1:0] (in _TIM3_CCMR1)

Definition at line 3761 of file STM8AF_STM8S.h.

◆ _TIM3_IC1PSC0

#define _TIM3_IC1PSC0 ((uint8_t) (0x01 << 2))

TIM3 Input capture 1 prescaler [0] (in _TIM3_CCMR1)

Definition at line 3762 of file STM8AF_STM8S.h.

◆ _TIM3_IC1PSC1

#define _TIM3_IC1PSC1 ((uint8_t) (0x01 << 3))

TIM3 Input capture 1 prescaler [1] (in _TIM3_CCMR1)

Definition at line 3763 of file STM8AF_STM8S.h.

◆ _TIM3_IC2F

#define _TIM3_IC2F ((uint8_t) (0x0F << 4))

TIM3 Output compare 2 mode [3:0] (in _TIM3_CCMR2)

Definition at line 3787 of file STM8AF_STM8S.h.

◆ _TIM3_IC2F0

#define _TIM3_IC2F0 ((uint8_t) (0x01 << 4))

TIM3 Output compare 2 mode [0] (in _TIM3_CCMR2)

Definition at line 3788 of file STM8AF_STM8S.h.

◆ _TIM3_IC2F1

#define _TIM3_IC2F1 ((uint8_t) (0x01 << 5))

TIM3 Output compare 2 mode [1] (in _TIM3_CCMR2)

Definition at line 3789 of file STM8AF_STM8S.h.

◆ _TIM3_IC2F2

#define _TIM3_IC2F2 ((uint8_t) (0x01 << 6))

TIM3 Output compare 2 mode [2] (in _TIM3_CCMR2)

Definition at line 3790 of file STM8AF_STM8S.h.

◆ _TIM3_IC2F3

#define _TIM3_IC2F3 ((uint8_t) (0x01 << 7))

TIM3 Output compare 2 mode [3] (in _TIM3_CCMR2)

Definition at line 3791 of file STM8AF_STM8S.h.

◆ _TIM3_IC2PSC

#define _TIM3_IC2PSC ((uint8_t) (0x03 << 2))

TIM3 Input capture 2 prescaler [1:0] (in _TIM3_CCMR2)

Definition at line 3784 of file STM8AF_STM8S.h.

◆ _TIM3_IC2PSC0

#define _TIM3_IC2PSC0 ((uint8_t) (0x01 << 2))

TIM3 Input capture 2 prescaler [0] (in _TIM3_CCMR2)

Definition at line 3785 of file STM8AF_STM8S.h.

◆ _TIM3_IC2PSC1

#define _TIM3_IC2PSC1 ((uint8_t) (0x01 << 3))

TIM3 Input capture 2 prescaler [1] (in _TIM3_CCMR2)

Definition at line 3786 of file STM8AF_STM8S.h.

◆ _TIM3_IER

#define _TIM3_IER _SFR(uint8_t, TIM3_AddressBase+0x01)

TIM3 interrupt enable register.

Definition at line 3679 of file STM8AF_STM8S.h.

◆ _TIM3_IER_RESET_VALUE

#define _TIM3_IER_RESET_VALUE ((uint8_t) 0x00)

TIM3 interrupt enable register reset value.

Definition at line 3698 of file STM8AF_STM8S.h.

◆ _TIM3_OC1M

#define _TIM3_OC1M ((uint8_t) (0x07 << 4))

TIM3 Output compare 1 mode [2:0] (in _TIM3_CCMR1)

Definition at line 3753 of file STM8AF_STM8S.h.

◆ _TIM3_OC1M0

#define _TIM3_OC1M0 ((uint8_t) (0x01 << 4))

TIM3 Output compare 1 mode [0] (in _TIM3_CCMR1)

Definition at line 3754 of file STM8AF_STM8S.h.

◆ _TIM3_OC1M1

#define _TIM3_OC1M1 ((uint8_t) (0x01 << 5))

TIM3 Output compare 1 mode [1] (in _TIM3_CCMR1)

Definition at line 3755 of file STM8AF_STM8S.h.

◆ _TIM3_OC1M2

#define _TIM3_OC1M2 ((uint8_t) (0x01 << 6))

TIM3 Output compare 1 mode [2] (in _TIM3_CCMR1)

Definition at line 3756 of file STM8AF_STM8S.h.

◆ _TIM3_OC1PE

#define _TIM3_OC1PE ((uint8_t) (0x01 << 3))

TIM3 Output compare 1 preload enable [0] (in _TIM3_CCMR1)

Definition at line 3752 of file STM8AF_STM8S.h.

◆ _TIM3_OC2M

#define _TIM3_OC2M ((uint8_t) (0x07 << 4))

TIM3 Output compare 2 mode [2:0] (in _TIM3_CCMR2)

Definition at line 3776 of file STM8AF_STM8S.h.

◆ _TIM3_OC2M0

#define _TIM3_OC2M0 ((uint8_t) (0x01 << 4))

TIM3 Output compare 2 mode [0] (in _TIM3_CCMR2)

Definition at line 3777 of file STM8AF_STM8S.h.

◆ _TIM3_OC2M1

#define _TIM3_OC2M1 ((uint8_t) (0x01 << 5))

TIM3 Output compare 2 mode [1] (in _TIM3_CCMR2)

Definition at line 3778 of file STM8AF_STM8S.h.

◆ _TIM3_OC2M2

#define _TIM3_OC2M2 ((uint8_t) (0x01 << 6))

TIM3 Output compare 2 mode [2] (in _TIM3_CCMR2)

Definition at line 3779 of file STM8AF_STM8S.h.

◆ _TIM3_OC2PE

#define _TIM3_OC2PE ((uint8_t) (0x01 << 3))

TIM3 Output compare 2 preload enable [0] (in _TIM3_CCMR2)

Definition at line 3775 of file STM8AF_STM8S.h.

◆ _TIM3_OPM

#define _TIM3_OPM ((uint8_t) (0x01 << 3))

TIM3 One-pulse mode [0] (in _TIM3_CR1)

Definition at line 3719 of file STM8AF_STM8S.h.

◆ _TIM3_PSC

#define _TIM3_PSC ((uint8_t) (0x0F << 0))

TIM3 clock prescaler [3:0] (in _TIM3_PSCR)

Definition at line 3802 of file STM8AF_STM8S.h.

◆ _TIM3_PSC0

#define _TIM3_PSC0 ((uint8_t) (0x01 << 0))

TIM3 clock prescaler [0] (in _TIM3_PSCR)

Definition at line 3803 of file STM8AF_STM8S.h.

◆ _TIM3_PSC1

#define _TIM3_PSC1 ((uint8_t) (0x01 << 1))

TIM3 clock prescaler [1] (in _TIM3_PSCR)

Definition at line 3804 of file STM8AF_STM8S.h.

◆ _TIM3_PSC2

#define _TIM3_PSC2 ((uint8_t) (0x01 << 2))

TIM3 clock prescaler [2] (in _TIM3_PSCR)

Definition at line 3805 of file STM8AF_STM8S.h.

◆ _TIM3_PSC3

#define _TIM3_PSC3 ((uint8_t) (0x01 << 3))

TIM3 clock prescaler [3] (in _TIM3_PSCR)

Definition at line 3806 of file STM8AF_STM8S.h.

◆ _TIM3_PSCR

#define _TIM3_PSCR _SFR(uint8_t, TIM3_AddressBase+0x0C)

TIM3 clock prescaler register.

Definition at line 3688 of file STM8AF_STM8S.h.

◆ _TIM3_PSCR_RESET_VALUE

#define _TIM3_PSCR_RESET_VALUE ((uint8_t) 0x00)

TIM3 clock prescaler register reset value.

Definition at line 3707 of file STM8AF_STM8S.h.

◆ _TIM3_SR1

#define _TIM3_SR1 _SFR(uint8_t, TIM3_AddressBase+0x02)

TIM3 status register 1.

Definition at line 3680 of file STM8AF_STM8S.h.

◆ _TIM3_SR1_RESET_VALUE

#define _TIM3_SR1_RESET_VALUE ((uint8_t) 0x00)

TIM3 status register 1 reset value.

Definition at line 3699 of file STM8AF_STM8S.h.

◆ _TIM3_SR2

#define _TIM3_SR2 _SFR(uint8_t, TIM3_AddressBase+0x03)

TIM3 status register 2.

Definition at line 3681 of file STM8AF_STM8S.h.

◆ _TIM3_SR2_RESET_VALUE

#define _TIM3_SR2_RESET_VALUE ((uint8_t) 0x00)

TIM3 status register 2 reset value.

Definition at line 3700 of file STM8AF_STM8S.h.

◆ _TIM3_UDIS

#define _TIM3_UDIS ((uint8_t) (0x01 << 1))

TIM3 Update disable [0] (in _TIM3_CR1)

Definition at line 3717 of file STM8AF_STM8S.h.

◆ _TIM3_UG

#define _TIM3_UG ((uint8_t) (0x01 << 0))

TIM3 Update generation [0] (in _TIM3_EGR)

Definition at line 3742 of file STM8AF_STM8S.h.

◆ _TIM3_UIE

#define _TIM3_UIE ((uint8_t) (0x01 << 0))

TIM3 Update interrupt enable [0] (in _TIM3_IER)

Definition at line 3724 of file STM8AF_STM8S.h.

◆ _TIM3_UIF

#define _TIM3_UIF ((uint8_t) (0x01 << 0))

TIM3 Update interrupt flag [0] (in _TIM3_SR1)

Definition at line 3730 of file STM8AF_STM8S.h.

◆ _TIM3_URS

#define _TIM3_URS ((uint8_t) (0x01 << 2))

TIM3 Update request source [0] (in _TIM3_CR1)

Definition at line 3718 of file STM8AF_STM8S.h.

◆ _TIM4

#define _TIM4 _SFR(TIM4_t, TIM4_AddressBase)

TIM4 struct/bit access.

Definition at line 3879 of file STM8AF_STM8S.h.

◆ _TIM4_ARPE

#define _TIM4_ARPE ((uint8_t) (0x01 << 7))

TIM4 Auto-reload preload enable [0] (in _TIM4_CR)

Definition at line 3913 of file STM8AF_STM8S.h.

◆ _TIM4_ARR

#define _TIM4_ARR _SFR(uint8_t, TIM4_AddressBase+0x06)

TIM4 auto-reload register.

Definition at line 3895 of file STM8AF_STM8S.h.

◆ _TIM4_ARR_RESET_VALUE

#define _TIM4_ARR_RESET_VALUE ((uint8_t) 0xFF)

TIM4 auto-reload register reset value.

Definition at line 3905 of file STM8AF_STM8S.h.

◆ _TIM4_CEN

#define _TIM4_CEN ((uint8_t) (0x01 << 0))

TIM4 Counter enable [0] (in _TIM4_CR)

Definition at line 3908 of file STM8AF_STM8S.h.

◆ _TIM4_CNTR

#define _TIM4_CNTR _SFR(uint8_t, TIM4_AddressBase+0x04)

TIM4 counter register.

Definition at line 3893 of file STM8AF_STM8S.h.

◆ _TIM4_CNTR_RESET_VALUE

#define _TIM4_CNTR_RESET_VALUE ((uint8_t) 0x00)

TIM4 counter register reset value.

Definition at line 3903 of file STM8AF_STM8S.h.

◆ _TIM4_CR

#define _TIM4_CR _SFR(uint8_t, TIM4_AddressBase+0x00)

TIM4 control register.

Definition at line 3880 of file STM8AF_STM8S.h.

◆ _TIM4_CR_RESET_VALUE

#define _TIM4_CR_RESET_VALUE ((uint8_t) 0x00)

TIM4 control register reset value.

Definition at line 3899 of file STM8AF_STM8S.h.

◆ _TIM4_EGR

#define _TIM4_EGR _SFR(uint8_t, TIM4_AddressBase+0x03)

TIM4 event generation register.

Definition at line 3892 of file STM8AF_STM8S.h.

◆ _TIM4_EGR_RESET_VALUE

#define _TIM4_EGR_RESET_VALUE ((uint8_t) 0x00)

TIM4 event generation register reset value.

Definition at line 3902 of file STM8AF_STM8S.h.

◆ _TIM4_IER

#define _TIM4_IER _SFR(uint8_t, TIM4_AddressBase+0x01)

TIM4 interrupt enable register.

Definition at line 3890 of file STM8AF_STM8S.h.

◆ _TIM4_IER_RESET_VALUE

#define _TIM4_IER_RESET_VALUE ((uint8_t) 0x00)

TIM4 interrupt enable register reset value.

Definition at line 3900 of file STM8AF_STM8S.h.

◆ _TIM4_OPM

#define _TIM4_OPM ((uint8_t) (0x01 << 3))

TIM4 One-pulse mode [0] (in _TIM4_CR)

Definition at line 3911 of file STM8AF_STM8S.h.

◆ _TIM4_PSC

#define _TIM4_PSC ((uint8_t) (0x07 << 0))

TIM4 clock prescaler [2:0] (in _TIM4_PSCR)

Definition at line 3928 of file STM8AF_STM8S.h.

◆ _TIM4_PSC0

#define _TIM4_PSC0 ((uint8_t) (0x01 << 0))

TIM4 clock prescaler [0] (in _TIM4_PSCR)

Definition at line 3929 of file STM8AF_STM8S.h.

◆ _TIM4_PSC1

#define _TIM4_PSC1 ((uint8_t) (0x01 << 1))

TIM4 clock prescaler [1] (in _TIM4_PSCR)

Definition at line 3930 of file STM8AF_STM8S.h.

◆ _TIM4_PSC2

#define _TIM4_PSC2 ((uint8_t) (0x01 << 2))

TIM4 clock prescaler [2] (in _TIM4_PSCR)

Definition at line 3931 of file STM8AF_STM8S.h.

◆ _TIM4_PSCR

#define _TIM4_PSCR _SFR(uint8_t, TIM4_AddressBase+0x05)

TIM4 clock prescaler register.

Definition at line 3894 of file STM8AF_STM8S.h.

◆ _TIM4_PSCR_RESET_VALUE

#define _TIM4_PSCR_RESET_VALUE ((uint8_t) 0x00)

TIM4 clock prescaler register reset value.

Definition at line 3904 of file STM8AF_STM8S.h.

◆ _TIM4_SR

#define _TIM4_SR _SFR(uint8_t, TIM4_AddressBase+0x02)

TIM4 status register.

Definition at line 3891 of file STM8AF_STM8S.h.

◆ _TIM4_SR_RESET_VALUE

#define _TIM4_SR_RESET_VALUE ((uint8_t) 0x00)

TIM4 status register reset value.

Definition at line 3901 of file STM8AF_STM8S.h.

◆ _TIM4_UDIS

#define _TIM4_UDIS ((uint8_t) (0x01 << 1))

TIM4 Update disable [0] (in _TIM4_CR)

Definition at line 3909 of file STM8AF_STM8S.h.

◆ _TIM4_UG

#define _TIM4_UG ((uint8_t) (0x01 << 0))

TIM4 Update generation [0] (in _TIM4_EGR)

Definition at line 3924 of file STM8AF_STM8S.h.

◆ _TIM4_UIE

#define _TIM4_UIE ((uint8_t) (0x01 << 0))

TIM4 Update interrupt enable [0] (in _TIM4_IER)

Definition at line 3916 of file STM8AF_STM8S.h.

◆ _TIM4_UIF

#define _TIM4_UIF ((uint8_t) (0x01 << 0))

TIM4 Update interrupt flag [0] (in _TIM4_SR)

Definition at line 3920 of file STM8AF_STM8S.h.

◆ _TIM4_URS

#define _TIM4_URS ((uint8_t) (0x01 << 2))

TIM4 Update request source [0] (in _TIM4_CR)

Definition at line 3910 of file STM8AF_STM8S.h.

◆ _TIM5

#define _TIM5 _SFR(TIM5_t, TIM5_AddressBase)

TIM5 struct/bit access.

Definition at line 4177 of file STM8AF_STM8S.h.

◆ _TIM5_ARPE

#define _TIM5_ARPE ((uint8_t) (0x01 << 7))

TIM5 Auto-reload preload enable [0] (in _TIM5_CR1)

Definition at line 4233 of file STM8AF_STM8S.h.

◆ _TIM5_ARRH

#define _TIM5_ARRH _SFR(uint8_t, TIM5_AddressBase+0x0F)

TIM5 auto-reload register high byte.

Definition at line 4193 of file STM8AF_STM8S.h.

◆ _TIM5_ARRH_RESET_VALUE

#define _TIM5_ARRH_RESET_VALUE ((uint8_t) 0xFF)

TIM5 auto-reload register high byte reset value.

Definition at line 4218 of file STM8AF_STM8S.h.

◆ _TIM5_ARRL

#define _TIM5_ARRL _SFR(uint8_t, TIM5_AddressBase+0x10)

TIM5 auto-reload register low byte.

Definition at line 4194 of file STM8AF_STM8S.h.

◆ _TIM5_ARRL_RESET_VALUE

#define _TIM5_ARRL_RESET_VALUE ((uint8_t) 0xFF)

TIM5 auto-reload register low byte reset value.

Definition at line 4219 of file STM8AF_STM8S.h.

◆ _TIM5_CC1E

#define _TIM5_CC1E ((uint8_t) (0x01 << 0))

TIM5 Capture/compare 1 output enable [0] (in _TIM5_CCER1)

Definition at line 4362 of file STM8AF_STM8S.h.

◆ _TIM5_CC1G

#define _TIM5_CC1G ((uint8_t) (0x01 << 1))

TIM5 Capture/compare 1 generation [0] (in _TIM5_EGR)

Definition at line 4285 of file STM8AF_STM8S.h.

◆ _TIM5_CC1IE

#define _TIM5_CC1IE ((uint8_t) (0x01 << 1))

TIM5 Capture/compare 1 interrupt enable [0] (in _TIM5_IER)

Definition at line 4260 of file STM8AF_STM8S.h.

◆ _TIM5_CC1IF

#define _TIM5_CC1IF ((uint8_t) (0x01 << 1))

TIM5 Capture/compare 1 interrupt flag [0] (in _TIM5_SR1)

Definition at line 4269 of file STM8AF_STM8S.h.

◆ _TIM5_CC1OF

#define _TIM5_CC1OF ((uint8_t) (0x01 << 1))

TIM5 Capture/compare 1 overcapture flag [0] (in _TIM5_SR2)

Definition at line 4278 of file STM8AF_STM8S.h.

◆ _TIM5_CC1P

#define _TIM5_CC1P ((uint8_t) (0x01 << 1))

TIM5 Capture/compare 1 output polarity [0] (in _TIM5_CCER1)

Definition at line 4363 of file STM8AF_STM8S.h.

◆ _TIM5_CC1S

#define _TIM5_CC1S ((uint8_t) (0x03 << 0))

TIM5 Compare 1 selection [1:0] (in _TIM5_CCMR1)

Definition at line 4293 of file STM8AF_STM8S.h.

◆ _TIM5_CC1S0

#define _TIM5_CC1S0 ((uint8_t) (0x01 << 0))

TIM5 Compare 1 selection [0] (in _TIM5_CCMR1)

Definition at line 4294 of file STM8AF_STM8S.h.

◆ _TIM5_CC1S1

#define _TIM5_CC1S1 ((uint8_t) (0x01 << 1))

TIM5 Compare 1 selection [1] (in _TIM5_CCMR1)

Definition at line 4295 of file STM8AF_STM8S.h.

◆ _TIM5_CC2E

#define _TIM5_CC2E ((uint8_t) (0x01 << 4))

TIM5 Capture/compare 2 output enable [0] (in _TIM5_CCER1)

Definition at line 4365 of file STM8AF_STM8S.h.

◆ _TIM5_CC2G

#define _TIM5_CC2G ((uint8_t) (0x01 << 2))

TIM5 Capture/compare 2 generation [0] (in _TIM5_EGR)

Definition at line 4286 of file STM8AF_STM8S.h.

◆ _TIM5_CC2IE

#define _TIM5_CC2IE ((uint8_t) (0x01 << 2))

TIM5 Capture/compare 2 interrupt enable [0] (in _TIM5_IER)

Definition at line 4261 of file STM8AF_STM8S.h.

◆ _TIM5_CC2IF

#define _TIM5_CC2IF ((uint8_t) (0x01 << 2))

TIM5 Capture/compare 2 interrupt flag [0] (in _TIM5_SR1)

Definition at line 4270 of file STM8AF_STM8S.h.

◆ _TIM5_CC2OF

#define _TIM5_CC2OF ((uint8_t) (0x01 << 2))

TIM5 Capture/compare 2 overcapture flag [0] (in _TIM5_SR2)

Definition at line 4279 of file STM8AF_STM8S.h.

◆ _TIM5_CC2P

#define _TIM5_CC2P ((uint8_t) (0x01 << 5))

TIM5 Capture/compare 2 output polarity [0] (in _TIM5_CCER1)

Definition at line 4366 of file STM8AF_STM8S.h.

◆ _TIM5_CC2S

#define _TIM5_CC2S ((uint8_t) (0x03 << 0))

TIM5 Compare 2 selection [1:0] (in _TIM5_CCMR2)

Definition at line 4316 of file STM8AF_STM8S.h.

◆ _TIM5_CC2S0

#define _TIM5_CC2S0 ((uint8_t) (0x01 << 0))

TIM5 Compare 2 selection [0] (in _TIM5_CCMR2)

Definition at line 4317 of file STM8AF_STM8S.h.

◆ _TIM5_CC2S1

#define _TIM5_CC2S1 ((uint8_t) (0x01 << 1))

TIM5 Compare 2 selection [1] (in _TIM5_CCMR2)

Definition at line 4318 of file STM8AF_STM8S.h.

◆ _TIM5_CC3E

#define _TIM5_CC3E ((uint8_t) (0x01 << 0))

TIM5 Capture/compare 3 output enable [0] (in _TIM5_CCER2)

Definition at line 4370 of file STM8AF_STM8S.h.

◆ _TIM5_CC3G

#define _TIM5_CC3G ((uint8_t) (0x01 << 3))

TIM5 Capture/compare 3 generation [0] (in _TIM5_EGR)

Definition at line 4287 of file STM8AF_STM8S.h.

◆ _TIM5_CC3IE

#define _TIM5_CC3IE ((uint8_t) (0x01 << 3))

TIM5 Capture/compare 3 interrupt enable [0] (in _TIM5_IER)

Definition at line 4262 of file STM8AF_STM8S.h.

◆ _TIM5_CC3IF

#define _TIM5_CC3IF ((uint8_t) (0x01 << 3))

TIM5 Capture/compare 3 interrupt flag [0] (in _TIM5_SR1)

Definition at line 4271 of file STM8AF_STM8S.h.

◆ _TIM5_CC3OF

#define _TIM5_CC3OF ((uint8_t) (0x01 << 3))

TIM5 Capture/compare 3 overcapture flag [0] (in _TIM5_SR2)

Definition at line 4280 of file STM8AF_STM8S.h.

◆ _TIM5_CC3P

#define _TIM5_CC3P ((uint8_t) (0x01 << 1))

TIM5 Capture/compare 3 output polarity [0] (in _TIM5_CCER2)

Definition at line 4371 of file STM8AF_STM8S.h.

◆ _TIM5_CC3S

#define _TIM5_CC3S ((uint8_t) (0x03 << 0))

TIM5 Compare 3 selection [1:0] (in _TIM5_CCMR3)

Definition at line 4339 of file STM8AF_STM8S.h.

◆ _TIM5_CC3S0

#define _TIM5_CC3S0 ((uint8_t) (0x01 << 0))

TIM5 Compare 3 selection [0] (in _TIM5_CCMR3)

Definition at line 4340 of file STM8AF_STM8S.h.

◆ _TIM5_CC3S1

#define _TIM5_CC3S1 ((uint8_t) (0x01 << 1))

TIM5 Compare 3 selection [1] (in _TIM5_CCMR3)

Definition at line 4341 of file STM8AF_STM8S.h.

◆ _TIM5_CCER1

#define _TIM5_CCER1 _SFR(uint8_t, TIM5_AddressBase+0x0A)

TIM5 Capture/compare enable register 1.

Definition at line 4188 of file STM8AF_STM8S.h.

◆ _TIM5_CCER1_RESET_VALUE

#define _TIM5_CCER1_RESET_VALUE ((uint8_t) 0x00)

TIM5 Capture/compare enable register 1 reset value.

Definition at line 4213 of file STM8AF_STM8S.h.

◆ _TIM5_CCER2

#define _TIM5_CCER2 _SFR(uint8_t, TIM5_AddressBase+0x0B)

TIM5 Capture/compare enable register 2.

Definition at line 4189 of file STM8AF_STM8S.h.

◆ _TIM5_CCER2_RESET_VALUE

#define _TIM5_CCER2_RESET_VALUE ((uint8_t) 0x00)

TIM5 Capture/compare enable register 2 reset value.

Definition at line 4214 of file STM8AF_STM8S.h.

◆ _TIM5_CCMR1

#define _TIM5_CCMR1 _SFR(uint8_t, TIM5_AddressBase+0x07)

TIM5 Capture/compare mode register 1.

Definition at line 4185 of file STM8AF_STM8S.h.

◆ _TIM5_CCMR1_RESET_VALUE

#define _TIM5_CCMR1_RESET_VALUE ((uint8_t) 0x00)

TIM5 Capture/compare mode register 1 reset value.

Definition at line 4210 of file STM8AF_STM8S.h.

◆ _TIM5_CCMR2

#define _TIM5_CCMR2 _SFR(uint8_t, TIM5_AddressBase+0x08)

TIM5 Capture/compare mode register 2.

Definition at line 4186 of file STM8AF_STM8S.h.

◆ _TIM5_CCMR2_RESET_VALUE

#define _TIM5_CCMR2_RESET_VALUE ((uint8_t) 0x00)

TIM5 Capture/compare mode register 2 reset value.

Definition at line 4211 of file STM8AF_STM8S.h.

◆ _TIM5_CCMR3

#define _TIM5_CCMR3 _SFR(uint8_t, TIM5_AddressBase+0x09)

TIM5 Capture/compare mode register 3.

Definition at line 4187 of file STM8AF_STM8S.h.

◆ _TIM5_CCMR3_RESET_VALUE

#define _TIM5_CCMR3_RESET_VALUE ((uint8_t) 0x00)

TIM5 Capture/compare mode register 3 reset value.

Definition at line 4212 of file STM8AF_STM8S.h.

◆ _TIM5_CCPC

#define _TIM5_CCPC ((uint8_t) (0x01 << 0))

TIM5 Capture/compare preloaded control [0] (in _TIM5_CR2)

Definition at line 4236 of file STM8AF_STM8S.h.

◆ _TIM5_CCR1H

#define _TIM5_CCR1H _SFR(uint8_t, TIM5_AddressBase+0x11)

TIM5 16-bit capture/compare value 1 high byte.

Definition at line 4195 of file STM8AF_STM8S.h.

◆ _TIM5_CCR1H_RESET_VALUE

#define _TIM5_CCR1H_RESET_VALUE ((uint8_t) 0x00)

TIM5 16-bit capture/compare value 1 high byte reset value.

Definition at line 4220 of file STM8AF_STM8S.h.

◆ _TIM5_CCR1L

#define _TIM5_CCR1L _SFR(uint8_t, TIM5_AddressBase+0x12)

TIM5 16-bit capture/compare value 1 low byte.

Definition at line 4196 of file STM8AF_STM8S.h.

◆ _TIM5_CCR1L_RESET_VALUE

#define _TIM5_CCR1L_RESET_VALUE ((uint8_t) 0x00)

TIM5 16-bit capture/compare value 1 low byte reset value.

Definition at line 4221 of file STM8AF_STM8S.h.

◆ _TIM5_CCR2H

#define _TIM5_CCR2H _SFR(uint8_t, TIM5_AddressBase+0x13)

TIM5 16-bit capture/compare value 2 high byte.

Definition at line 4197 of file STM8AF_STM8S.h.

◆ _TIM5_CCR2H_RESET_VALUE

#define _TIM5_CCR2H_RESET_VALUE ((uint8_t) 0x00)

TIM5 16-bit capture/compare value 2 high byte reset value.

Definition at line 4222 of file STM8AF_STM8S.h.

◆ _TIM5_CCR2L

#define _TIM5_CCR2L _SFR(uint8_t, TIM5_AddressBase+0x14)

TIM5 16-bit capture/compare value 2 low byte.

Definition at line 4198 of file STM8AF_STM8S.h.

◆ _TIM5_CCR2L_RESET_VALUE

#define _TIM5_CCR2L_RESET_VALUE ((uint8_t) 0x00)

TIM5 16-bit capture/compare value 2 low byte reset value.

Definition at line 4223 of file STM8AF_STM8S.h.

◆ _TIM5_CCR3H

#define _TIM5_CCR3H _SFR(uint8_t, TIM5_AddressBase+0x15)

TIM5 16-bit capture/compare value 3 high byte.

Definition at line 4199 of file STM8AF_STM8S.h.

◆ _TIM5_CCR3H_RESET_VALUE

#define _TIM5_CCR3H_RESET_VALUE ((uint8_t) 0x00)

TIM5 16-bit capture/compare value 3 high byte reset value.

Definition at line 4224 of file STM8AF_STM8S.h.

◆ _TIM5_CCR3L

#define _TIM5_CCR3L _SFR(uint8_t, TIM5_AddressBase+0x16)

TIM5 16-bit capture/compare value 3 low byte.

Definition at line 4200 of file STM8AF_STM8S.h.

◆ _TIM5_CCR3L_RESET_VALUE

#define _TIM5_CCR3L_RESET_VALUE ((uint8_t) 0x00)

TIM5 16-bit capture/compare value 3 low byte reset value.

Definition at line 4225 of file STM8AF_STM8S.h.

◆ _TIM5_CEN

#define _TIM5_CEN ((uint8_t) (0x01 << 0))

TIM5 Counter enable [0] (in _TIM5_CR1)

Definition at line 4228 of file STM8AF_STM8S.h.

◆ _TIM5_CNTRH

#define _TIM5_CNTRH _SFR(uint8_t, TIM5_AddressBase+0x0C)

TIM5 counter register high byte.

Definition at line 4190 of file STM8AF_STM8S.h.

◆ _TIM5_CNTRH_RESET_VALUE

#define _TIM5_CNTRH_RESET_VALUE ((uint8_t) 0x00)

TIM5 counter register high byte reset value.

Definition at line 4215 of file STM8AF_STM8S.h.

◆ _TIM5_CNTRL

#define _TIM5_CNTRL _SFR(uint8_t, TIM5_AddressBase+0x0D)

TIM5 counter register low byte.

Definition at line 4191 of file STM8AF_STM8S.h.

◆ _TIM5_CNTRL_RESET_VALUE

#define _TIM5_CNTRL_RESET_VALUE ((uint8_t) 0x00)

TIM5 counter register low byte reset value.

Definition at line 4216 of file STM8AF_STM8S.h.

◆ _TIM5_COMS

#define _TIM5_COMS ((uint8_t) (0x01 << 2))

TIM5 Capture/compare control update selection [0] (in _TIM5_CR2)

Definition at line 4238 of file STM8AF_STM8S.h.

◆ _TIM5_CR1

#define _TIM5_CR1 _SFR(uint8_t, TIM5_AddressBase+0x00)

TIM5 control register 1.

Definition at line 4178 of file STM8AF_STM8S.h.

◆ _TIM5_CR1_RESET_VALUE

#define _TIM5_CR1_RESET_VALUE ((uint8_t) 0x00)

TIM5 control register 1 reset value.

Definition at line 4203 of file STM8AF_STM8S.h.

◆ _TIM5_CR2

#define _TIM5_CR2 _SFR(uint8_t, TIM5_AddressBase+0x01)

TIM5 control register 2.

Definition at line 4179 of file STM8AF_STM8S.h.

◆ _TIM5_CR2_RESET_VALUE

#define _TIM5_CR2_RESET_VALUE ((uint8_t) 0x00)

TIM5 control register 2 reset value.

Definition at line 4204 of file STM8AF_STM8S.h.

◆ _TIM5_EGR

#define _TIM5_EGR _SFR(uint8_t, TIM5_AddressBase+0x06)

TIM5 Event generation register.

Definition at line 4184 of file STM8AF_STM8S.h.

◆ _TIM5_EGR_RESET_VALUE

#define _TIM5_EGR_RESET_VALUE ((uint8_t) 0x00)

TIM5 Event generation register reset value.

Definition at line 4209 of file STM8AF_STM8S.h.

◆ _TIM5_IC1F

#define _TIM5_IC1F ((uint8_t) (0x0F << 4))

TIM5 Output compare 1 mode [3:0] (in _TIM5_CCMR1)

Definition at line 4309 of file STM8AF_STM8S.h.

◆ _TIM5_IC1F0

#define _TIM5_IC1F0 ((uint8_t) (0x01 << 4))

TIM5 Input capture 1 filter [0] (in _TIM5_CCMR1)

Definition at line 4310 of file STM8AF_STM8S.h.

◆ _TIM5_IC1F1

#define _TIM5_IC1F1 ((uint8_t) (0x01 << 5))

TIM5 Input capture 1 filter [1] (in _TIM5_CCMR1)

Definition at line 4311 of file STM8AF_STM8S.h.

◆ _TIM5_IC1F2

#define _TIM5_IC1F2 ((uint8_t) (0x01 << 6))

TIM5 Input capture 1 filter [2] (in _TIM5_CCMR1)

Definition at line 4312 of file STM8AF_STM8S.h.

◆ _TIM5_IC1F3

#define _TIM5_IC1F3 ((uint8_t) (0x01 << 7))

TIM5 Input capture 1 filter [3] (in _TIM5_CCMR1)

Definition at line 4313 of file STM8AF_STM8S.h.

◆ _TIM5_IC1PSC

#define _TIM5_IC1PSC ((uint8_t) (0x03 << 2))

TIM5 Input capture 1 prescaler [1:0] (in _TIM5_CCMR1)

Definition at line 4306 of file STM8AF_STM8S.h.

◆ _TIM5_IC1PSC0

#define _TIM5_IC1PSC0 ((uint8_t) (0x01 << 2))

TIM5 Input capture 1 prescaler [0] (in _TIM5_CCMR1)

Definition at line 4307 of file STM8AF_STM8S.h.

◆ _TIM5_IC1PSC1

#define _TIM5_IC1PSC1 ((uint8_t) (0x01 << 3))

TIM5 Input capture 1 prescaler [1] (in _TIM5_CCMR1)

Definition at line 4308 of file STM8AF_STM8S.h.

◆ _TIM5_IC2F

#define _TIM5_IC2F ((uint8_t) (0x0F << 4))

TIM5 Output compare 2 mode [3:0] (in _TIM5_CCMR2)

Definition at line 4332 of file STM8AF_STM8S.h.

◆ _TIM5_IC2F0

#define _TIM5_IC2F0 ((uint8_t) (0x01 << 4))

TIM5 Input capture 2 filter [0] (in _TIM5_CCMR2)

Definition at line 4333 of file STM8AF_STM8S.h.

◆ _TIM5_IC2F1

#define _TIM5_IC2F1 ((uint8_t) (0x01 << 5))

TIM5 Input capture 2 filter [1] (in _TIM5_CCMR2)

Definition at line 4334 of file STM8AF_STM8S.h.

◆ _TIM5_IC2F2

#define _TIM5_IC2F2 ((uint8_t) (0x01 << 6))

TIM5 Input capture 2 filter [2] (in _TIM5_CCMR2)

Definition at line 4335 of file STM8AF_STM8S.h.

◆ _TIM5_IC2F3

#define _TIM5_IC2F3 ((uint8_t) (0x01 << 7))

TIM5 Input capture 2 filter [3] (in _TIM5_CCMR2)

Definition at line 4336 of file STM8AF_STM8S.h.

◆ _TIM5_IC2PSC

#define _TIM5_IC2PSC ((uint8_t) (0x03 << 2))

TIM5 Input capture 2 prescaler [1:0] (in _TIM5_CCMR2)

Definition at line 4329 of file STM8AF_STM8S.h.

◆ _TIM5_IC2PSC0

#define _TIM5_IC2PSC0 ((uint8_t) (0x01 << 2))

TIM5 Input capture 2 prescaler [0] (in _TIM5_CCMR2)

Definition at line 4330 of file STM8AF_STM8S.h.

◆ _TIM5_IC2PSC1

#define _TIM5_IC2PSC1 ((uint8_t) (0x01 << 3))

TIM5 Input capture 2 prescaler [1] (in _TIM5_CCMR2)

Definition at line 4331 of file STM8AF_STM8S.h.

◆ _TIM5_IC3F

#define _TIM5_IC3F ((uint8_t) (0x0F << 4))

TIM5 Output compare 3 mode [3:0] (in _TIM5_CCMR3)

Definition at line 4355 of file STM8AF_STM8S.h.

◆ _TIM5_IC3F0

#define _TIM5_IC3F0 ((uint8_t) (0x01 << 4))

TIM5 Input capture 3 filter [0] (in _TIM5_CCMR3)

Definition at line 4356 of file STM8AF_STM8S.h.

◆ _TIM5_IC3F1

#define _TIM5_IC3F1 ((uint8_t) (0x01 << 5))

TIM5 Input capture 3 filter [1] (in _TIM5_CCMR3)

Definition at line 4357 of file STM8AF_STM8S.h.

◆ _TIM5_IC3F2

#define _TIM5_IC3F2 ((uint8_t) (0x01 << 6))

TIM5 Input capture 3 filter [2] (in _TIM5_CCMR3)

Definition at line 4358 of file STM8AF_STM8S.h.

◆ _TIM5_IC3F3

#define _TIM5_IC3F3 ((uint8_t) (0x01 << 7))

TIM5 Input capture 3 filter [3] (in _TIM5_CCMR3)

Definition at line 4359 of file STM8AF_STM8S.h.

◆ _TIM5_IC3PSC

#define _TIM5_IC3PSC ((uint8_t) (0x03 << 2))

TIM5 Input capture 3 prescaler [1:0] (in _TIM5_CCMR3)

Definition at line 4352 of file STM8AF_STM8S.h.

◆ _TIM5_IC3PSC0

#define _TIM5_IC3PSC0 ((uint8_t) (0x01 << 2))

TIM5 Input capture 3 prescaler [0] (in _TIM5_CCMR3)

Definition at line 4353 of file STM8AF_STM8S.h.

◆ _TIM5_IC3PSC1

#define _TIM5_IC3PSC1 ((uint8_t) (0x01 << 3))

TIM5 Input capture 3 prescaler [1] (in _TIM5_CCMR3)

Definition at line 4354 of file STM8AF_STM8S.h.

◆ _TIM5_IER

#define _TIM5_IER _SFR(uint8_t, TIM5_AddressBase+0x03)

TIM5 interrupt enable register.

Definition at line 4181 of file STM8AF_STM8S.h.

◆ _TIM5_IER_RESET_VALUE

#define _TIM5_IER_RESET_VALUE ((uint8_t) 0x00)

TIM5 interrupt enable register reset value.

Definition at line 4206 of file STM8AF_STM8S.h.

◆ _TIM5_MMS

#define _TIM5_MMS ((uint8_t) (0x07 << 4))

TIM5 Master mode selection [2:0] (in _TIM5_CR2)

Definition at line 4240 of file STM8AF_STM8S.h.

◆ _TIM5_MMS0

#define _TIM5_MMS0 ((uint8_t) (0x01 << 4))

TIM5 Master mode selection [0] (in _TIM5_CR2)

Definition at line 4241 of file STM8AF_STM8S.h.

◆ _TIM5_MMS1

#define _TIM5_MMS1 ((uint8_t) (0x01 << 5))

TIM5 Master mode selection [1] (in _TIM5_CR2)

Definition at line 4242 of file STM8AF_STM8S.h.

◆ _TIM5_MMS2

#define _TIM5_MMS2 ((uint8_t) (0x01 << 6))

TIM5 Master mode selection [2] (in _TIM5_CR2)

Definition at line 4243 of file STM8AF_STM8S.h.

◆ _TIM5_MSM

#define _TIM5_MSM ((uint8_t) (0x01 << 7))

TIM5 Master/slave mode [0] (in _TIM5_SMCR)

Definition at line 4256 of file STM8AF_STM8S.h.

◆ _TIM5_OC1M

#define _TIM5_OC1M ((uint8_t) (0x07 << 4))

TIM5 Output compare 1 mode [2:0] (in _TIM5_CCMR1)

Definition at line 4298 of file STM8AF_STM8S.h.

◆ _TIM5_OC1M0

#define _TIM5_OC1M0 ((uint8_t) (0x01 << 4))

TIM5 Output compare 1 mode [0] (in _TIM5_CCMR1)

Definition at line 4299 of file STM8AF_STM8S.h.

◆ _TIM5_OC1M1

#define _TIM5_OC1M1 ((uint8_t) (0x01 << 5))

TIM5 Output compare 1 mode [1] (in _TIM5_CCMR1)

Definition at line 4300 of file STM8AF_STM8S.h.

◆ _TIM5_OC1M2

#define _TIM5_OC1M2 ((uint8_t) (0x01 << 6))

TIM5 Output compare 1 mode [2] (in _TIM5_CCMR1)

Definition at line 4301 of file STM8AF_STM8S.h.

◆ _TIM5_OC1PE

#define _TIM5_OC1PE ((uint8_t) (0x01 << 3))

TIM5 Output compare 1 preload enable [0] (in _TIM5_CCMR1)

Definition at line 4297 of file STM8AF_STM8S.h.

◆ _TIM5_OC2M

#define _TIM5_OC2M ((uint8_t) (0x07 << 4))

TIM5 Output compare 2 mode [2:0] (in _TIM5_CCMR2)

Definition at line 4321 of file STM8AF_STM8S.h.

◆ _TIM5_OC2M0

#define _TIM5_OC2M0 ((uint8_t) (0x01 << 4))

TIM5 Output compare 2 mode [0] (in _TIM5_CCMR2)

Definition at line 4322 of file STM8AF_STM8S.h.

◆ _TIM5_OC2M1

#define _TIM5_OC2M1 ((uint8_t) (0x01 << 5))

TIM5 Output compare 2 mode [1] (in _TIM5_CCMR2)

Definition at line 4323 of file STM8AF_STM8S.h.

◆ _TIM5_OC2M2

#define _TIM5_OC2M2 ((uint8_t) (0x01 << 6))

TIM5 Output compare 2 mode [2] (in _TIM5_CCMR2)

Definition at line 4324 of file STM8AF_STM8S.h.

◆ _TIM5_OC2PE

#define _TIM5_OC2PE ((uint8_t) (0x01 << 3))

TIM5 Output compare 2 preload enable [0] (in _TIM5_CCMR2)

Definition at line 4320 of file STM8AF_STM8S.h.

◆ _TIM5_OC3M

#define _TIM5_OC3M ((uint8_t) (0x07 << 4))

TIM5 Output compare 3 mode [2:0] (in _TIM5_CCMR3)

Definition at line 4344 of file STM8AF_STM8S.h.

◆ _TIM5_OC3M0

#define _TIM5_OC3M0 ((uint8_t) (0x01 << 4))

TIM5 Output compare 3 mode [0] (in _TIM5_CCMR3)

Definition at line 4345 of file STM8AF_STM8S.h.

◆ _TIM5_OC3M1

#define _TIM5_OC3M1 ((uint8_t) (0x01 << 5))

TIM5 Output compare 3 mode [1] (in _TIM5_CCMR3)

Definition at line 4346 of file STM8AF_STM8S.h.

◆ _TIM5_OC3M2

#define _TIM5_OC3M2 ((uint8_t) (0x01 << 6))

TIM5 Output compare 3 mode [2] (in _TIM5_CCMR3)

Definition at line 4347 of file STM8AF_STM8S.h.

◆ _TIM5_OC3PE

#define _TIM5_OC3PE ((uint8_t) (0x01 << 3))

TIM5 Output compare 3 preload enable [0] (in _TIM5_CCMR3)

Definition at line 4343 of file STM8AF_STM8S.h.

◆ _TIM5_OPM

#define _TIM5_OPM ((uint8_t) (0x01 << 3))

TIM5 One-pulse mode [0] (in _TIM5_CR1)

Definition at line 4231 of file STM8AF_STM8S.h.

◆ _TIM5_PSC

#define _TIM5_PSC ((uint8_t) (0x0F << 0))

TIM5 clock prescaler [3:0] (in _TIM5_PSCR)

Definition at line 4375 of file STM8AF_STM8S.h.

◆ _TIM5_PSC0

#define _TIM5_PSC0 ((uint8_t) (0x01 << 0))

TIM5 clock prescaler [0] (in _TIM5_PSCR)

Definition at line 4376 of file STM8AF_STM8S.h.

◆ _TIM5_PSC1

#define _TIM5_PSC1 ((uint8_t) (0x01 << 1))

TIM5 clock prescaler [1] (in _TIM5_PSCR)

Definition at line 4377 of file STM8AF_STM8S.h.

◆ _TIM5_PSC2

#define _TIM5_PSC2 ((uint8_t) (0x01 << 2))

TIM5 clock prescaler [2] (in _TIM5_PSCR)

Definition at line 4378 of file STM8AF_STM8S.h.

◆ _TIM5_PSC3

#define _TIM5_PSC3 ((uint8_t) (0x01 << 3))

TIM5 clock prescaler [3] (in _TIM5_PSCR)

Definition at line 4379 of file STM8AF_STM8S.h.

◆ _TIM5_PSCR

#define _TIM5_PSCR _SFR(uint8_t, TIM5_AddressBase+0x0E)

TIM5 clock prescaler register.

Definition at line 4192 of file STM8AF_STM8S.h.

◆ _TIM5_PSCR_RESET_VALUE

#define _TIM5_PSCR_RESET_VALUE ((uint8_t) 0x00)

TIM5 clock prescaler register reset value.

Definition at line 4217 of file STM8AF_STM8S.h.

◆ _TIM5_SMCR

#define _TIM5_SMCR _SFR(uint8_t, TIM5_AddressBase+0x02)

TIM5 Slave mode control register.

Definition at line 4180 of file STM8AF_STM8S.h.

◆ _TIM5_SMCR_RESET_VALUE

#define _TIM5_SMCR_RESET_VALUE ((uint8_t) 0x00)

TIM5 Slave mode control register reset value.

Definition at line 4205 of file STM8AF_STM8S.h.

◆ _TIM5_SMS

#define _TIM5_SMS ((uint8_t) (0x07 << 0))

TIM5 Clock/trigger/slave mode selection [2:0] (in _TIM5_SMCR)

Definition at line 4247 of file STM8AF_STM8S.h.

◆ _TIM5_SMS0

#define _TIM5_SMS0 ((uint8_t) (0x01 << 0))

TIM5 Clock/trigger/slave mode selection [0] (in _TIM5_SMCR)

Definition at line 4248 of file STM8AF_STM8S.h.

◆ _TIM5_SMS1

#define _TIM5_SMS1 ((uint8_t) (0x01 << 1))

TIM5 Clock/trigger/slave mode selection [1] (in _TIM5_SMCR)

Definition at line 4249 of file STM8AF_STM8S.h.

◆ _TIM5_SMS2

#define _TIM5_SMS2 ((uint8_t) (0x01 << 2))

TIM5 Clock/trigger/slave mode selection [2] (in _TIM5_SMCR)

Definition at line 4250 of file STM8AF_STM8S.h.

◆ _TIM5_SR1

#define _TIM5_SR1 _SFR(uint8_t, TIM5_AddressBase+0x04)

TIM5 status register 1.

Definition at line 4182 of file STM8AF_STM8S.h.

◆ _TIM5_SR1_RESET_VALUE

#define _TIM5_SR1_RESET_VALUE ((uint8_t) 0x00)

TIM5 status register 1 reset value.

Definition at line 4207 of file STM8AF_STM8S.h.

◆ _TIM5_SR2

#define _TIM5_SR2 _SFR(uint8_t, TIM5_AddressBase+0x05)

TIM5 status register 2.

Definition at line 4183 of file STM8AF_STM8S.h.

◆ _TIM5_SR2_RESET_VALUE

#define _TIM5_SR2_RESET_VALUE ((uint8_t) 0x00)

TIM5 status register 2 reset value.

Definition at line 4208 of file STM8AF_STM8S.h.

◆ _TIM5_TG

#define _TIM5_TG ((uint8_t) (0x01 << 6))

TIM5 Trigger generation [0] (in _TIM5_EGR)

Definition at line 4289 of file STM8AF_STM8S.h.

◆ _TIM5_TIE

#define _TIM5_TIE ((uint8_t) (0x01 << 6))

TIM5 Trigger interrupt enable [0] (in _TIM5_IER)

Definition at line 4264 of file STM8AF_STM8S.h.

◆ _TIM5_TIF

#define _TIM5_TIF ((uint8_t) (0x01 << 6))

TIM5 Trigger interrupt flag [0] (in _TIM5_SR1)

Definition at line 4273 of file STM8AF_STM8S.h.

◆ _TIM5_TS

#define _TIM5_TS ((uint8_t) (0x07 << 4))

TIM5 Trigger selection [2:0] (in _TIM5_SMCR)

Definition at line 4252 of file STM8AF_STM8S.h.

◆ _TIM5_TS0

#define _TIM5_TS0 ((uint8_t) (0x01 << 4))

TIM5 Trigger selection [0] (in _TIM5_SMCR)

Definition at line 4253 of file STM8AF_STM8S.h.

◆ _TIM5_TS1

#define _TIM5_TS1 ((uint8_t) (0x01 << 5))

TIM5 Trigger selection [1] (in _TIM5_SMCR)

Definition at line 4254 of file STM8AF_STM8S.h.

◆ _TIM5_TS2

#define _TIM5_TS2 ((uint8_t) (0x01 << 6))

TIM5 Trigger selection [2] (in _TIM5_SMCR)

Definition at line 4255 of file STM8AF_STM8S.h.

◆ _TIM5_UDIS

#define _TIM5_UDIS ((uint8_t) (0x01 << 1))

TIM5 Update disable [0] (in _TIM5_CR1)

Definition at line 4229 of file STM8AF_STM8S.h.

◆ _TIM5_UG

#define _TIM5_UG ((uint8_t) (0x01 << 0))

TIM5 Update generation [0] (in _TIM5_EGR)

Definition at line 4284 of file STM8AF_STM8S.h.

◆ _TIM5_UIE

#define _TIM5_UIE ((uint8_t) (0x01 << 0))

TIM5 Update interrupt enable [0] (in _TIM5_IER)

Definition at line 4259 of file STM8AF_STM8S.h.

◆ _TIM5_UIF

#define _TIM5_UIF ((uint8_t) (0x01 << 0))

TIM5 Update interrupt flag [0] (in _TIM5_SR1)

Definition at line 4268 of file STM8AF_STM8S.h.

◆ _TIM5_URS

#define _TIM5_URS ((uint8_t) (0x01 << 2))

TIM5 Update request source [0] (in _TIM5_CR1)

Definition at line 4230 of file STM8AF_STM8S.h.

◆ _TIM6

#define _TIM6 _SFR(TIM6_t, TIM6_AddressBase)

TIM6 struct/bit access.

Definition at line 4464 of file STM8AF_STM8S.h.

◆ _TIM6_ARPE

#define _TIM6_ARPE ((uint8_t) (0x01 << 7))

TIM6 Auto-reload preload enable [0] (in _TIM6_CR1)

Definition at line 4488 of file STM8AF_STM8S.h.

◆ _TIM6_ARR

#define _TIM6_ARR _SFR(uint8_t, TIM6_AddressBase+0x06)

TIM6 auto-reload register.

Definition at line 4471 of file STM8AF_STM8S.h.

◆ _TIM6_ARR_RESET_VALUE

#define _TIM6_ARR_RESET_VALUE ((uint8_t) 0xFF)

TIM6 auto-reload register reset value.

Definition at line 4480 of file STM8AF_STM8S.h.

◆ _TIM6_CEN

#define _TIM6_CEN ((uint8_t) (0x01 << 0))

TIM6 Counter enable [0] (in _TIM6_CR1)

Definition at line 4483 of file STM8AF_STM8S.h.

◆ _TIM6_CNTR

#define _TIM6_CNTR _SFR(uint8_t, TIM6_AddressBase+0x04)

TIM6 counter register.

Definition at line 4469 of file STM8AF_STM8S.h.

◆ _TIM6_CNTR_RESET_VALUE

#define _TIM6_CNTR_RESET_VALUE ((uint8_t) 0x00)

TIM6 counter register reset value.

Definition at line 4478 of file STM8AF_STM8S.h.

◆ _TIM6_CR

#define _TIM6_CR _SFR(uint8_t, TIM6_AddressBase+0x00)

TIM6 control register.

Definition at line 4465 of file STM8AF_STM8S.h.

◆ _TIM6_CR_RESET_VALUE

#define _TIM6_CR_RESET_VALUE ((uint8_t) 0x00)

TIM6 control register reset value.

Definition at line 4474 of file STM8AF_STM8S.h.

◆ _TIM6_EGR

#define _TIM6_EGR _SFR(uint8_t, TIM6_AddressBase+0x03)

TIM6 event generation register.

Definition at line 4468 of file STM8AF_STM8S.h.

◆ _TIM6_EGR_RESET_VALUE

#define _TIM6_EGR_RESET_VALUE ((uint8_t) 0x00)

TIM6 event generation register reset value.

Definition at line 4477 of file STM8AF_STM8S.h.

◆ _TIM6_IER

#define _TIM6_IER _SFR(uint8_t, TIM6_AddressBase+0x01)

TIM6 interrupt enable register.

Definition at line 4466 of file STM8AF_STM8S.h.

◆ _TIM6_IER_RESET_VALUE

#define _TIM6_IER_RESET_VALUE ((uint8_t) 0x00)

TIM6 interrupt enable register reset value.

Definition at line 4475 of file STM8AF_STM8S.h.

◆ _TIM6_MMS

#define _TIM6_MMS ((uint8_t) (0x07 << 4))

TIM6 Master mode selection [2:0] (in _TIM6_CR2)

Definition at line 4492 of file STM8AF_STM8S.h.

◆ _TIM6_MMS0

#define _TIM6_MMS0 ((uint8_t) (0x01 << 4))

TIM6 Master mode selection [0] (in _TIM6_CR2)

Definition at line 4493 of file STM8AF_STM8S.h.

◆ _TIM6_MMS1

#define _TIM6_MMS1 ((uint8_t) (0x01 << 5))

TIM6 Master mode selection [1] (in _TIM6_CR2)

Definition at line 4494 of file STM8AF_STM8S.h.

◆ _TIM6_MMS2

#define _TIM6_MMS2 ((uint8_t) (0x01 << 6))

TIM6 Master mode selection [2] (in _TIM6_CR2)

Definition at line 4495 of file STM8AF_STM8S.h.

◆ _TIM6_OPM

#define _TIM6_OPM ((uint8_t) (0x01 << 3))

TIM6 One-pulse mode [0] (in _TIM6_CR1)

Definition at line 4486 of file STM8AF_STM8S.h.

◆ _TIM6_PSC

#define _TIM6_PSC ((uint8_t) (0x07 << 0))

TIM6 clock prescaler [2:0] (in _TIM6_PSCR)

Definition at line 4523 of file STM8AF_STM8S.h.

◆ _TIM6_PSC0

#define _TIM6_PSC0 ((uint8_t) (0x01 << 0))

TIM6 clock prescaler [0] (in _TIM6_PSCR)

Definition at line 4524 of file STM8AF_STM8S.h.

◆ _TIM6_PSC1

#define _TIM6_PSC1 ((uint8_t) (0x01 << 1))

TIM6 clock prescaler [1] (in _TIM6_PSCR)

Definition at line 4525 of file STM8AF_STM8S.h.

◆ _TIM6_PSC2

#define _TIM6_PSC2 ((uint8_t) (0x01 << 2))

TIM6 clock prescaler [2] (in _TIM6_PSCR)

Definition at line 4526 of file STM8AF_STM8S.h.

◆ _TIM6_PSCR

#define _TIM6_PSCR _SFR(uint8_t, TIM6_AddressBase+0x05)

TIM6 clock prescaler register.

Definition at line 4470 of file STM8AF_STM8S.h.

◆ _TIM6_PSCR_RESET_VALUE

#define _TIM6_PSCR_RESET_VALUE ((uint8_t) 0x00)

TIM6 clock prescaler register reset value.

Definition at line 4479 of file STM8AF_STM8S.h.

◆ _TIM6_SMS

#define _TIM6_SMS ((uint8_t) (0x07 << 0))

TIM6 Clock/trigger/slave mode selection [2:0] (in _TIM6_SMCR)

Definition at line 4499 of file STM8AF_STM8S.h.

◆ _TIM6_SMS0

#define _TIM6_SMS0 ((uint8_t) (0x01 << 0))

TIM6 Clock/trigger/slave mode selection [0] (in _TIM6_SMCR)

Definition at line 4500 of file STM8AF_STM8S.h.

◆ _TIM6_SMS1

#define _TIM6_SMS1 ((uint8_t) (0x01 << 1))

TIM6 Clock/trigger/slave mode selection [1] (in _TIM6_SMCR)

Definition at line 4501 of file STM8AF_STM8S.h.

◆ _TIM6_SMS2

#define _TIM6_SMS2 ((uint8_t) (0x01 << 2))

TIM6 Clock/trigger/slave mode selection [2] (in _TIM6_SMCR)

Definition at line 4502 of file STM8AF_STM8S.h.

◆ _TIM6_SR

#define _TIM6_SR _SFR(uint8_t, TIM6_AddressBase+0x02)

TIM6 status register.

Definition at line 4467 of file STM8AF_STM8S.h.

◆ _TIM6_SR_RESET_VALUE

#define _TIM6_SR_RESET_VALUE ((uint8_t) 0x00)

TIM6 status register reset value.

Definition at line 4476 of file STM8AF_STM8S.h.

◆ _TIM6_TS

#define _TIM6_TS ((uint8_t) (0x07 << 4))

TIM6 Trigger selection [2:0] (in _TIM6_SMCR)

Definition at line 4504 of file STM8AF_STM8S.h.

◆ _TIM6_TS0

#define _TIM6_TS0 ((uint8_t) (0x01 << 4))

TIM6 Trigger selection [0] (in _TIM6_SMCR)

Definition at line 4505 of file STM8AF_STM8S.h.

◆ _TIM6_TS1

#define _TIM6_TS1 ((uint8_t) (0x01 << 5))

TIM6 Trigger selection [1] (in _TIM6_SMCR)

Definition at line 4506 of file STM8AF_STM8S.h.

◆ _TIM6_TS2

#define _TIM6_TS2 ((uint8_t) (0x01 << 6))

TIM6 Trigger selection [2] (in _TIM6_SMCR)

Definition at line 4507 of file STM8AF_STM8S.h.

◆ _TIM6_UDIS

#define _TIM6_UDIS ((uint8_t) (0x01 << 1))

TIM6 Update disable [0] (in _TIM6_CR1)

Definition at line 4484 of file STM8AF_STM8S.h.

◆ _TIM6_UG

#define _TIM6_UG ((uint8_t) (0x01 << 0))

TIM6 Update generation [0] (in _TIM6_EGR)

Definition at line 4519 of file STM8AF_STM8S.h.

◆ _TIM6_UIE

#define _TIM6_UIE ((uint8_t) (0x01 << 0))

TIM6 Update interrupt enable [0] (in _TIM6_IER)

Definition at line 4511 of file STM8AF_STM8S.h.

◆ _TIM6_UIF

#define _TIM6_UIF ((uint8_t) (0x01 << 0))

TIM6 Update interrupt flag [0] (in _TIM6_SR)

Definition at line 4515 of file STM8AF_STM8S.h.

◆ _TIM6_URS

#define _TIM6_URS ((uint8_t) (0x01 << 2))

TIM6 Update request source [0] (in _TIM6_CR1)

Definition at line 4485 of file STM8AF_STM8S.h.

◆ _UART1

#define _UART1 _SFR(UART1_t, UART1_AddressBase)

UART1 struct/bit access.

Definition at line 1731 of file STM8AF_STM8S.h.

◆ _UART1_ADD

#define _UART1_ADD ((uint8_t) (0x0F << 0))

UART1 Address of the UART node [3:0] (in _UART1_CR4)

Definition at line 1798 of file STM8AF_STM8S.h.

◆ _UART1_ADD0

#define _UART1_ADD0 ((uint8_t) (0x01 << 0))

UART1 Address of the UART node [0] (in _UART1_CR4)

Definition at line 1799 of file STM8AF_STM8S.h.

◆ _UART1_ADD1

#define _UART1_ADD1 ((uint8_t) (0x01 << 1))

UART1 Address of the UART node [1] (in _UART1_CR4)

Definition at line 1800 of file STM8AF_STM8S.h.

◆ _UART1_ADD2

#define _UART1_ADD2 ((uint8_t) (0x01 << 2))

UART1 Address of the UART node [2] (in _UART1_CR4)

Definition at line 1801 of file STM8AF_STM8S.h.

◆ _UART1_ADD3

#define _UART1_ADD3 ((uint8_t) (0x01 << 3))

UART1 Address of the UART node [3] (in _UART1_CR4)

Definition at line 1802 of file STM8AF_STM8S.h.

◆ _UART1_BRR1

#define _UART1_BRR1 _SFR(uint8_t, UART1_AddressBase+0x02)

UART1 Baud rate register 1.

Definition at line 1734 of file STM8AF_STM8S.h.

◆ _UART1_BRR1_RESET_VALUE

#define _UART1_BRR1_RESET_VALUE ((uint8_t) 0x00)

UART1 Baud rate register 1 reset value.

Definition at line 1746 of file STM8AF_STM8S.h.

◆ _UART1_BRR2

#define _UART1_BRR2 _SFR(uint8_t, UART1_AddressBase+0x03)

UART1 Baud rate register 2.

Definition at line 1735 of file STM8AF_STM8S.h.

◆ _UART1_BRR2_RESET_VALUE

#define _UART1_BRR2_RESET_VALUE ((uint8_t) 0x00)

UART1 Baud rate register 2 reset value.

Definition at line 1747 of file STM8AF_STM8S.h.

◆ _UART1_CKEN

#define _UART1_CKEN ((uint8_t) (0x01 << 3))

UART1 Clock enable [0] (in _UART1_CR3)

Definition at line 1790 of file STM8AF_STM8S.h.

◆ _UART1_CPHA

#define _UART1_CPHA ((uint8_t) (0x01 << 1))

UART1 Clock phase [0] (in _UART1_CR3)

Definition at line 1788 of file STM8AF_STM8S.h.

◆ _UART1_CPOL

#define _UART1_CPOL ((uint8_t) (0x01 << 2))

UART1 Clock polarity [0] (in _UART1_CR3)

Definition at line 1789 of file STM8AF_STM8S.h.

◆ _UART1_CR1

#define _UART1_CR1 _SFR(uint8_t, UART1_AddressBase+0x04)

UART1 Control register 1.

Definition at line 1736 of file STM8AF_STM8S.h.

◆ _UART1_CR1_RESET_VALUE

#define _UART1_CR1_RESET_VALUE ((uint8_t) 0x00)

UART1 Control register 1 reset value.

Definition at line 1748 of file STM8AF_STM8S.h.

◆ _UART1_CR2

#define _UART1_CR2 _SFR(uint8_t, UART1_AddressBase+0x05)

UART1 Control register 2.

Definition at line 1737 of file STM8AF_STM8S.h.

◆ _UART1_CR2_RESET_VALUE

#define _UART1_CR2_RESET_VALUE ((uint8_t) 0x00)

UART1 Control register 2 reset value.

Definition at line 1749 of file STM8AF_STM8S.h.

◆ _UART1_CR3

#define _UART1_CR3 _SFR(uint8_t, UART1_AddressBase+0x06)

UART1 Control register 3.

Definition at line 1738 of file STM8AF_STM8S.h.

◆ _UART1_CR3_RESET_VALUE

#define _UART1_CR3_RESET_VALUE ((uint8_t) 0x00)

UART1 Control register 3 reset value.

Definition at line 1750 of file STM8AF_STM8S.h.

◆ _UART1_CR4

#define _UART1_CR4 _SFR(uint8_t, UART1_AddressBase+0x07)

UART1 Control register 4.

Definition at line 1739 of file STM8AF_STM8S.h.

◆ _UART1_CR4_RESET_VALUE

#define _UART1_CR4_RESET_VALUE ((uint8_t) 0x00)

UART1 Control register 4 reset value.

Definition at line 1751 of file STM8AF_STM8S.h.

◆ _UART1_CR5

#define _UART1_CR5 _SFR(uint8_t, UART1_AddressBase+0x08)

UART1 Control register 5.

Definition at line 1740 of file STM8AF_STM8S.h.

◆ _UART1_CR5_RESET_VALUE

#define _UART1_CR5_RESET_VALUE ((uint8_t) 0x00)

UART1 Control register 5 reset value.

Definition at line 1752 of file STM8AF_STM8S.h.

◆ _UART1_DR

#define _UART1_DR _SFR(uint8_t, UART1_AddressBase+0x01)

UART1 data register.

Definition at line 1733 of file STM8AF_STM8S.h.

◆ _UART1_FE

#define _UART1_FE ((uint8_t) (0x01 << 1))

UART1 Framing error [0] (in _UART1_SR)

Definition at line 1758 of file STM8AF_STM8S.h.

◆ _UART1_GTR

#define _UART1_GTR _SFR(uint8_t, UART1_AddressBase+0x09)

UART1 guard time register.

Definition at line 1741 of file STM8AF_STM8S.h.

◆ _UART1_GTR_RESET_VALUE

#define _UART1_GTR_RESET_VALUE ((uint8_t) 0x00)

UART1 guard time register reset value.

Definition at line 1753 of file STM8AF_STM8S.h.

◆ _UART1_HDSEL

#define _UART1_HDSEL ((uint8_t) (0x01 << 3))

UART1 Half-Duplex Selection [0] (in _UART1_CR5)

Definition at line 1812 of file STM8AF_STM8S.h.

◆ _UART1_IDLE

#define _UART1_IDLE ((uint8_t) (0x01 << 4))

UART1 IDLE line detected [0] (in _UART1_SR)

Definition at line 1761 of file STM8AF_STM8S.h.

◆ _UART1_ILIEN

#define _UART1_ILIEN ((uint8_t) (0x01 << 4))

UART1 IDLE Line interrupt enable [0] (in _UART1_CR2)

Definition at line 1781 of file STM8AF_STM8S.h.

◆ _UART1_IREN

#define _UART1_IREN ((uint8_t) (0x01 << 1))

UART1 IrDA mode Enable [0] (in _UART1_CR5)

Definition at line 1810 of file STM8AF_STM8S.h.

◆ _UART1_IRLP

#define _UART1_IRLP ((uint8_t) (0x01 << 2))

UART1 IrDA Low Power [0] (in _UART1_CR5)

Definition at line 1811 of file STM8AF_STM8S.h.

◆ _UART1_LBCL

#define _UART1_LBCL ((uint8_t) (0x01 << 0))

UART1 Last bit clock pulse [0] (in _UART1_CR3)

Definition at line 1787 of file STM8AF_STM8S.h.

◆ _UART1_LBDF

#define _UART1_LBDF ((uint8_t) (0x01 << 4))

UART1 LIN Break Detection Flag [0] (in _UART1_CR4)

Definition at line 1803 of file STM8AF_STM8S.h.

◆ _UART1_LBDIEN

#define _UART1_LBDIEN ((uint8_t) (0x01 << 6))

UART1 LIN Break Detection Interrupt Enable [0] (in _UART1_CR4)

Definition at line 1805 of file STM8AF_STM8S.h.

◆ _UART1_LBDL

#define _UART1_LBDL ((uint8_t) (0x01 << 5))

UART1 LIN Break Detection Length [0] (in _UART1_CR4)

Definition at line 1804 of file STM8AF_STM8S.h.

◆ _UART1_LINEN

#define _UART1_LINEN ((uint8_t) (0x01 << 6))

UART1 LIN mode enable [0] (in _UART1_CR3)

Definition at line 1794 of file STM8AF_STM8S.h.

◆ _UART1_M

#define _UART1_M ((uint8_t) (0x01 << 4))

UART1 word length [0] (in _UART1_CR1)

Definition at line 1771 of file STM8AF_STM8S.h.

◆ _UART1_NACK

#define _UART1_NACK ((uint8_t) (0x01 << 4))

UART1 Smartcard NACK enable [0] (in _UART1_CR5)

Definition at line 1813 of file STM8AF_STM8S.h.

◆ _UART1_NF

#define _UART1_NF ((uint8_t) (0x01 << 2))

UART1 Noise flag [0] (in _UART1_SR)

Definition at line 1759 of file STM8AF_STM8S.h.

◆ _UART1_OR_LHE

#define _UART1_OR_LHE ((uint8_t) (0x01 << 3))

UART1 LIN Header Error (LIN slave mode) / Overrun error [0] (in _UART1_SR)

Definition at line 1760 of file STM8AF_STM8S.h.

◆ _UART1_PCEN

#define _UART1_PCEN ((uint8_t) (0x01 << 2))

UART1 Parity control enable [0] (in _UART1_CR1)

Definition at line 1769 of file STM8AF_STM8S.h.

◆ _UART1_PE

#define _UART1_PE ((uint8_t) (0x01 << 0))

UART1 Parity error [0] (in _UART1_SR)

Definition at line 1757 of file STM8AF_STM8S.h.

◆ _UART1_PIEN

#define _UART1_PIEN ((uint8_t) (0x01 << 0))

UART1 Parity interrupt enable [0] (in _UART1_CR1)

Definition at line 1767 of file STM8AF_STM8S.h.

◆ _UART1_PS

#define _UART1_PS ((uint8_t) (0x01 << 1))

UART1 Parity selection [0] (in _UART1_CR1)

Definition at line 1768 of file STM8AF_STM8S.h.

◆ _UART1_PSCR

#define _UART1_PSCR _SFR(uint8_t, UART1_AddressBase+0x0A)

UART1 prescaler register.

Definition at line 1742 of file STM8AF_STM8S.h.

◆ _UART1_PSCR_RESET_VALUE

#define _UART1_PSCR_RESET_VALUE ((uint8_t) 0x00)

UART1 prescaler register reset value.

Definition at line 1754 of file STM8AF_STM8S.h.

◆ _UART1_R8

#define _UART1_R8 ((uint8_t) (0x01 << 7))

UART1 Receive Data bit 8 (in 9-bit mode) [0] (in _UART1_CR1)

Definition at line 1774 of file STM8AF_STM8S.h.

◆ _UART1_REN

#define _UART1_REN ((uint8_t) (0x01 << 2))

UART1 Receiver enable [0] (in _UART1_CR2)

Definition at line 1779 of file STM8AF_STM8S.h.

◆ _UART1_RIEN

#define _UART1_RIEN ((uint8_t) (0x01 << 5))

UART1 Receiver interrupt enable [0] (in _UART1_CR2)

Definition at line 1782 of file STM8AF_STM8S.h.

◆ _UART1_RWU

#define _UART1_RWU ((uint8_t) (0x01 << 1))

UART1 Receiver wakeup [0] (in _UART1_CR2)

Definition at line 1778 of file STM8AF_STM8S.h.

◆ _UART1_RXNE

#define _UART1_RXNE ((uint8_t) (0x01 << 5))

UART1 Read data register not empty [0] (in _UART1_SR)

Definition at line 1762 of file STM8AF_STM8S.h.

◆ _UART1_SBK

#define _UART1_SBK ((uint8_t) (0x01 << 0))

UART1 Send break [0] (in _UART1_CR2)

Definition at line 1777 of file STM8AF_STM8S.h.

◆ _UART1_SCEN

#define _UART1_SCEN ((uint8_t) (0x01 << 5))

UART1 Smartcard mode enable [0] (in _UART1_CR5)

Definition at line 1814 of file STM8AF_STM8S.h.

◆ _UART1_SR

#define _UART1_SR _SFR(uint8_t, UART1_AddressBase+0x00)

UART1 Status register.

Definition at line 1732 of file STM8AF_STM8S.h.

◆ _UART1_SR_RESET_VALUE

#define _UART1_SR_RESET_VALUE ((uint8_t) 0xC0)

UART1 Status register reset value.

Definition at line 1745 of file STM8AF_STM8S.h.

◆ _UART1_STOP

#define _UART1_STOP ((uint8_t) (0x03 << 4))

UART1 STOP bits [1:0] (in _UART1_CR3)

Definition at line 1791 of file STM8AF_STM8S.h.

◆ _UART1_STOP0

#define _UART1_STOP0 ((uint8_t) (0x01 << 4))

UART1 STOP bits [0] (in _UART1_CR3)

Definition at line 1792 of file STM8AF_STM8S.h.

◆ _UART1_STOP1

#define _UART1_STOP1 ((uint8_t) (0x01 << 5))

UART1 STOP bits [1] (in _UART1_CR3)

Definition at line 1793 of file STM8AF_STM8S.h.

◆ _UART1_T8

#define _UART1_T8 ((uint8_t) (0x01 << 6))

UART1 Transmit Data bit 8 (in 9-bit mode) [0] (in _UART1_CR1)

Definition at line 1773 of file STM8AF_STM8S.h.

◆ _UART1_TC

#define _UART1_TC ((uint8_t) (0x01 << 6))

UART1 Transmission complete [0] (in _UART1_SR)

Definition at line 1763 of file STM8AF_STM8S.h.

◆ _UART1_TCIEN

#define _UART1_TCIEN ((uint8_t) (0x01 << 6))

UART1 Transmission complete interrupt enable [0] (in _UART1_CR2)

Definition at line 1783 of file STM8AF_STM8S.h.

◆ _UART1_TEN

#define _UART1_TEN ((uint8_t) (0x01 << 3))

UART1 Transmitter enable [0] (in _UART1_CR2)

Definition at line 1780 of file STM8AF_STM8S.h.

◆ _UART1_TIEN

#define _UART1_TIEN ((uint8_t) (0x01 << 7))

UART1 Transmitter interrupt enable [0] (in _UART1_CR2)

Definition at line 1784 of file STM8AF_STM8S.h.

◆ _UART1_TXE

#define _UART1_TXE ((uint8_t) (0x01 << 7))

UART1 Transmit data register empty [0] (in _UART1_SR)

Definition at line 1764 of file STM8AF_STM8S.h.

◆ _UART1_UARTD

#define _UART1_UARTD ((uint8_t) (0x01 << 5))

UART1 Disable (for low power consumption) [0] (in _UART1_CR1)

Definition at line 1772 of file STM8AF_STM8S.h.

◆ _UART1_WAKE

#define _UART1_WAKE ((uint8_t) (0x01 << 3))

UART1 Wakeup method [0] (in _UART1_CR1)

Definition at line 1770 of file STM8AF_STM8S.h.

◆ _UART2

#define _UART2 _SFR(UART2_t, UART2_AddressBase)

UART2 struct/bit access.

Definition at line 1948 of file STM8AF_STM8S.h.

◆ _UART2_ADD

#define _UART2_ADD ((uint8_t) (0x0F << 0))

UART2 Address of the UART node [3:0] (in _UART2_CR4)

Definition at line 2017 of file STM8AF_STM8S.h.

◆ _UART2_ADD0

#define _UART2_ADD0 ((uint8_t) (0x01 << 0))

UART2 Address of the UART node [0] (in _UART2_CR4)

Definition at line 2018 of file STM8AF_STM8S.h.

◆ _UART2_ADD1

#define _UART2_ADD1 ((uint8_t) (0x01 << 1))

UART2 Address of the UART node [1] (in _UART2_CR4)

Definition at line 2019 of file STM8AF_STM8S.h.

◆ _UART2_ADD2

#define _UART2_ADD2 ((uint8_t) (0x01 << 2))

UART2 Address of the UART node [2] (in _UART2_CR4)

Definition at line 2020 of file STM8AF_STM8S.h.

◆ _UART2_ADD3

#define _UART2_ADD3 ((uint8_t) (0x01 << 3))

UART2 Address of the UART node [3] (in _UART2_CR4)

Definition at line 2021 of file STM8AF_STM8S.h.

◆ _UART2_BRR1

#define _UART2_BRR1 _SFR(uint8_t, UART2_AddressBase+0x02)

UART2 Baud rate register 1.

Definition at line 1951 of file STM8AF_STM8S.h.

◆ _UART2_BRR1_RESET_VALUE

#define _UART2_BRR1_RESET_VALUE ((uint8_t) 0x00)

UART2 Baud rate register 1 reset value.

Definition at line 1964 of file STM8AF_STM8S.h.

◆ _UART2_BRR2

#define _UART2_BRR2 _SFR(uint8_t, UART2_AddressBase+0x03)

UART2 Baud rate register 2.

Definition at line 1952 of file STM8AF_STM8S.h.

◆ _UART2_BRR2_RESET_VALUE

#define _UART2_BRR2_RESET_VALUE ((uint8_t) 0x00)

UART2 Baud rate register 2 reset value.

Definition at line 1965 of file STM8AF_STM8S.h.

◆ _UART2_CKEN

#define _UART2_CKEN ((uint8_t) (0x01 << 3))

UART2 Clock enable [0] (in _UART2_CR3)

Definition at line 2009 of file STM8AF_STM8S.h.

◆ _UART2_CPHA

#define _UART2_CPHA ((uint8_t) (0x01 << 1))

UART2 Clock phase [0] (in _UART2_CR3)

Definition at line 2007 of file STM8AF_STM8S.h.

◆ _UART2_CPOL

#define _UART2_CPOL ((uint8_t) (0x01 << 2))

UART2 Clock polarity [0] (in _UART2_CR3)

Definition at line 2008 of file STM8AF_STM8S.h.

◆ _UART2_CR1

#define _UART2_CR1 _SFR(uint8_t, UART2_AddressBase+0x04)

UART2 Control register 1.

Definition at line 1953 of file STM8AF_STM8S.h.

◆ _UART2_CR1_RESET_VALUE

#define _UART2_CR1_RESET_VALUE ((uint8_t) 0x00)

UART2 Control register 1 reset value.

Definition at line 1966 of file STM8AF_STM8S.h.

◆ _UART2_CR2

#define _UART2_CR2 _SFR(uint8_t, UART2_AddressBase+0x05)

UART2 Control register 2.

Definition at line 1954 of file STM8AF_STM8S.h.

◆ _UART2_CR2_RESET_VALUE

#define _UART2_CR2_RESET_VALUE ((uint8_t) 0x00)

UART2 Control register 2 reset value.

Definition at line 1967 of file STM8AF_STM8S.h.

◆ _UART2_CR3

#define _UART2_CR3 _SFR(uint8_t, UART2_AddressBase+0x06)

UART2 Control register 3.

Definition at line 1955 of file STM8AF_STM8S.h.

◆ _UART2_CR3_RESET_VALUE

#define _UART2_CR3_RESET_VALUE ((uint8_t) 0x00)

UART2 Control register 3 reset value.

Definition at line 1968 of file STM8AF_STM8S.h.

◆ _UART2_CR4

#define _UART2_CR4 _SFR(uint8_t, UART2_AddressBase+0x07)

UART2 Control register 4.

Definition at line 1956 of file STM8AF_STM8S.h.

◆ _UART2_CR4_RESET_VALUE

#define _UART2_CR4_RESET_VALUE ((uint8_t) 0x00)

UART2 Control register 4 reset value.

Definition at line 1969 of file STM8AF_STM8S.h.

◆ _UART2_CR5

#define _UART2_CR5 _SFR(uint8_t, UART2_AddressBase+0x08)

UART2 Control register 5.

Definition at line 1957 of file STM8AF_STM8S.h.

◆ _UART2_CR5_RESET_VALUE

#define _UART2_CR5_RESET_VALUE ((uint8_t) 0x00)

UART2 Control register 5 reset value.

Definition at line 1970 of file STM8AF_STM8S.h.

◆ _UART2_CR6

#define _UART2_CR6 _SFR(uint8_t, UART2_AddressBase+0x09)

UART2 Control register 6.

Definition at line 1958 of file STM8AF_STM8S.h.

◆ _UART2_CR6_RESET_VALUE

#define _UART2_CR6_RESET_VALUE ((uint8_t) 0x00)

UART2 Control register 6 reset value.

Definition at line 1971 of file STM8AF_STM8S.h.

◆ _UART2_DR

#define _UART2_DR _SFR(uint8_t, UART2_AddressBase+0x01)

UART2 data register.

Definition at line 1950 of file STM8AF_STM8S.h.

◆ _UART2_FE

#define _UART2_FE ((uint8_t) (0x01 << 1))

UART2 Framing error [0] (in _UART2_SR)

Definition at line 1977 of file STM8AF_STM8S.h.

◆ _UART2_GTR

#define _UART2_GTR _SFR(uint8_t, UART2_AddressBase+0x0A)

UART2 guard time register.

Definition at line 1959 of file STM8AF_STM8S.h.

◆ _UART2_GTR_RESET_VALUE

#define _UART2_GTR_RESET_VALUE ((uint8_t) 0x00)

UART2 guard time register reset value.

Definition at line 1972 of file STM8AF_STM8S.h.

◆ _UART2_IDLE

#define _UART2_IDLE ((uint8_t) (0x01 << 4))

UART2 IDLE line detected [0] (in _UART2_SR)

Definition at line 1980 of file STM8AF_STM8S.h.

◆ _UART2_ILIEN

#define _UART2_ILIEN ((uint8_t) (0x01 << 4))

UART2 IDLE Line interrupt enable [0] (in _UART2_CR2)

Definition at line 2000 of file STM8AF_STM8S.h.

◆ _UART2_IREN

#define _UART2_IREN ((uint8_t) (0x01 << 1))

UART2 IrDA mode Enable [0] (in _UART2_CR5)

Definition at line 2029 of file STM8AF_STM8S.h.

◆ _UART2_IRLP

#define _UART2_IRLP ((uint8_t) (0x01 << 2))

UART2 IrDA Low Power [0] (in _UART2_CR5)

Definition at line 2030 of file STM8AF_STM8S.h.

◆ _UART2_LASE

#define _UART2_LASE ((uint8_t) (0x01 << 4))

UART2 LIN automatic resynchronisation enable [0] (in _UART2_CR6)

Definition at line 2041 of file STM8AF_STM8S.h.

◆ _UART2_LBCL

#define _UART2_LBCL ((uint8_t) (0x01 << 0))

UART2 Last bit clock pulse [0] (in _UART2_CR3)

Definition at line 2006 of file STM8AF_STM8S.h.

◆ _UART2_LBDF

#define _UART2_LBDF ((uint8_t) (0x01 << 4))

UART2 LIN Break Detection Flag [0] (in _UART2_CR4)

Definition at line 2022 of file STM8AF_STM8S.h.

◆ _UART2_LBDIEN

#define _UART2_LBDIEN ((uint8_t) (0x01 << 6))

UART2 LIN Break Detection Interrupt Enable [0] (in _UART2_CR4)

Definition at line 2024 of file STM8AF_STM8S.h.

◆ _UART2_LBDL

#define _UART2_LBDL ((uint8_t) (0x01 << 5))

UART2 LIN Break Detection Length [0] (in _UART2_CR4)

Definition at line 2023 of file STM8AF_STM8S.h.

◆ _UART2_LDUM

#define _UART2_LDUM ((uint8_t) (0x01 << 7))

UART2 LIN Divider Update Method [0] (in _UART2_CR6)

Definition at line 2044 of file STM8AF_STM8S.h.

◆ _UART2_LHDF

#define _UART2_LHDF ((uint8_t) (0x01 << 1))

UART2 LIN Header Detection Flag [0] (in _UART2_CR6)

Definition at line 2038 of file STM8AF_STM8S.h.

◆ _UART2_LHDIEN

#define _UART2_LHDIEN ((uint8_t) (0x01 << 2))

UART2 LIN Header Detection Interrupt Enable [0] (in _UART2_CR6)

Definition at line 2039 of file STM8AF_STM8S.h.

◆ _UART2_LINEN

#define _UART2_LINEN ((uint8_t) (0x01 << 6))

UART2 LIN mode enable [0] (in _UART2_CR3)

Definition at line 2013 of file STM8AF_STM8S.h.

◆ _UART2_LSF

#define _UART2_LSF ((uint8_t) (0x01 << 0))

UART2 LIN Sync Field [0] (in _UART2_CR6)

Definition at line 2037 of file STM8AF_STM8S.h.

◆ _UART2_LSLV

#define _UART2_LSLV ((uint8_t) (0x01 << 5))

UART2 LIN Slave Enable [0] (in _UART2_CR6)

Definition at line 2042 of file STM8AF_STM8S.h.

◆ _UART2_M

#define _UART2_M ((uint8_t) (0x01 << 4))

UART2 word length [0] (in _UART2_CR1)

Definition at line 1990 of file STM8AF_STM8S.h.

◆ _UART2_NACK

#define _UART2_NACK ((uint8_t) (0x01 << 4))

UART2 Smartcard NACK enable [0] (in _UART2_CR5)

Definition at line 2032 of file STM8AF_STM8S.h.

◆ _UART2_NF

#define _UART2_NF ((uint8_t) (0x01 << 2))

UART2 Noise flag [0] (in _UART2_SR)

Definition at line 1978 of file STM8AF_STM8S.h.

◆ _UART2_OR_LHE

#define _UART2_OR_LHE ((uint8_t) (0x01 << 3))

UART2 LIN Header Error (LIN slave mode) / Overrun error [0] (in _UART2_SR)

Definition at line 1979 of file STM8AF_STM8S.h.

◆ _UART2_PCEN

#define _UART2_PCEN ((uint8_t) (0x01 << 2))

UART2 Parity control enable [0] (in _UART2_CR1)

Definition at line 1988 of file STM8AF_STM8S.h.

◆ _UART2_PE

#define _UART2_PE ((uint8_t) (0x01 << 0))

UART2 Parity error [0] (in _UART2_SR)

Definition at line 1976 of file STM8AF_STM8S.h.

◆ _UART2_PIEN

#define _UART2_PIEN ((uint8_t) (0x01 << 0))

UART2 Parity interrupt enable [0] (in _UART2_CR1)

Definition at line 1986 of file STM8AF_STM8S.h.

◆ _UART2_PS

#define _UART2_PS ((uint8_t) (0x01 << 1))

UART2 Parity selection [0] (in _UART2_CR1)

Definition at line 1987 of file STM8AF_STM8S.h.

◆ _UART2_PSCR

#define _UART2_PSCR _SFR(uint8_t, UART2_AddressBase+0x0B)

UART2 prescaler register.

Definition at line 1960 of file STM8AF_STM8S.h.

◆ _UART2_PSCR_RESET_VALUE

#define _UART2_PSCR_RESET_VALUE ((uint8_t) 0x00)

UART2 prescaler register reset value.

Definition at line 1973 of file STM8AF_STM8S.h.

◆ _UART2_R8

#define _UART2_R8 ((uint8_t) (0x01 << 7))

UART2 Receive Data bit 8 (in 9-bit mode) [0] (in _UART2_CR1)

Definition at line 1993 of file STM8AF_STM8S.h.

◆ _UART2_REN

#define _UART2_REN ((uint8_t) (0x01 << 2))

UART2 Receiver enable [0] (in _UART2_CR2)

Definition at line 1998 of file STM8AF_STM8S.h.

◆ _UART2_RIEN

#define _UART2_RIEN ((uint8_t) (0x01 << 5))

UART2 Receiver interrupt enable [0] (in _UART2_CR2)

Definition at line 2001 of file STM8AF_STM8S.h.

◆ _UART2_RWU

#define _UART2_RWU ((uint8_t) (0x01 << 1))

UART2 Receiver wakeup [0] (in _UART2_CR2)

Definition at line 1997 of file STM8AF_STM8S.h.

◆ _UART2_RXNE

#define _UART2_RXNE ((uint8_t) (0x01 << 5))

UART2 Read data register not empty [0] (in _UART2_SR)

Definition at line 1981 of file STM8AF_STM8S.h.

◆ _UART2_SBK

#define _UART2_SBK ((uint8_t) (0x01 << 0))

UART2 Send break [0] (in _UART2_CR2)

Definition at line 1996 of file STM8AF_STM8S.h.

◆ _UART2_SCEN

#define _UART2_SCEN ((uint8_t) (0x01 << 5))

UART2 Smartcard mode enable [0] (in _UART2_CR5)

Definition at line 2033 of file STM8AF_STM8S.h.

◆ _UART2_SR

#define _UART2_SR _SFR(uint8_t, UART2_AddressBase+0x00)

UART2 Status register.

Definition at line 1949 of file STM8AF_STM8S.h.

◆ _UART2_SR_RESET_VALUE

#define _UART2_SR_RESET_VALUE ((uint8_t) 0xC0)

UART2 Status register reset value.

Definition at line 1963 of file STM8AF_STM8S.h.

◆ _UART2_STOP

#define _UART2_STOP ((uint8_t) (0x03 << 4))

UART2 STOP bits [1:0] (in _UART2_CR3)

Definition at line 2010 of file STM8AF_STM8S.h.

◆ _UART2_STOP0

#define _UART2_STOP0 ((uint8_t) (0x01 << 4))

UART2 STOP bits [0] (in _UART2_CR3)

Definition at line 2011 of file STM8AF_STM8S.h.

◆ _UART2_STOP1

#define _UART2_STOP1 ((uint8_t) (0x01 << 5))

UART2 STOP bits [1] (in _UART2_CR3)

Definition at line 2012 of file STM8AF_STM8S.h.

◆ _UART2_T8

#define _UART2_T8 ((uint8_t) (0x01 << 6))

UART2 Transmit Data bit 8 (in 9-bit mode) [0] (in _UART2_CR1)

Definition at line 1992 of file STM8AF_STM8S.h.

◆ _UART2_TC

#define _UART2_TC ((uint8_t) (0x01 << 6))

UART2 Transmission complete [0] (in _UART2_SR)

Definition at line 1982 of file STM8AF_STM8S.h.

◆ _UART2_TCIEN

#define _UART2_TCIEN ((uint8_t) (0x01 << 6))

UART2 Transmission complete interrupt enable [0] (in _UART2_CR2)

Definition at line 2002 of file STM8AF_STM8S.h.

◆ _UART2_TEN

#define _UART2_TEN ((uint8_t) (0x01 << 3))

UART2 Transmitter enable [0] (in _UART2_CR2)

Definition at line 1999 of file STM8AF_STM8S.h.

◆ _UART2_TIEN

#define _UART2_TIEN ((uint8_t) (0x01 << 7))

UART2 Transmitter interrupt enable [0] (in _UART2_CR2)

Definition at line 2003 of file STM8AF_STM8S.h.

◆ _UART2_TXE

#define _UART2_TXE ((uint8_t) (0x01 << 7))

UART2 Transmit data register empty [0] (in _UART2_SR)

Definition at line 1983 of file STM8AF_STM8S.h.

◆ _UART2_UARTD

#define _UART2_UARTD ((uint8_t) (0x01 << 5))

UART2 Disable (for low power consumption) [0] (in _UART2_CR1)

Definition at line 1991 of file STM8AF_STM8S.h.

◆ _UART2_WAKE

#define _UART2_WAKE ((uint8_t) (0x01 << 3))

UART2 Wakeup method [0] (in _UART2_CR1)

Definition at line 1989 of file STM8AF_STM8S.h.

◆ _UART3

#define _UART3 _SFR(UART3_t, UART3_AddressBase)

UART3 struct/bit access.

Definition at line 2154 of file STM8AF_STM8S.h.

◆ _UART3_ADD

#define _UART3_ADD ((uint8_t) (0x0F << 0))

UART3 Address of the UART node [3:0] (in _UART3_CR4)

Definition at line 2215 of file STM8AF_STM8S.h.

◆ _UART3_ADD0

#define _UART3_ADD0 ((uint8_t) (0x01 << 0))

UART3 Address of the UART node [0] (in _UART3_CR4)

Definition at line 2216 of file STM8AF_STM8S.h.

◆ _UART3_ADD1

#define _UART3_ADD1 ((uint8_t) (0x01 << 1))

UART3 Address of the UART node [1] (in _UART3_CR4)

Definition at line 2217 of file STM8AF_STM8S.h.

◆ _UART3_ADD2

#define _UART3_ADD2 ((uint8_t) (0x01 << 2))

UART3 Address of the UART node [2] (in _UART3_CR4)

Definition at line 2218 of file STM8AF_STM8S.h.

◆ _UART3_ADD3

#define _UART3_ADD3 ((uint8_t) (0x01 << 3))

UART3 Address of the UART node [3] (in _UART3_CR4)

Definition at line 2219 of file STM8AF_STM8S.h.

◆ _UART3_BRR1

#define _UART3_BRR1 _SFR(uint8_t, UART3_AddressBase+0x02)

UART3 Baud rate register 1.

Definition at line 2157 of file STM8AF_STM8S.h.

◆ _UART3_BRR1_RESET_VALUE

#define _UART3_BRR1_RESET_VALUE ((uint8_t) 0x00)

UART3 Baud rate register 1 reset value.

Definition at line 2168 of file STM8AF_STM8S.h.

◆ _UART3_BRR2

#define _UART3_BRR2 _SFR(uint8_t, UART3_AddressBase+0x03)

UART3 Baud rate register 2.

Definition at line 2158 of file STM8AF_STM8S.h.

◆ _UART3_BRR2_RESET_VALUE

#define _UART3_BRR2_RESET_VALUE ((uint8_t) 0x00)

UART3 Baud rate register 2 reset value.

Definition at line 2169 of file STM8AF_STM8S.h.

◆ _UART3_CR1

#define _UART3_CR1 _SFR(uint8_t, UART3_AddressBase+0x04)

UART3 Control register 1.

Definition at line 2159 of file STM8AF_STM8S.h.

◆ _UART3_CR1_RESET_VALUE

#define _UART3_CR1_RESET_VALUE ((uint8_t) 0x00)

UART3 Control register 1 reset value.

Definition at line 2170 of file STM8AF_STM8S.h.

◆ _UART3_CR2

#define _UART3_CR2 _SFR(uint8_t, UART3_AddressBase+0x05)

UART3 Control register 2.

Definition at line 2160 of file STM8AF_STM8S.h.

◆ _UART3_CR2_RESET_VALUE

#define _UART3_CR2_RESET_VALUE ((uint8_t) 0x00)

UART3 Control register 2 reset value.

Definition at line 2171 of file STM8AF_STM8S.h.

◆ _UART3_CR3

#define _UART3_CR3 _SFR(uint8_t, UART3_AddressBase+0x06)

UART3 Control register 3.

Definition at line 2161 of file STM8AF_STM8S.h.

◆ _UART3_CR3_RESET_VALUE

#define _UART3_CR3_RESET_VALUE ((uint8_t) 0x00)

UART3 Control register 3 reset value.

Definition at line 2172 of file STM8AF_STM8S.h.

◆ _UART3_CR4

#define _UART3_CR4 _SFR(uint8_t, UART3_AddressBase+0x07)

UART3 Control register 4.

Definition at line 2162 of file STM8AF_STM8S.h.

◆ _UART3_CR4_RESET_VALUE

#define _UART3_CR4_RESET_VALUE ((uint8_t) 0x00)

UART3 Control register 4 reset value.

Definition at line 2173 of file STM8AF_STM8S.h.

◆ _UART3_CR6

#define _UART3_CR6 _SFR(uint8_t, UART3_AddressBase+0x09)

UART3 Control register 6.

Definition at line 2164 of file STM8AF_STM8S.h.

◆ _UART3_CR6_RESET_VALUE

#define _UART3_CR6_RESET_VALUE ((uint8_t) 0x00)

UART3 Control register 6 reset value.

Definition at line 2174 of file STM8AF_STM8S.h.

◆ _UART3_DR

#define _UART3_DR _SFR(uint8_t, UART3_AddressBase+0x01)

UART3 data register.

Definition at line 2156 of file STM8AF_STM8S.h.

◆ _UART3_FE

#define _UART3_FE ((uint8_t) (0x01 << 1))

UART3 Framing error [0] (in _UART3_SR)

Definition at line 2178 of file STM8AF_STM8S.h.

◆ _UART3_IDLE

#define _UART3_IDLE ((uint8_t) (0x01 << 4))

UART3 IDLE line detected [0] (in _UART3_SR)

Definition at line 2181 of file STM8AF_STM8S.h.

◆ _UART3_ILIEN

#define _UART3_ILIEN ((uint8_t) (0x01 << 4))

UART3 IDLE Line interrupt enable [0] (in _UART3_CR2)

Definition at line 2201 of file STM8AF_STM8S.h.

◆ _UART3_LASE

#define _UART3_LASE ((uint8_t) (0x01 << 4))

UART3 LIN automatic resynchronisation enable [0] (in _UART3_CR6)

Definition at line 2230 of file STM8AF_STM8S.h.

◆ _UART3_LBDF

#define _UART3_LBDF ((uint8_t) (0x01 << 4))

UART3 LIN Break Detection Flag [0] (in _UART3_CR4)

Definition at line 2220 of file STM8AF_STM8S.h.

◆ _UART3_LBDIEN

#define _UART3_LBDIEN ((uint8_t) (0x01 << 6))

UART3 LIN Break Detection Interrupt Enable [0] (in _UART3_CR4)

Definition at line 2222 of file STM8AF_STM8S.h.

◆ _UART3_LBDL

#define _UART3_LBDL ((uint8_t) (0x01 << 5))

UART3 LIN Break Detection Length [0] (in _UART3_CR4)

Definition at line 2221 of file STM8AF_STM8S.h.

◆ _UART3_LDUM

#define _UART3_LDUM ((uint8_t) (0x01 << 7))

UART3 LIN Divider Update Method [0] (in _UART3_CR6)

Definition at line 2233 of file STM8AF_STM8S.h.

◆ _UART3_LHDF

#define _UART3_LHDF ((uint8_t) (0x01 << 1))

UART3 LIN Header Detection Flag [0] (in _UART3_CR6)

Definition at line 2227 of file STM8AF_STM8S.h.

◆ _UART3_LHDIEN

#define _UART3_LHDIEN ((uint8_t) (0x01 << 2))

UART3 LIN Header Detection Interrupt Enable [0] (in _UART3_CR6)

Definition at line 2228 of file STM8AF_STM8S.h.

◆ _UART3_LINEN

#define _UART3_LINEN ((uint8_t) (0x01 << 6))

UART3 LIN mode enable [0] (in _UART3_CR3)

Definition at line 2211 of file STM8AF_STM8S.h.

◆ _UART3_LSF

#define _UART3_LSF ((uint8_t) (0x01 << 0))

UART3 LIN Sync Field [0] (in _UART3_CR6)

Definition at line 2226 of file STM8AF_STM8S.h.

◆ _UART3_LSLV

#define _UART3_LSLV ((uint8_t) (0x01 << 5))

UART3 LIN Slave Enable [0] (in _UART3_CR6)

Definition at line 2231 of file STM8AF_STM8S.h.

◆ _UART3_M

#define _UART3_M ((uint8_t) (0x01 << 4))

UART3 word length [0] (in _UART3_CR1)

Definition at line 2191 of file STM8AF_STM8S.h.

◆ _UART3_NF

#define _UART3_NF ((uint8_t) (0x01 << 2))

UART3 Noise flag [0] (in _UART3_SR)

Definition at line 2179 of file STM8AF_STM8S.h.

◆ _UART3_OR_LHE

#define _UART3_OR_LHE ((uint8_t) (0x01 << 3))

UART3 LIN Header Error (LIN slave mode) / Overrun error [0] (in _UART3_SR)

Definition at line 2180 of file STM8AF_STM8S.h.

◆ _UART3_PCEN

#define _UART3_PCEN ((uint8_t) (0x01 << 2))

UART3 Parity control enable [0] (in _UART3_CR1)

Definition at line 2189 of file STM8AF_STM8S.h.

◆ _UART3_PE

#define _UART3_PE ((uint8_t) (0x01 << 0))

UART3 Parity error [0] (in _UART3_SR)

Definition at line 2177 of file STM8AF_STM8S.h.

◆ _UART3_PIEN

#define _UART3_PIEN ((uint8_t) (0x01 << 0))

UART3 Parity interrupt enable [0] (in _UART3_CR1)

Definition at line 2187 of file STM8AF_STM8S.h.

◆ _UART3_PS

#define _UART3_PS ((uint8_t) (0x01 << 1))

UART3 Parity selection [0] (in _UART3_CR1)

Definition at line 2188 of file STM8AF_STM8S.h.

◆ _UART3_R8

#define _UART3_R8 ((uint8_t) (0x01 << 7))

UART3 Receive Data bit 8 (in 9-bit mode) [0] (in _UART3_CR1)

Definition at line 2194 of file STM8AF_STM8S.h.

◆ _UART3_REN

#define _UART3_REN ((uint8_t) (0x01 << 2))

UART3 Receiver enable [0] (in _UART3_CR2)

Definition at line 2199 of file STM8AF_STM8S.h.

◆ _UART3_RIEN

#define _UART3_RIEN ((uint8_t) (0x01 << 5))

UART3 Receiver interrupt enable [0] (in _UART3_CR2)

Definition at line 2202 of file STM8AF_STM8S.h.

◆ _UART3_RWU

#define _UART3_RWU ((uint8_t) (0x01 << 1))

UART3 Receiver wakeup [0] (in _UART3_CR2)

Definition at line 2198 of file STM8AF_STM8S.h.

◆ _UART3_RXNE

#define _UART3_RXNE ((uint8_t) (0x01 << 5))

UART3 Read data register not empty [0] (in _UART3_SR)

Definition at line 2182 of file STM8AF_STM8S.h.

◆ _UART3_SBK

#define _UART3_SBK ((uint8_t) (0x01 << 0))

UART3 Send break [0] (in _UART3_CR2)

Definition at line 2197 of file STM8AF_STM8S.h.

◆ _UART3_SR

#define _UART3_SR _SFR(uint8_t, UART3_AddressBase+0x00)

UART3 Status register.

Definition at line 2155 of file STM8AF_STM8S.h.

◆ _UART3_SR_RESET_VALUE

#define _UART3_SR_RESET_VALUE ((uint8_t) 0xC0)

UART3 Status register reset value.

Definition at line 2167 of file STM8AF_STM8S.h.

◆ _UART3_STOP

#define _UART3_STOP ((uint8_t) (0x03 << 4))

UART3 STOP bits [1:0] (in _UART3_CR3)

Definition at line 2208 of file STM8AF_STM8S.h.

◆ _UART3_STOP0

#define _UART3_STOP0 ((uint8_t) (0x01 << 4))

UART3 STOP bits [0] (in _UART3_CR3)

Definition at line 2209 of file STM8AF_STM8S.h.

◆ _UART3_STOP1

#define _UART3_STOP1 ((uint8_t) (0x01 << 5))

UART3 STOP bits [1] (in _UART3_CR3)

Definition at line 2210 of file STM8AF_STM8S.h.

◆ _UART3_T8

#define _UART3_T8 ((uint8_t) (0x01 << 6))

UART3 Transmit Data bit 8 (in 9-bit mode) [0] (in _UART3_CR1)

Definition at line 2193 of file STM8AF_STM8S.h.

◆ _UART3_TC

#define _UART3_TC ((uint8_t) (0x01 << 6))

UART3 Transmission complete [0] (in _UART3_SR)

Definition at line 2183 of file STM8AF_STM8S.h.

◆ _UART3_TCIEN

#define _UART3_TCIEN ((uint8_t) (0x01 << 6))

UART3 Transmission complete interrupt enable [0] (in _UART3_CR2)

Definition at line 2203 of file STM8AF_STM8S.h.

◆ _UART3_TEN

#define _UART3_TEN ((uint8_t) (0x01 << 3))

UART3 Transmitter enable [0] (in _UART3_CR2)

Definition at line 2200 of file STM8AF_STM8S.h.

◆ _UART3_TIEN

#define _UART3_TIEN ((uint8_t) (0x01 << 7))

UART3 Transmitter interrupt enable [0] (in _UART3_CR2)

Definition at line 2204 of file STM8AF_STM8S.h.

◆ _UART3_TXE

#define _UART3_TXE ((uint8_t) (0x01 << 7))

UART3 Transmit data register empty [0] (in _UART3_SR)

Definition at line 2184 of file STM8AF_STM8S.h.

◆ _UART3_UARTD

#define _UART3_UARTD ((uint8_t) (0x01 << 5))

UART3 Disable (for low power consumption) [0] (in _UART3_CR1)

Definition at line 2192 of file STM8AF_STM8S.h.

◆ _UART3_WAKE

#define _UART3_WAKE ((uint8_t) (0x01 << 3))

UART3 Wakeup method [0] (in _UART3_CR1)

Definition at line 2190 of file STM8AF_STM8S.h.

◆ _UART4

#define _UART4 _SFR(UART4_t, UART4_AddressBase)

UART4 struct/bit access.

Definition at line 2366 of file STM8AF_STM8S.h.

◆ _UART4_ADD

#define _UART4_ADD ((uint8_t) (0x0F << 0))

UART4 Address of the UART node [3:0] (in _UART4_CR4)

Definition at line 2435 of file STM8AF_STM8S.h.

◆ _UART4_ADD0

#define _UART4_ADD0 ((uint8_t) (0x01 << 0))

UART4 Address of the UART node [0] (in _UART4_CR4)

Definition at line 2436 of file STM8AF_STM8S.h.

◆ _UART4_ADD1

#define _UART4_ADD1 ((uint8_t) (0x01 << 1))

UART4 Address of the UART node [1] (in _UART4_CR4)

Definition at line 2437 of file STM8AF_STM8S.h.

◆ _UART4_ADD2

#define _UART4_ADD2 ((uint8_t) (0x01 << 2))

UART4 Address of the UART node [2] (in _UART4_CR4)

Definition at line 2438 of file STM8AF_STM8S.h.

◆ _UART4_ADD3

#define _UART4_ADD3 ((uint8_t) (0x01 << 3))

UART4 Address of the UART node [3] (in _UART4_CR4)

Definition at line 2439 of file STM8AF_STM8S.h.

◆ _UART4_BRR1

#define _UART4_BRR1 _SFR(uint8_t, UART4_AddressBase+0x02)

UART4 Baud rate register 1.

Definition at line 2369 of file STM8AF_STM8S.h.

◆ _UART4_BRR1_RESET_VALUE

#define _UART4_BRR1_RESET_VALUE ((uint8_t) 0x00)

UART4 Baud rate register 1 reset value.

Definition at line 2382 of file STM8AF_STM8S.h.

◆ _UART4_BRR2

#define _UART4_BRR2 _SFR(uint8_t, UART4_AddressBase+0x03)

UART4 Baud rate register 2.

Definition at line 2370 of file STM8AF_STM8S.h.

◆ _UART4_BRR2_RESET_VALUE

#define _UART4_BRR2_RESET_VALUE ((uint8_t) 0x00)

UART4 Baud rate register 2 reset value.

Definition at line 2383 of file STM8AF_STM8S.h.

◆ _UART4_CKEN

#define _UART4_CKEN ((uint8_t) (0x01 << 3))

UART4 Clock enable [0] (in _UART4_CR3)

Definition at line 2427 of file STM8AF_STM8S.h.

◆ _UART4_CPHA

#define _UART4_CPHA ((uint8_t) (0x01 << 1))

UART4 Clock phase [0] (in _UART4_CR3)

Definition at line 2425 of file STM8AF_STM8S.h.

◆ _UART4_CPOL

#define _UART4_CPOL ((uint8_t) (0x01 << 2))

UART4 Clock polarity [0] (in _UART4_CR3)

Definition at line 2426 of file STM8AF_STM8S.h.

◆ _UART4_CR1

#define _UART4_CR1 _SFR(uint8_t, UART4_AddressBase+0x04)

UART4 Control register 1.

Definition at line 2371 of file STM8AF_STM8S.h.

◆ _UART4_CR1_RESET_VALUE

#define _UART4_CR1_RESET_VALUE ((uint8_t) 0x00)

UART4 Control register 1 reset value.

Definition at line 2384 of file STM8AF_STM8S.h.

◆ _UART4_CR2

#define _UART4_CR2 _SFR(uint8_t, UART4_AddressBase+0x05)

UART4 Control register 2.

Definition at line 2372 of file STM8AF_STM8S.h.

◆ _UART4_CR2_RESET_VALUE

#define _UART4_CR2_RESET_VALUE ((uint8_t) 0x00)

UART4 Control register 2 reset value.

Definition at line 2385 of file STM8AF_STM8S.h.

◆ _UART4_CR3

#define _UART4_CR3 _SFR(uint8_t, UART4_AddressBase+0x06)

UART4 Control register 3.

Definition at line 2373 of file STM8AF_STM8S.h.

◆ _UART4_CR3_RESET_VALUE

#define _UART4_CR3_RESET_VALUE ((uint8_t) 0x00)

UART4 Control register 3 reset value.

Definition at line 2386 of file STM8AF_STM8S.h.

◆ _UART4_CR4

#define _UART4_CR4 _SFR(uint8_t, UART4_AddressBase+0x07)

UART4 Control register 4.

Definition at line 2374 of file STM8AF_STM8S.h.

◆ _UART4_CR4_RESET_VALUE

#define _UART4_CR4_RESET_VALUE ((uint8_t) 0x00)

UART4 Control register 4 reset value.

Definition at line 2387 of file STM8AF_STM8S.h.

◆ _UART4_CR5

#define _UART4_CR5 _SFR(uint8_t, UART4_AddressBase+0x08)

UART4 Control register 5.

Definition at line 2375 of file STM8AF_STM8S.h.

◆ _UART4_CR5_RESET_VALUE

#define _UART4_CR5_RESET_VALUE ((uint8_t) 0x00)

UART4 Control register 5 reset value.

Definition at line 2388 of file STM8AF_STM8S.h.

◆ _UART4_CR6

#define _UART4_CR6 _SFR(uint8_t, UART4_AddressBase+0x09)

UART4 Control register 6.

Definition at line 2376 of file STM8AF_STM8S.h.

◆ _UART4_CR6_RESET_VALUE

#define _UART4_CR6_RESET_VALUE ((uint8_t) 0x00)

UART4 Control register 6 reset value.

Definition at line 2389 of file STM8AF_STM8S.h.

◆ _UART4_DR

#define _UART4_DR _SFR(uint8_t, UART4_AddressBase+0x01)

UART4 data register.

Definition at line 2368 of file STM8AF_STM8S.h.

◆ _UART4_FE

#define _UART4_FE ((uint8_t) (0x01 << 1))

UART4 Framing error [0] (in _UART4_SR)

Definition at line 2395 of file STM8AF_STM8S.h.

◆ _UART4_GTR

#define _UART4_GTR _SFR(uint8_t, UART4_AddressBase+0x0A)

UART4 guard time register.

Definition at line 2377 of file STM8AF_STM8S.h.

◆ _UART4_GTR_RESET_VALUE

#define _UART4_GTR_RESET_VALUE ((uint8_t) 0x00)

UART4 guard time register reset value.

Definition at line 2390 of file STM8AF_STM8S.h.

◆ _UART4_HDSEL

#define _UART4_HDSEL ((uint8_t) (0x01 << 3))

UART4 Half-Duplex Selection [0] (in _UART4_CR5)

Definition at line 2449 of file STM8AF_STM8S.h.

◆ _UART4_IDLE

#define _UART4_IDLE ((uint8_t) (0x01 << 4))

UART4 IDLE line detected [0] (in _UART4_SR)

Definition at line 2398 of file STM8AF_STM8S.h.

◆ _UART4_ILIEN

#define _UART4_ILIEN ((uint8_t) (0x01 << 4))

UART4 IDLE Line interrupt enable [0] (in _UART4_CR2)

Definition at line 2418 of file STM8AF_STM8S.h.

◆ _UART4_IREN

#define _UART4_IREN ((uint8_t) (0x01 << 1))

UART4 IrDA mode Enable [0] (in _UART4_CR5)

Definition at line 2447 of file STM8AF_STM8S.h.

◆ _UART4_IRLP

#define _UART4_IRLP ((uint8_t) (0x01 << 2))

UART4 IrDA Low Power [0] (in _UART4_CR5)

Definition at line 2448 of file STM8AF_STM8S.h.

◆ _UART4_LASE

#define _UART4_LASE ((uint8_t) (0x01 << 4))

UART4 LIN automatic resynchronisation enable [0] (in _UART4_CR6)

Definition at line 2459 of file STM8AF_STM8S.h.

◆ _UART4_LBCL

#define _UART4_LBCL ((uint8_t) (0x01 << 0))

UART4 Last bit clock pulse [0] (in _UART4_CR3)

Definition at line 2424 of file STM8AF_STM8S.h.

◆ _UART4_LBDF

#define _UART4_LBDF ((uint8_t) (0x01 << 4))

UART4 LIN Break Detection Flag [0] (in _UART4_CR4)

Definition at line 2440 of file STM8AF_STM8S.h.

◆ _UART4_LBDIEN

#define _UART4_LBDIEN ((uint8_t) (0x01 << 6))

UART4 LIN Break Detection Interrupt Enable [0] (in _UART4_CR4)

Definition at line 2442 of file STM8AF_STM8S.h.

◆ _UART4_LBDL

#define _UART4_LBDL ((uint8_t) (0x01 << 5))

UART4 LIN Break Detection Length [0] (in _UART4_CR4)

Definition at line 2441 of file STM8AF_STM8S.h.

◆ _UART4_LDUM

#define _UART4_LDUM ((uint8_t) (0x01 << 7))

UART4 LIN Divider Update Method [0] (in _UART4_CR6)

Definition at line 2462 of file STM8AF_STM8S.h.

◆ _UART4_LHDF

#define _UART4_LHDF ((uint8_t) (0x01 << 1))

UART4 LIN Header Detection Flag [0] (in _UART4_CR6)

Definition at line 2456 of file STM8AF_STM8S.h.

◆ _UART4_LHDIEN

#define _UART4_LHDIEN ((uint8_t) (0x01 << 2))

UART4 LIN Header Detection Interrupt Enable [0] (in _UART4_CR6)

Definition at line 2457 of file STM8AF_STM8S.h.

◆ _UART4_LINEN

#define _UART4_LINEN ((uint8_t) (0x01 << 6))

UART4 LIN mode enable [0] (in _UART4_CR3)

Definition at line 2431 of file STM8AF_STM8S.h.

◆ _UART4_LSF

#define _UART4_LSF ((uint8_t) (0x01 << 0))

UART4 LIN Sync Field [0] (in _UART4_CR6)

Definition at line 2455 of file STM8AF_STM8S.h.

◆ _UART4_LSLV

#define _UART4_LSLV ((uint8_t) (0x01 << 5))

UART4 LIN Slave Enable [0] (in _UART4_CR6)

Definition at line 2460 of file STM8AF_STM8S.h.

◆ _UART4_M

#define _UART4_M ((uint8_t) (0x01 << 4))

UART4 word length [0] (in _UART4_CR1)

Definition at line 2408 of file STM8AF_STM8S.h.

◆ _UART4_NACK

#define _UART4_NACK ((uint8_t) (0x01 << 4))

UART4 Smartcard NACK enable [0] (in _UART4_CR5)

Definition at line 2450 of file STM8AF_STM8S.h.

◆ _UART4_NF

#define _UART4_NF ((uint8_t) (0x01 << 2))

UART4 Noise flag [0] (in _UART4_SR)

Definition at line 2396 of file STM8AF_STM8S.h.

◆ _UART4_OR_LHE

#define _UART4_OR_LHE ((uint8_t) (0x01 << 3))

UART4 LIN Header Error (LIN slave mode) / Overrun error [0] (in _UART4_SR)

Definition at line 2397 of file STM8AF_STM8S.h.

◆ _UART4_PCEN

#define _UART4_PCEN ((uint8_t) (0x01 << 2))

UART4 Parity control enable [0] (in _UART4_CR1)

Definition at line 2406 of file STM8AF_STM8S.h.

◆ _UART4_PE

#define _UART4_PE ((uint8_t) (0x01 << 0))

UART4 Parity error [0] (in _UART4_SR)

Definition at line 2394 of file STM8AF_STM8S.h.

◆ _UART4_PIEN

#define _UART4_PIEN ((uint8_t) (0x01 << 0))

UART4 Parity interrupt enable [0] (in _UART4_CR1)

Definition at line 2404 of file STM8AF_STM8S.h.

◆ _UART4_PS

#define _UART4_PS ((uint8_t) (0x01 << 1))

UART4 Parity selection [0] (in _UART4_CR1)

Definition at line 2405 of file STM8AF_STM8S.h.

◆ _UART4_PSCR

#define _UART4_PSCR _SFR(uint8_t, UART4_AddressBase+0x0B)

UART4 prescaler register.

Definition at line 2378 of file STM8AF_STM8S.h.

◆ _UART4_PSCR_RESET_VALUE

#define _UART4_PSCR_RESET_VALUE ((uint8_t) 0x00)

UART4 prescaler register reset value.

Definition at line 2391 of file STM8AF_STM8S.h.

◆ _UART4_R8

#define _UART4_R8 ((uint8_t) (0x01 << 7))

UART4 Receive Data bit 8 (in 9-bit mode) [0] (in _UART4_CR1)

Definition at line 2411 of file STM8AF_STM8S.h.

◆ _UART4_REN

#define _UART4_REN ((uint8_t) (0x01 << 2))

UART4 Receiver enable [0] (in _UART4_CR2)

Definition at line 2416 of file STM8AF_STM8S.h.

◆ _UART4_RIEN

#define _UART4_RIEN ((uint8_t) (0x01 << 5))

UART4 Receiver interrupt enable [0] (in _UART4_CR2)

Definition at line 2419 of file STM8AF_STM8S.h.

◆ _UART4_RWU

#define _UART4_RWU ((uint8_t) (0x01 << 1))

UART4 Receiver wakeup [0] (in _UART4_CR2)

Definition at line 2415 of file STM8AF_STM8S.h.

◆ _UART4_RXNE

#define _UART4_RXNE ((uint8_t) (0x01 << 5))

UART4 Read data register not empty [0] (in _UART4_SR)

Definition at line 2399 of file STM8AF_STM8S.h.

◆ _UART4_SBK

#define _UART4_SBK ((uint8_t) (0x01 << 0))

UART4 Send break [0] (in _UART4_CR2)

Definition at line 2414 of file STM8AF_STM8S.h.

◆ _UART4_SCEN

#define _UART4_SCEN ((uint8_t) (0x01 << 5))

UART4 Smartcard mode enable [0] (in _UART4_CR5)

Definition at line 2451 of file STM8AF_STM8S.h.

◆ _UART4_SR

#define _UART4_SR _SFR(uint8_t, UART4_AddressBase+0x00)

UART4 Status register.

Definition at line 2367 of file STM8AF_STM8S.h.

◆ _UART4_SR_RESET_VALUE

#define _UART4_SR_RESET_VALUE ((uint8_t) 0xC0)

UART4 Status register reset value.

Definition at line 2381 of file STM8AF_STM8S.h.

◆ _UART4_STOP

#define _UART4_STOP ((uint8_t) (0x03 << 4))

UART4 STOP bits [1:0] (in _UART4_CR3)

Definition at line 2428 of file STM8AF_STM8S.h.

◆ _UART4_STOP0

#define _UART4_STOP0 ((uint8_t) (0x01 << 4))

UART4 STOP bits [0] (in _UART4_CR3)

Definition at line 2429 of file STM8AF_STM8S.h.

◆ _UART4_STOP1

#define _UART4_STOP1 ((uint8_t) (0x01 << 5))

UART4 STOP bits [1] (in _UART4_CR3)

Definition at line 2430 of file STM8AF_STM8S.h.

◆ _UART4_T8

#define _UART4_T8 ((uint8_t) (0x01 << 6))

UART4 Transmit Data bit 8 (in 9-bit mode) [0] (in _UART4_CR1)

Definition at line 2410 of file STM8AF_STM8S.h.

◆ _UART4_TC

#define _UART4_TC ((uint8_t) (0x01 << 6))

UART4 Transmission complete [0] (in _UART4_SR)

Definition at line 2400 of file STM8AF_STM8S.h.

◆ _UART4_TCIEN

#define _UART4_TCIEN ((uint8_t) (0x01 << 6))

UART4 Transmission complete interrupt enable [0] (in _UART4_CR2)

Definition at line 2420 of file STM8AF_STM8S.h.

◆ _UART4_TEN

#define _UART4_TEN ((uint8_t) (0x01 << 3))

UART4 Transmitter enable [0] (in _UART4_CR2)

Definition at line 2417 of file STM8AF_STM8S.h.

◆ _UART4_TIEN

#define _UART4_TIEN ((uint8_t) (0x01 << 7))

UART4 Transmitter interrupt enable [0] (in _UART4_CR2)

Definition at line 2421 of file STM8AF_STM8S.h.

◆ _UART4_TXE

#define _UART4_TXE ((uint8_t) (0x01 << 7))

UART4 Transmit data register empty [0] (in _UART4_SR)

Definition at line 2401 of file STM8AF_STM8S.h.

◆ _UART4_UARTD

#define _UART4_UARTD ((uint8_t) (0x01 << 5))

UART4 Disable (for low power consumption) [0] (in _UART4_CR1)

Definition at line 2409 of file STM8AF_STM8S.h.

◆ _UART4_WAKE

#define _UART4_WAKE ((uint8_t) (0x01 << 3))

UART4 Wakeup method [0] (in _UART4_CR1)

Definition at line 2407 of file STM8AF_STM8S.h.

◆ _WWDG

#define _WWDG _SFR(WWDG_t, WWDG_AddressBase)

Window Watchdog struct/bit access.

Definition at line 1006 of file STM8AF_STM8S.h.

◆ _WWDG_CR

#define _WWDG_CR _SFR(uint8_t, WWDG_AddressBase+0x00)

Window Watchdog Control register (WWDG_CR)

Definition at line 1007 of file STM8AF_STM8S.h.

◆ _WWDG_CR_RESET_VALUE

#define _WWDG_CR_RESET_VALUE ((uint8_t) 0x7F)

Window Watchdog Control register reset value.

Definition at line 1011 of file STM8AF_STM8S.h.

◆ _WWDG_T

#define _WWDG_T ((uint8_t) (0x7F << 0))

Window Watchdog 7-bit counter [6:0] (in _WWDG_CR)

Definition at line 1015 of file STM8AF_STM8S.h.

◆ _WWDG_T0

#define _WWDG_T0 ((uint8_t) (0x01 << 0))

Window Watchdog 7-bit counter [0] (in _WWDG_CR)

Definition at line 1016 of file STM8AF_STM8S.h.

◆ _WWDG_T1

#define _WWDG_T1 ((uint8_t) (0x01 << 1))

Window Watchdog 7-bit counter [1] (in _WWDG_CR)

Definition at line 1017 of file STM8AF_STM8S.h.

◆ _WWDG_T2

#define _WWDG_T2 ((uint8_t) (0x01 << 2))

Window Watchdog 7-bit counter [2] (in _WWDG_CR)

Definition at line 1018 of file STM8AF_STM8S.h.

◆ _WWDG_T3

#define _WWDG_T3 ((uint8_t) (0x01 << 3))

Window Watchdog 7-bit counter [3] (in _WWDG_CR)

Definition at line 1019 of file STM8AF_STM8S.h.

◆ _WWDG_T4

#define _WWDG_T4 ((uint8_t) (0x01 << 4))

Window Watchdog 7-bit counter [4] (in _WWDG_CR)

Definition at line 1020 of file STM8AF_STM8S.h.

◆ _WWDG_T5

#define _WWDG_T5 ((uint8_t) (0x01 << 5))

Window Watchdog 7-bit counter [5] (in _WWDG_CR)

Definition at line 1021 of file STM8AF_STM8S.h.

◆ _WWDG_T6

#define _WWDG_T6 ((uint8_t) (0x01 << 6))

Window Watchdog 7-bit counter [6] (in _WWDG_CR)

Definition at line 1022 of file STM8AF_STM8S.h.

◆ _WWDG_W

#define _WWDG_W ((uint8_t) (0x7F << 0))

Window Watchdog 7-bit window value [6:0] (in _WWDG_WR)

Definition at line 1026 of file STM8AF_STM8S.h.

◆ _WWDG_W0

#define _WWDG_W0 ((uint8_t) (0x01 << 0))

Window Watchdog 7-bit window value [0] (in _WWDG_WR)

Definition at line 1027 of file STM8AF_STM8S.h.

◆ _WWDG_W1

#define _WWDG_W1 ((uint8_t) (0x01 << 1))

Window Watchdog 7-bit window value [1] (in _WWDG_WR)

Definition at line 1028 of file STM8AF_STM8S.h.

◆ _WWDG_W2

#define _WWDG_W2 ((uint8_t) (0x01 << 2))

Window Watchdog 7-bit window value [2] (in _WWDG_WR)

Definition at line 1029 of file STM8AF_STM8S.h.

◆ _WWDG_W3

#define _WWDG_W3 ((uint8_t) (0x01 << 3))

Window Watchdog 7-bit window value [3] (in _WWDG_WR)

Definition at line 1030 of file STM8AF_STM8S.h.

◆ _WWDG_W4

#define _WWDG_W4 ((uint8_t) (0x01 << 4))

Window Watchdog 7-bit window value [4] (in _WWDG_WR)

Definition at line 1031 of file STM8AF_STM8S.h.

◆ _WWDG_W5

#define _WWDG_W5 ((uint8_t) (0x01 << 5))

Window Watchdog 7-bit window value [5] (in _WWDG_WR)

Definition at line 1032 of file STM8AF_STM8S.h.

◆ _WWDG_W6

#define _WWDG_W6 ((uint8_t) (0x01 << 6))

Window Watchdog 7-bit window value [6] (in _WWDG_WR)

Definition at line 1033 of file STM8AF_STM8S.h.

◆ _WWDG_WDGA

#define _WWDG_WDGA ((uint8_t) (0x01 << 7))

Window Watchdog activation bit (n/a if WWDG enabled by option byte) [0] (in _WWDG_CR)

Definition at line 1023 of file STM8AF_STM8S.h.

◆ _WWDG_WR

#define _WWDG_WR _SFR(uint8_t, WWDG_AddressBase+0x01)

Window Watchdog Window register (WWDG_WR)

Definition at line 1008 of file STM8AF_STM8S.h.

◆ _WWDG_WR_RESET_VALUE

#define _WWDG_WR_RESET_VALUE ((uint8_t) 0x7F)

Window Watchdog Window register reset value.

Definition at line 1012 of file STM8AF_STM8S.h.

◆ ADC1_AddressBase [1/27]

#define ADC1_AddressBase 0x53E0

Definition at line 73 of file STM8AF6213.h.

◆ ADC1_AddressBase [2/27]

#define ADC1_AddressBase 0x53E0

Definition at line 73 of file STM8S903F3.h.

◆ ADC1_AddressBase [3/27]

#define ADC1_AddressBase 0x53E0

Definition at line 73 of file STM8S903K3.h.

◆ ADC1_AddressBase [4/27]

#define ADC1_AddressBase 0x53E0

Definition at line 73 of file STM8S001J3.h.

◆ ADC1_AddressBase [5/27]

#define ADC1_AddressBase 0x53E0

Definition at line 73 of file STM8S003F3.h.

◆ ADC1_AddressBase [6/27]

#define ADC1_AddressBase 0x53E0

Definition at line 73 of file STM8S003K3.h.

◆ ADC1_AddressBase [7/27]

#define ADC1_AddressBase 0x53E0

Definition at line 73 of file STM8S103F2.h.

◆ ADC1_AddressBase [8/27]

#define ADC1_AddressBase 0x53E0

Definition at line 73 of file STM8AF6213A.h.

◆ ADC1_AddressBase [9/27]

#define ADC1_AddressBase 0x53E0

Definition at line 73 of file STM8AF6223.h.

◆ ADC1_AddressBase [10/27]

#define ADC1_AddressBase 0x53E0

Definition at line 73 of file STM8S103F3.h.

◆ ADC1_AddressBase [11/27]

#define ADC1_AddressBase 0x53E0

Definition at line 73 of file STM8AF6223A.h.

◆ ADC1_AddressBase [12/27]

#define ADC1_AddressBase 0x53E0

Definition at line 73 of file STM8AF6226.h.

◆ ADC1_AddressBase [13/27]

#define ADC1_AddressBase 0x53E0

Definition at line 73 of file STM8S103K3.h.

◆ ADC1_AddressBase [14/27]

#define ADC1_AddressBase 0x53E0

Definition at line 74 of file STM8AF6366.h.

◆ ADC1_AddressBase [15/27]

#define ADC1_AddressBase 0x53E0

Definition at line 75 of file STM8AF6246.h.

◆ ADC1_AddressBase [16/27]

#define ADC1_AddressBase 0x53E0

Definition at line 75 of file STM8AF6248.h.

◆ ADC1_AddressBase [17/27]

#define ADC1_AddressBase 0x53E0

Definition at line 75 of file STM8AF6266.h.

◆ ADC1_AddressBase [18/27]

#define ADC1_AddressBase 0x53E0

Definition at line 75 of file STM8AF6268.h.

◆ ADC1_AddressBase [19/27]

#define ADC1_AddressBase 0x53E0

Definition at line 75 of file STM8AF6269.h.

◆ ADC1_AddressBase [20/27]

#define ADC1_AddressBase 0x53E0

Definition at line 75 of file STM8S005C6.h.

◆ ADC1_AddressBase [21/27]

#define ADC1_AddressBase 0x53E0

Definition at line 75 of file STM8S005K6.h.

◆ ADC1_AddressBase [22/27]

#define ADC1_AddressBase 0x53E0

Definition at line 75 of file STM8S105C4.h.

◆ ADC1_AddressBase [23/27]

#define ADC1_AddressBase 0x53E0

Definition at line 75 of file STM8S105C6.h.

◆ ADC1_AddressBase [24/27]

#define ADC1_AddressBase 0x53E0

Definition at line 75 of file STM8S105K4.h.

◆ ADC1_AddressBase [25/27]

#define ADC1_AddressBase 0x53E0

Definition at line 75 of file STM8S105K6.h.

◆ ADC1_AddressBase [26/27]

#define ADC1_AddressBase 0x53E0

Definition at line 75 of file STM8S105S4.h.

◆ ADC1_AddressBase [27/27]

#define ADC1_AddressBase 0x53E0

Definition at line 75 of file STM8S105S6.h.

◆ ADC2_AddressBase [1/43]

#define ADC2_AddressBase 0x5400

Definition at line 78 of file STM8AF5269.h.

◆ ADC2_AddressBase [2/43]

#define ADC2_AddressBase 0x5400

Definition at line 78 of file STM8S208S8.h.

◆ ADC2_AddressBase [3/43]

#define ADC2_AddressBase 0x5400

Definition at line 78 of file STM8AF52A8.h.

◆ ADC2_AddressBase [4/43]

#define ADC2_AddressBase 0x5400

Definition at line 78 of file STM8S208SB.h.

◆ ADC2_AddressBase [5/43]

#define ADC2_AddressBase 0x5400

Definition at line 78 of file STM8AF5288.h.

◆ ADC2_AddressBase [6/43]

#define ADC2_AddressBase 0x5400

Definition at line 78 of file STM8S208R8.h.

◆ ADC2_AddressBase [7/43]

#define ADC2_AddressBase 0x5400

Definition at line 78 of file STM8AF52A9.h.

◆ ADC2_AddressBase [8/43]

#define ADC2_AddressBase 0x5400

Definition at line 78 of file STM8AF5289.h.

◆ ADC2_AddressBase [9/43]

#define ADC2_AddressBase 0x5400

Definition at line 78 of file STM8S208CB.h.

◆ ADC2_AddressBase [10/43]

#define ADC2_AddressBase 0x5400

Definition at line 78 of file STM8AF6286.h.

◆ ADC2_AddressBase [11/43]

#define ADC2_AddressBase 0x5400

Definition at line 78 of file STM8AF52AA.h.

◆ ADC2_AddressBase [12/43]

#define ADC2_AddressBase 0x5400

Definition at line 78 of file STM8AF6288.h.

◆ ADC2_AddressBase [13/43]

#define ADC2_AddressBase 0x5400

Definition at line 78 of file STM8S007C8.h.

◆ ADC2_AddressBase [14/43]

#define ADC2_AddressBase 0x5400

Definition at line 78 of file STM8AF6289.h.

◆ ADC2_AddressBase [15/43]

#define ADC2_AddressBase 0x5400

Definition at line 78 of file STM8AF528A.h.

◆ ADC2_AddressBase [16/43]

#define ADC2_AddressBase 0x5400

Definition at line 78 of file STM8AF628A.h.

◆ ADC2_AddressBase [17/43]

#define ADC2_AddressBase 0x5400

Definition at line 78 of file STM8AF62A6.h.

◆ ADC2_AddressBase [18/43]

#define ADC2_AddressBase 0x5400

Definition at line 78 of file STM8AF5268.h.

◆ ADC2_AddressBase [19/43]

#define ADC2_AddressBase 0x5400

Definition at line 78 of file STM8S207C6.h.

◆ ADC2_AddressBase [20/43]

#define ADC2_AddressBase 0x5400

Definition at line 78 of file STM8S207C8.h.

◆ ADC2_AddressBase [21/43]

#define ADC2_AddressBase 0x5400

Definition at line 78 of file STM8S207CB.h.

◆ ADC2_AddressBase [22/43]

#define ADC2_AddressBase 0x5400

Definition at line 78 of file STM8AF5286.h.

◆ ADC2_AddressBase [23/43]

#define ADC2_AddressBase 0x5400

Definition at line 78 of file STM8AF62A8.h.

◆ ADC2_AddressBase [24/43]

#define ADC2_AddressBase 0x5400

Definition at line 78 of file STM8S207K6.h.

◆ ADC2_AddressBase [25/43]

#define ADC2_AddressBase 0x5400

Definition at line 78 of file STM8S207K8.h.

◆ ADC2_AddressBase [26/43]

#define ADC2_AddressBase 0x5400

Definition at line 78 of file STM8S207M8.h.

◆ ADC2_AddressBase [27/43]

#define ADC2_AddressBase 0x5400

Definition at line 78 of file STM8S207MB.h.

◆ ADC2_AddressBase [28/43]

#define ADC2_AddressBase 0x5400

Definition at line 78 of file STM8AF62A9.h.

◆ ADC2_AddressBase [29/43]

#define ADC2_AddressBase 0x5400

Definition at line 78 of file STM8AF52A6.h.

◆ ADC2_AddressBase [30/43]

#define ADC2_AddressBase 0x5400

Definition at line 78 of file STM8S207R6.h.

◆ ADC2_AddressBase [31/43]

#define ADC2_AddressBase 0x5400

Definition at line 78 of file STM8S207R8.h.

◆ ADC2_AddressBase [32/43]

#define ADC2_AddressBase 0x5400

Definition at line 78 of file STM8S207RB.h.

◆ ADC2_AddressBase [33/43]

#define ADC2_AddressBase 0x5400

Definition at line 78 of file STM8AF62AA.h.

◆ ADC2_AddressBase [34/43]

#define ADC2_AddressBase 0x5400

Definition at line 78 of file STM8S207S6.h.

◆ ADC2_AddressBase [35/43]

#define ADC2_AddressBase 0x5400

Definition at line 78 of file STM8S207S8.h.

◆ ADC2_AddressBase [36/43]

#define ADC2_AddressBase 0x5400

Definition at line 78 of file STM8S207SB.h.

◆ ADC2_AddressBase [37/43]

#define ADC2_AddressBase 0x5400

Definition at line 78 of file STM8S208C6.h.

◆ ADC2_AddressBase [38/43]

#define ADC2_AddressBase 0x5400

Definition at line 78 of file STM8S208C8.h.

◆ ADC2_AddressBase [39/43]

#define ADC2_AddressBase 0x5400

Definition at line 78 of file STM8S208MB.h.

◆ ADC2_AddressBase [40/43]

#define ADC2_AddressBase 0x5400

Definition at line 78 of file STM8AF6388.h.

◆ ADC2_AddressBase [41/43]

#define ADC2_AddressBase 0x5400

Definition at line 78 of file STM8S208R6.h.

◆ ADC2_AddressBase [42/43]

#define ADC2_AddressBase 0x5400

Definition at line 78 of file STM8S208RB.h.

◆ ADC2_AddressBase [43/43]

#define ADC2_AddressBase 0x5400

Definition at line 78 of file STM8S208S6.h.

◆ AWU_AddressBase [1/70]

#define AWU_AddressBase 0x50F0

Definition at line 65 of file STM8S103K3.h.

◆ AWU_AddressBase [2/70]

#define AWU_AddressBase 0x50F0

Definition at line 65 of file STM8S903F3.h.

◆ AWU_AddressBase [3/70]

#define AWU_AddressBase 0x50F0

Definition at line 65 of file STM8S903K3.h.

◆ AWU_AddressBase [4/70]

#define AWU_AddressBase 0x50F0

Definition at line 65 of file STM8S001J3.h.

◆ AWU_AddressBase [5/70]

#define AWU_AddressBase 0x50F0

Definition at line 65 of file STM8S003F3.h.

◆ AWU_AddressBase [6/70]

#define AWU_AddressBase 0x50F0

Definition at line 65 of file STM8S003K3.h.

◆ AWU_AddressBase [7/70]

#define AWU_AddressBase 0x50F0

Definition at line 65 of file STM8AF6213.h.

◆ AWU_AddressBase [8/70]

#define AWU_AddressBase 0x50F0

Definition at line 65 of file STM8S103F2.h.

◆ AWU_AddressBase [9/70]

#define AWU_AddressBase 0x50F0

Definition at line 65 of file STM8S103F3.h.

◆ AWU_AddressBase [10/70]

#define AWU_AddressBase 0x50F0

Definition at line 65 of file STM8AF6213A.h.

◆ AWU_AddressBase [11/70]

#define AWU_AddressBase 0x50F0

Definition at line 65 of file STM8AF6223.h.

◆ AWU_AddressBase [12/70]

#define AWU_AddressBase 0x50F0

Definition at line 65 of file STM8AF6223A.h.

◆ AWU_AddressBase [13/70]

#define AWU_AddressBase 0x50F0

Definition at line 65 of file STM8AF6366.h.

◆ AWU_AddressBase [14/70]

#define AWU_AddressBase 0x50F0

Definition at line 65 of file STM8AF6226.h.

◆ AWU_AddressBase [15/70]

#define AWU_AddressBase 0x50F0

Definition at line 66 of file STM8AF6246.h.

◆ AWU_AddressBase [16/70]

#define AWU_AddressBase 0x50F0

Definition at line 66 of file STM8S005K6.h.

◆ AWU_AddressBase [17/70]

#define AWU_AddressBase 0x50F0

Definition at line 66 of file STM8AF6248.h.

◆ AWU_AddressBase [18/70]

#define AWU_AddressBase 0x50F0

Definition at line 66 of file STM8AF6266.h.

◆ AWU_AddressBase [19/70]

#define AWU_AddressBase 0x50F0

Definition at line 66 of file STM8AF6268.h.

◆ AWU_AddressBase [20/70]

#define AWU_AddressBase 0x50F0

Definition at line 66 of file STM8AF6269.h.

◆ AWU_AddressBase [21/70]

#define AWU_AddressBase 0x50F0

Definition at line 66 of file STM8S005C6.h.

◆ AWU_AddressBase [22/70]

#define AWU_AddressBase 0x50F0

Definition at line 66 of file STM8S105C6.h.

◆ AWU_AddressBase [23/70]

#define AWU_AddressBase 0x50F0

Definition at line 66 of file STM8S105K4.h.

◆ AWU_AddressBase [24/70]

#define AWU_AddressBase 0x50F0

Definition at line 66 of file STM8S105K6.h.

◆ AWU_AddressBase [25/70]

#define AWU_AddressBase 0x50F0

Definition at line 66 of file STM8S105S4.h.

◆ AWU_AddressBase [26/70]

#define AWU_AddressBase 0x50F0

Definition at line 66 of file STM8S105S6.h.

◆ AWU_AddressBase [27/70]

#define AWU_AddressBase 0x50F0

Definition at line 66 of file STM8S105C4.h.

◆ AWU_AddressBase [28/70]

#define AWU_AddressBase 0x50F0

Definition at line 68 of file STM8S208S8.h.

◆ AWU_AddressBase [29/70]

#define AWU_AddressBase 0x50F0

Definition at line 68 of file STM8S208SB.h.

◆ AWU_AddressBase [30/70]

#define AWU_AddressBase 0x50F0

Definition at line 68 of file STM8AF52A8.h.

◆ AWU_AddressBase [31/70]

#define AWU_AddressBase 0x50F0

Definition at line 68 of file STM8S207R8.h.

◆ AWU_AddressBase [32/70]

#define AWU_AddressBase 0x50F0

Definition at line 68 of file STM8AF5288.h.

◆ AWU_AddressBase [33/70]

#define AWU_AddressBase 0x50F0

Definition at line 68 of file STM8AF5268.h.

◆ AWU_AddressBase [34/70]

#define AWU_AddressBase 0x50F0

Definition at line 68 of file STM8S207S6.h.

◆ AWU_AddressBase [35/70]

#define AWU_AddressBase 0x50F0

Definition at line 68 of file STM8AF52A9.h.

◆ AWU_AddressBase [36/70]

#define AWU_AddressBase 0x50F0

Definition at line 68 of file STM8S207CB.h.

◆ AWU_AddressBase [37/70]

#define AWU_AddressBase 0x50F0

Definition at line 68 of file STM8AF5289.h.

◆ AWU_AddressBase [38/70]

#define AWU_AddressBase 0x50F0

Definition at line 68 of file STM8S208S6.h.

◆ AWU_AddressBase [39/70]

#define AWU_AddressBase 0x50F0

Definition at line 68 of file STM8S208R6.h.

◆ AWU_AddressBase [40/70]

#define AWU_AddressBase 0x50F0

Definition at line 68 of file STM8AF52AA.h.

◆ AWU_AddressBase [41/70]

#define AWU_AddressBase 0x50F0

Definition at line 68 of file STM8AF6286.h.

◆ AWU_AddressBase [42/70]

#define AWU_AddressBase 0x50F0

Definition at line 68 of file STM8S207MB.h.

◆ AWU_AddressBase [43/70]

#define AWU_AddressBase 0x50F0

Definition at line 68 of file STM8AF5286.h.

◆ AWU_AddressBase [44/70]

#define AWU_AddressBase 0x50F0

Definition at line 68 of file STM8S207K8.h.

◆ AWU_AddressBase [45/70]

#define AWU_AddressBase 0x50F0

Definition at line 68 of file STM8AF6288.h.

◆ AWU_AddressBase [46/70]

#define AWU_AddressBase 0x50F0

Definition at line 68 of file STM8AF6289.h.

◆ AWU_AddressBase [47/70]

#define AWU_AddressBase 0x50F0

Definition at line 68 of file STM8S007C8.h.

◆ AWU_AddressBase [48/70]

#define AWU_AddressBase 0x50F0

Definition at line 68 of file STM8AF528A.h.

◆ AWU_AddressBase [49/70]

#define AWU_AddressBase 0x50F0

Definition at line 68 of file STM8AF628A.h.

◆ AWU_AddressBase [50/70]

#define AWU_AddressBase 0x50F0

Definition at line 68 of file STM8AF5269.h.

◆ AWU_AddressBase [51/70]

#define AWU_AddressBase 0x50F0

Definition at line 68 of file STM8AF62A6.h.

◆ AWU_AddressBase [52/70]

#define AWU_AddressBase 0x50F0

Definition at line 68 of file STM8S207C8.h.

◆ AWU_AddressBase [53/70]

#define AWU_AddressBase 0x50F0

Definition at line 68 of file STM8S207K6.h.

◆ AWU_AddressBase [54/70]

#define AWU_AddressBase 0x50F0

Definition at line 68 of file STM8AF62A8.h.

◆ AWU_AddressBase [55/70]

#define AWU_AddressBase 0x50F0

Definition at line 68 of file STM8S207M8.h.

◆ AWU_AddressBase [56/70]

#define AWU_AddressBase 0x50F0

Definition at line 68 of file STM8S207R6.h.

◆ AWU_AddressBase [57/70]

#define AWU_AddressBase 0x50F0

Definition at line 68 of file STM8AF62A9.h.

◆ AWU_AddressBase [58/70]

#define AWU_AddressBase 0x50F0

Definition at line 68 of file STM8S207RB.h.

◆ AWU_AddressBase [59/70]

#define AWU_AddressBase 0x50F0

Definition at line 68 of file STM8AF62AA.h.

◆ AWU_AddressBase [60/70]

#define AWU_AddressBase 0x50F0

Definition at line 68 of file STM8S207S8.h.

◆ AWU_AddressBase [61/70]

#define AWU_AddressBase 0x50F0

Definition at line 68 of file STM8S207SB.h.

◆ AWU_AddressBase [62/70]

#define AWU_AddressBase 0x50F0

Definition at line 68 of file STM8S208C6.h.

◆ AWU_AddressBase [63/70]

#define AWU_AddressBase 0x50F0

Definition at line 68 of file STM8S208C8.h.

◆ AWU_AddressBase [64/70]

#define AWU_AddressBase 0x50F0

Definition at line 68 of file STM8S208CB.h.

◆ AWU_AddressBase [65/70]

#define AWU_AddressBase 0x50F0

Definition at line 68 of file STM8S207C6.h.

◆ AWU_AddressBase [66/70]

#define AWU_AddressBase 0x50F0

Definition at line 68 of file STM8S208MB.h.

◆ AWU_AddressBase [67/70]

#define AWU_AddressBase 0x50F0

Definition at line 68 of file STM8AF6388.h.

◆ AWU_AddressBase [68/70]

#define AWU_AddressBase 0x50F0

Definition at line 68 of file STM8S208R8.h.

◆ AWU_AddressBase [69/70]

#define AWU_AddressBase 0x50F0

Definition at line 68 of file STM8AF52A6.h.

◆ AWU_AddressBase [70/70]

#define AWU_AddressBase 0x50F0

Definition at line 68 of file STM8S208RB.h.

◆ BEEP_AddressBase [1/70]

#define BEEP_AddressBase 0x50F3

Definition at line 66 of file STM8S903F3.h.

◆ BEEP_AddressBase [2/70]

#define BEEP_AddressBase 0x50F3

Definition at line 66 of file STM8S903K3.h.

◆ BEEP_AddressBase [3/70]

#define BEEP_AddressBase 0x50F3

Definition at line 66 of file STM8AF6223A.h.

◆ BEEP_AddressBase [4/70]

#define BEEP_AddressBase 0x50F3

Definition at line 66 of file STM8S001J3.h.

◆ BEEP_AddressBase [5/70]

#define BEEP_AddressBase 0x50F3

Definition at line 66 of file STM8S003F3.h.

◆ BEEP_AddressBase [6/70]

#define BEEP_AddressBase 0x50F3

Definition at line 66 of file STM8S003K3.h.

◆ BEEP_AddressBase [7/70]

#define BEEP_AddressBase 0x50F3

Definition at line 66 of file STM8AF6213.h.

◆ BEEP_AddressBase [8/70]

#define BEEP_AddressBase 0x50F3

Definition at line 66 of file STM8S103F2.h.

◆ BEEP_AddressBase [9/70]

#define BEEP_AddressBase 0x50F3

Definition at line 66 of file STM8S103F3.h.

◆ BEEP_AddressBase [10/70]

#define BEEP_AddressBase 0x50F3

Definition at line 66 of file STM8S103K3.h.

◆ BEEP_AddressBase [11/70]

#define BEEP_AddressBase 0x50F3

Definition at line 66 of file STM8AF6213A.h.

◆ BEEP_AddressBase [12/70]

#define BEEP_AddressBase 0x50F3

Definition at line 66 of file STM8AF6223.h.

◆ BEEP_AddressBase [13/70]

#define BEEP_AddressBase 0x50F3

Definition at line 66 of file STM8AF6366.h.

◆ BEEP_AddressBase [14/70]

#define BEEP_AddressBase 0x50F3

Definition at line 66 of file STM8AF6226.h.

◆ BEEP_AddressBase [15/70]

#define BEEP_AddressBase 0x50F3

Definition at line 67 of file STM8AF6246.h.

◆ BEEP_AddressBase [16/70]

#define BEEP_AddressBase 0x50F3

Definition at line 67 of file STM8AF6248.h.

◆ BEEP_AddressBase [17/70]

#define BEEP_AddressBase 0x50F3

Definition at line 67 of file STM8AF6266.h.

◆ BEEP_AddressBase [18/70]

#define BEEP_AddressBase 0x50F3

Definition at line 67 of file STM8AF6268.h.

◆ BEEP_AddressBase [19/70]

#define BEEP_AddressBase 0x50F3

Definition at line 67 of file STM8AF6269.h.

◆ BEEP_AddressBase [20/70]

#define BEEP_AddressBase 0x50F3

Definition at line 67 of file STM8S005C6.h.

◆ BEEP_AddressBase [21/70]

#define BEEP_AddressBase 0x50F3

Definition at line 67 of file STM8S005K6.h.

◆ BEEP_AddressBase [22/70]

#define BEEP_AddressBase 0x50F3

Definition at line 67 of file STM8S105C4.h.

◆ BEEP_AddressBase [23/70]

#define BEEP_AddressBase 0x50F3

Definition at line 67 of file STM8S105C6.h.

◆ BEEP_AddressBase [24/70]

#define BEEP_AddressBase 0x50F3

Definition at line 67 of file STM8S105K4.h.

◆ BEEP_AddressBase [25/70]

#define BEEP_AddressBase 0x50F3

Definition at line 67 of file STM8S105K6.h.

◆ BEEP_AddressBase [26/70]

#define BEEP_AddressBase 0x50F3

Definition at line 67 of file STM8S105S4.h.

◆ BEEP_AddressBase [27/70]

#define BEEP_AddressBase 0x50F3

Definition at line 67 of file STM8S105S6.h.

◆ BEEP_AddressBase [28/70]

#define BEEP_AddressBase 0x50F3

Definition at line 69 of file STM8S208S8.h.

◆ BEEP_AddressBase [29/70]

#define BEEP_AddressBase 0x50F3

Definition at line 69 of file STM8AF5288.h.

◆ BEEP_AddressBase [30/70]

#define BEEP_AddressBase 0x50F3

Definition at line 69 of file STM8AF5268.h.

◆ BEEP_AddressBase [31/70]

#define BEEP_AddressBase 0x50F3

Definition at line 69 of file STM8AF52A8.h.

◆ BEEP_AddressBase [32/70]

#define BEEP_AddressBase 0x50F3

Definition at line 69 of file STM8S208SB.h.

◆ BEEP_AddressBase [33/70]

#define BEEP_AddressBase 0x50F3

Definition at line 69 of file STM8AF52A9.h.

◆ BEEP_AddressBase [34/70]

#define BEEP_AddressBase 0x50F3

Definition at line 69 of file STM8S208CB.h.

◆ BEEP_AddressBase [35/70]

#define BEEP_AddressBase 0x50F3

Definition at line 69 of file STM8S208R8.h.

◆ BEEP_AddressBase [36/70]

#define BEEP_AddressBase 0x50F3

Definition at line 69 of file STM8AF5289.h.

◆ BEEP_AddressBase [37/70]

#define BEEP_AddressBase 0x50F3

Definition at line 69 of file STM8S208S6.h.

◆ BEEP_AddressBase [38/70]

#define BEEP_AddressBase 0x50F3

Definition at line 69 of file STM8S208MB.h.

◆ BEEP_AddressBase [39/70]

#define BEEP_AddressBase 0x50F3

Definition at line 69 of file STM8AF52AA.h.

◆ BEEP_AddressBase [40/70]

#define BEEP_AddressBase 0x50F3

Definition at line 69 of file STM8AF6286.h.

◆ BEEP_AddressBase [41/70]

#define BEEP_AddressBase 0x50F3

Definition at line 69 of file STM8AF5286.h.

◆ BEEP_AddressBase [42/70]

#define BEEP_AddressBase 0x50F3

Definition at line 69 of file STM8AF6288.h.

◆ BEEP_AddressBase [43/70]

#define BEEP_AddressBase 0x50F3

Definition at line 69 of file STM8S007C8.h.

◆ BEEP_AddressBase [44/70]

#define BEEP_AddressBase 0x50F3

Definition at line 69 of file STM8AF6289.h.

◆ BEEP_AddressBase [45/70]

#define BEEP_AddressBase 0x50F3

Definition at line 69 of file STM8AF628A.h.

◆ BEEP_AddressBase [46/70]

#define BEEP_AddressBase 0x50F3

Definition at line 69 of file STM8AF528A.h.

◆ BEEP_AddressBase [47/70]

#define BEEP_AddressBase 0x50F3

Definition at line 69 of file STM8AF62A6.h.

◆ BEEP_AddressBase [48/70]

#define BEEP_AddressBase 0x50F3

Definition at line 69 of file STM8S207C6.h.

◆ BEEP_AddressBase [49/70]

#define BEEP_AddressBase 0x50F3

Definition at line 69 of file STM8S207C8.h.

◆ BEEP_AddressBase [50/70]

#define BEEP_AddressBase 0x50F3

Definition at line 69 of file STM8S207CB.h.

◆ BEEP_AddressBase [51/70]

#define BEEP_AddressBase 0x50F3

Definition at line 69 of file STM8S207K6.h.

◆ BEEP_AddressBase [52/70]

#define BEEP_AddressBase 0x50F3

Definition at line 69 of file STM8AF62A8.h.

◆ BEEP_AddressBase [53/70]

#define BEEP_AddressBase 0x50F3

Definition at line 69 of file STM8S207K8.h.

◆ BEEP_AddressBase [54/70]

#define BEEP_AddressBase 0x50F3

Definition at line 69 of file STM8S207M8.h.

◆ BEEP_AddressBase [55/70]

#define BEEP_AddressBase 0x50F3

Definition at line 69 of file STM8S207MB.h.

◆ BEEP_AddressBase [56/70]

#define BEEP_AddressBase 0x50F3

Definition at line 69 of file STM8AF62A9.h.

◆ BEEP_AddressBase [57/70]

#define BEEP_AddressBase 0x50F3

Definition at line 69 of file STM8S207R6.h.

◆ BEEP_AddressBase [58/70]

#define BEEP_AddressBase 0x50F3

Definition at line 69 of file STM8S207R8.h.

◆ BEEP_AddressBase [59/70]

#define BEEP_AddressBase 0x50F3

Definition at line 69 of file STM8S207RB.h.

◆ BEEP_AddressBase [60/70]

#define BEEP_AddressBase 0x50F3

Definition at line 69 of file STM8S207S6.h.

◆ BEEP_AddressBase [61/70]

#define BEEP_AddressBase 0x50F3

Definition at line 69 of file STM8AF52A6.h.

◆ BEEP_AddressBase [62/70]

#define BEEP_AddressBase 0x50F3

Definition at line 69 of file STM8S207S8.h.

◆ BEEP_AddressBase [63/70]

#define BEEP_AddressBase 0x50F3

Definition at line 69 of file STM8AF5269.h.

◆ BEEP_AddressBase [64/70]

#define BEEP_AddressBase 0x50F3

Definition at line 69 of file STM8AF62AA.h.

◆ BEEP_AddressBase [65/70]

#define BEEP_AddressBase 0x50F3

Definition at line 69 of file STM8S207SB.h.

◆ BEEP_AddressBase [66/70]

#define BEEP_AddressBase 0x50F3

Definition at line 69 of file STM8S208C6.h.

◆ BEEP_AddressBase [67/70]

#define BEEP_AddressBase 0x50F3

Definition at line 69 of file STM8S208C8.h.

◆ BEEP_AddressBase [68/70]

#define BEEP_AddressBase 0x50F3

Definition at line 69 of file STM8S208R6.h.

◆ BEEP_AddressBase [69/70]

#define BEEP_AddressBase 0x50F3

Definition at line 69 of file STM8AF6388.h.

◆ BEEP_AddressBase [70/70]

#define BEEP_AddressBase 0x50F3

Definition at line 69 of file STM8S208RB.h.

◆ CAN_AddressBase [1/20]

#define CAN_AddressBase 0x5420

Definition at line 79 of file STM8AF5269.h.

◆ CAN_AddressBase [2/20]

#define CAN_AddressBase 0x5420

Definition at line 79 of file STM8AF5288.h.

◆ CAN_AddressBase [3/20]

#define CAN_AddressBase 0x5420

Definition at line 79 of file STM8AF5268.h.

◆ CAN_AddressBase [4/20]

#define CAN_AddressBase 0x5420

Definition at line 79 of file STM8AF52A8.h.

◆ CAN_AddressBase [5/20]

#define CAN_AddressBase 0x5420

Definition at line 79 of file STM8S208SB.h.

◆ CAN_AddressBase [6/20]

#define CAN_AddressBase 0x5420

Definition at line 79 of file STM8S208S8.h.

◆ CAN_AddressBase [7/20]

#define CAN_AddressBase 0x5420

Definition at line 79 of file STM8S208R8.h.

◆ CAN_AddressBase [8/20]

#define CAN_AddressBase 0x5420

Definition at line 79 of file STM8AF52A9.h.

◆ CAN_AddressBase [9/20]

#define CAN_AddressBase 0x5420

Definition at line 79 of file STM8S208MB.h.

◆ CAN_AddressBase [10/20]

#define CAN_AddressBase 0x5420

Definition at line 79 of file STM8S208C8.h.

◆ CAN_AddressBase [11/20]

#define CAN_AddressBase 0x5420

Definition at line 79 of file STM8S208S6.h.

◆ CAN_AddressBase [12/20]

#define CAN_AddressBase 0x5420

Definition at line 79 of file STM8S208C6.h.

◆ CAN_AddressBase [13/20]

#define CAN_AddressBase 0x5420

Definition at line 79 of file STM8AF52AA.h.

◆ CAN_AddressBase [14/20]

#define CAN_AddressBase 0x5420

Definition at line 79 of file STM8AF5289.h.

◆ CAN_AddressBase [15/20]

#define CAN_AddressBase 0x5420

Definition at line 79 of file STM8AF5286.h.

◆ CAN_AddressBase [16/20]

#define CAN_AddressBase 0x5420

Definition at line 79 of file STM8AF528A.h.

◆ CAN_AddressBase [17/20]

#define CAN_AddressBase 0x5420

Definition at line 79 of file STM8S208CB.h.

◆ CAN_AddressBase [18/20]

#define CAN_AddressBase 0x5420

Definition at line 79 of file STM8S208R6.h.

◆ CAN_AddressBase [19/20]

#define CAN_AddressBase 0x5420

Definition at line 79 of file STM8AF52A6.h.

◆ CAN_AddressBase [20/20]

#define CAN_AddressBase 0x5420

Definition at line 79 of file STM8S208RB.h.

◆ CFG_AddressBase [1/70]

#define CFG_AddressBase 0x7F60

Definition at line 74 of file STM8S903F3.h.

◆ CFG_AddressBase [2/70]

#define CFG_AddressBase 0x7F60

Definition at line 74 of file STM8S903K3.h.

◆ CFG_AddressBase [3/70]

#define CFG_AddressBase 0x7F60

Definition at line 74 of file STM8S001J3.h.

◆ CFG_AddressBase [4/70]

#define CFG_AddressBase 0x7F60

Definition at line 74 of file STM8S003F3.h.

◆ CFG_AddressBase [5/70]

#define CFG_AddressBase 0x7F60

Definition at line 74 of file STM8S003K3.h.

◆ CFG_AddressBase [6/70]

#define CFG_AddressBase 0x7F60

Definition at line 74 of file STM8S103F2.h.

◆ CFG_AddressBase [7/70]

#define CFG_AddressBase 0x7F60

Definition at line 74 of file STM8AF6213.h.

◆ CFG_AddressBase [8/70]

#define CFG_AddressBase 0x7F60

Definition at line 74 of file STM8S103K3.h.

◆ CFG_AddressBase [9/70]

#define CFG_AddressBase 0x7F60

Definition at line 74 of file STM8AF6213A.h.

◆ CFG_AddressBase [10/70]

#define CFG_AddressBase 0x7F60

Definition at line 74 of file STM8AF6223.h.

◆ CFG_AddressBase [11/70]

#define CFG_AddressBase 0x7F60

Definition at line 74 of file STM8AF6223A.h.

◆ CFG_AddressBase [12/70]

#define CFG_AddressBase 0x7F60

Definition at line 74 of file STM8S103F3.h.

◆ CFG_AddressBase [13/70]

#define CFG_AddressBase 0x7F60

Definition at line 74 of file STM8AF6226.h.

◆ CFG_AddressBase [14/70]

#define CFG_AddressBase 0x7F60

Definition at line 75 of file STM8AF6366.h.

◆ CFG_AddressBase [15/70]

#define CFG_AddressBase 0x7F60

Definition at line 76 of file STM8AF6246.h.

◆ CFG_AddressBase [16/70]

#define CFG_AddressBase 0x7F60

Definition at line 76 of file STM8S005K6.h.

◆ CFG_AddressBase [17/70]

#define CFG_AddressBase 0x7F60

Definition at line 76 of file STM8S005C6.h.

◆ CFG_AddressBase [18/70]

#define CFG_AddressBase 0x7F60

Definition at line 76 of file STM8AF6248.h.

◆ CFG_AddressBase [19/70]

#define CFG_AddressBase 0x7F60

Definition at line 76 of file STM8AF6266.h.

◆ CFG_AddressBase [20/70]

#define CFG_AddressBase 0x7F60

Definition at line 76 of file STM8AF6268.h.

◆ CFG_AddressBase [21/70]

#define CFG_AddressBase 0x7F60

Definition at line 76 of file STM8AF6269.h.

◆ CFG_AddressBase [22/70]

#define CFG_AddressBase 0x7F60

Definition at line 76 of file STM8S105C6.h.

◆ CFG_AddressBase [23/70]

#define CFG_AddressBase 0x7F60

Definition at line 76 of file STM8S105K6.h.

◆ CFG_AddressBase [24/70]

#define CFG_AddressBase 0x7F60

Definition at line 76 of file STM8S105C4.h.

◆ CFG_AddressBase [25/70]

#define CFG_AddressBase 0x7F60

Definition at line 76 of file STM8S105S4.h.

◆ CFG_AddressBase [26/70]

#define CFG_AddressBase 0x7F60

Definition at line 76 of file STM8S105S6.h.

◆ CFG_AddressBase [27/70]

#define CFG_AddressBase 0x7F60

Definition at line 76 of file STM8S105K4.h.

◆ CFG_AddressBase [28/70]

#define CFG_AddressBase 0x7F60

Definition at line 79 of file STM8S207S8.h.

◆ CFG_AddressBase [29/70]

#define CFG_AddressBase 0x7F60

Definition at line 79 of file STM8AF6286.h.

◆ CFG_AddressBase [30/70]

#define CFG_AddressBase 0x7F60

Definition at line 79 of file STM8S207K6.h.

◆ CFG_AddressBase [31/70]

#define CFG_AddressBase 0x7F60

Definition at line 79 of file STM8S207M8.h.

◆ CFG_AddressBase [32/70]

#define CFG_AddressBase 0x7F60

Definition at line 79 of file STM8S207R6.h.

◆ CFG_AddressBase [33/70]

#define CFG_AddressBase 0x7F60

Definition at line 79 of file STM8AF6288.h.

◆ CFG_AddressBase [34/70]

#define CFG_AddressBase 0x7F60

Definition at line 79 of file STM8S007C8.h.

◆ CFG_AddressBase [35/70]

#define CFG_AddressBase 0x7F60

Definition at line 79 of file STM8AF628A.h.

◆ CFG_AddressBase [36/70]

#define CFG_AddressBase 0x7F60

Definition at line 79 of file STM8AF62A6.h.

◆ CFG_AddressBase [37/70]

#define CFG_AddressBase 0x7F60

Definition at line 79 of file STM8S207C6.h.

◆ CFG_AddressBase [38/70]

#define CFG_AddressBase 0x7F60

Definition at line 79 of file STM8S207C8.h.

◆ CFG_AddressBase [39/70]

#define CFG_AddressBase 0x7F60

Definition at line 79 of file STM8S207CB.h.

◆ CFG_AddressBase [40/70]

#define CFG_AddressBase 0x7F60

Definition at line 79 of file STM8AF62A8.h.

◆ CFG_AddressBase [41/70]

#define CFG_AddressBase 0x7F60

Definition at line 79 of file STM8S207K8.h.

◆ CFG_AddressBase [42/70]

#define CFG_AddressBase 0x7F60

Definition at line 79 of file STM8S207MB.h.

◆ CFG_AddressBase [43/70]

#define CFG_AddressBase 0x7F60

Definition at line 79 of file STM8S207R8.h.

◆ CFG_AddressBase [44/70]

#define CFG_AddressBase 0x7F60

Definition at line 79 of file STM8AF62A9.h.

◆ CFG_AddressBase [45/70]

#define CFG_AddressBase 0x7F60

Definition at line 79 of file STM8S207RB.h.

◆ CFG_AddressBase [46/70]

#define CFG_AddressBase 0x7F60

Definition at line 79 of file STM8S207S6.h.

◆ CFG_AddressBase [47/70]

#define CFG_AddressBase 0x7F60

Definition at line 79 of file STM8AF62AA.h.

◆ CFG_AddressBase [48/70]

#define CFG_AddressBase 0x7F60

Definition at line 79 of file STM8S207SB.h.

◆ CFG_AddressBase [49/70]

#define CFG_AddressBase 0x7F60

Definition at line 79 of file STM8AF6388.h.

◆ CFG_AddressBase [50/70]

#define CFG_AddressBase 0x7F60

Definition at line 79 of file STM8AF6289.h.

◆ CFG_AddressBase [51/70]

#define CFG_AddressBase 0x7F60

Definition at line 80 of file STM8S208SB.h.

◆ CFG_AddressBase [52/70]

#define CFG_AddressBase 0x7F60

Definition at line 80 of file STM8AF5268.h.

◆ CFG_AddressBase [53/70]

#define CFG_AddressBase 0x7F60

Definition at line 80 of file STM8AF5269.h.

◆ CFG_AddressBase [54/70]

#define CFG_AddressBase 0x7F60

Definition at line 80 of file STM8AF5288.h.

◆ CFG_AddressBase [55/70]

#define CFG_AddressBase 0x7F60

Definition at line 80 of file STM8AF52A8.h.

◆ CFG_AddressBase [56/70]

#define CFG_AddressBase 0x7F60

Definition at line 80 of file STM8S208S8.h.

◆ CFG_AddressBase [57/70]

#define CFG_AddressBase 0x7F60

Definition at line 80 of file STM8S208R6.h.

◆ CFG_AddressBase [58/70]

#define CFG_AddressBase 0x7F60

Definition at line 80 of file STM8AF52A9.h.

◆ CFG_AddressBase [59/70]

#define CFG_AddressBase 0x7F60

Definition at line 80 of file STM8S208RB.h.

◆ CFG_AddressBase [60/70]

#define CFG_AddressBase 0x7F60

Definition at line 80 of file STM8AF5286.h.

◆ CFG_AddressBase [61/70]

#define CFG_AddressBase 0x7F60

Definition at line 80 of file STM8S208C6.h.

◆ CFG_AddressBase [62/70]

#define CFG_AddressBase 0x7F60

Definition at line 80 of file STM8AF5289.h.

◆ CFG_AddressBase [63/70]

#define CFG_AddressBase 0x7F60

Definition at line 80 of file STM8AF52AA.h.

◆ CFG_AddressBase [64/70]

#define CFG_AddressBase 0x7F60

Definition at line 80 of file STM8AF528A.h.

◆ CFG_AddressBase [65/70]

#define CFG_AddressBase 0x7F60

Definition at line 80 of file STM8S208C8.h.

◆ CFG_AddressBase [66/70]

#define CFG_AddressBase 0x7F60

Definition at line 80 of file STM8S208CB.h.

◆ CFG_AddressBase [67/70]

#define CFG_AddressBase 0x7F60

Definition at line 80 of file STM8S208MB.h.

◆ CFG_AddressBase [68/70]

#define CFG_AddressBase 0x7F60

Definition at line 80 of file STM8AF52A6.h.

◆ CFG_AddressBase [69/70]

#define CFG_AddressBase 0x7F60

Definition at line 80 of file STM8S208R8.h.